decoder.isa revision 5094
13900Ssaidi@eecs.umich.edu// Copyright (c) 2006-2007 The Regents of The University of Michigan 22632Sstever@eecs.umich.edu// All rights reserved. 32632Sstever@eecs.umich.edu// 42632Sstever@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 52632Sstever@eecs.umich.edu// modification, are permitted provided that the following conditions are 62632Sstever@eecs.umich.edu// met: redistributions of source code must retain the above copyright 72632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 82632Sstever@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 92632Sstever@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 102632Sstever@eecs.umich.edu// documentation and/or other materials provided with the distribution; 112632Sstever@eecs.umich.edu// neither the name of the copyright holders nor the names of its 122632Sstever@eecs.umich.edu// contributors may be used to endorse or promote products derived from 132632Sstever@eecs.umich.edu// this software without specific prior written permission. 142632Sstever@eecs.umich.edu// 152632Sstever@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162632Sstever@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172632Sstever@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182632Sstever@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192632Sstever@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202632Sstever@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212632Sstever@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222632Sstever@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232632Sstever@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242632Sstever@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252632Sstever@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262632Sstever@eecs.umich.edu// 272632Sstever@eecs.umich.edu// Authors: Ali Saidi 282632Sstever@eecs.umich.edu// Gabe Black 292632Sstever@eecs.umich.edu// Steve Reinhardt 302632Sstever@eecs.umich.edu 312022SN/A//////////////////////////////////////////////////////////////////// 322022SN/A// 332022SN/A// The actual decoder specification 342022SN/A// 352022SN/A 362469SN/Adecode OP default Unknown::unknown() 372469SN/A{ 382469SN/A 0x0: decode OP2 392469SN/A { 402516SN/A //Throw an illegal instruction acception 412516SN/A 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 422944Sgblack@eecs.umich.edu format BranchN 432482SN/A { 443598Sgblack@eecs.umich.edu //bpcc 453056Sgblack@eecs.umich.edu 0x1: decode COND2 462469SN/A { 473056Sgblack@eecs.umich.edu //Branch Always 485091Sgblack@eecs.umich.edu 0x8: bpa(19, annul_code={{ 495091Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 505091Sgblack@eecs.umich.edu NNPC = NPC + 4; 515091Sgblack@eecs.umich.edu }}); 523056Sgblack@eecs.umich.edu //Branch Never 535091Sgblack@eecs.umich.edu 0x0: bpn(19, {{;}}, 545091Sgblack@eecs.umich.edu annul_code={{ 555091Sgblack@eecs.umich.edu NNPC = NPC + 8; 565091Sgblack@eecs.umich.edu NPC = NPC + 4; 575091Sgblack@eecs.umich.edu }}); 583056Sgblack@eecs.umich.edu default: decode BPCC 593056Sgblack@eecs.umich.edu { 605091Sgblack@eecs.umich.edu 0x0: bpcci(19, test={{passesCondition(Ccr<3:0>, COND2)}}); 615091Sgblack@eecs.umich.edu 0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}}); 623056Sgblack@eecs.umich.edu } 632482SN/A } 643598Sgblack@eecs.umich.edu //bicc 653598Sgblack@eecs.umich.edu 0x2: decode COND2 663598Sgblack@eecs.umich.edu { 673598Sgblack@eecs.umich.edu //Branch Always 685091Sgblack@eecs.umich.edu 0x8: ba(22, annul_code={{ 695091Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 705091Sgblack@eecs.umich.edu NNPC = NPC + 4; 715091Sgblack@eecs.umich.edu }}); 723598Sgblack@eecs.umich.edu //Branch Never 735091Sgblack@eecs.umich.edu 0x0: bn(22, {{;}}, 745091Sgblack@eecs.umich.edu annul_code={{ 755091Sgblack@eecs.umich.edu NNPC = NPC + 8; 765091Sgblack@eecs.umich.edu NPC = NPC + 4; 775091Sgblack@eecs.umich.edu }}); 785091Sgblack@eecs.umich.edu default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}}); 793598Sgblack@eecs.umich.edu } 802516SN/A } 812516SN/A 0x3: decode RCOND2 822516SN/A { 832516SN/A format BranchSplit 842482SN/A { 855091Sgblack@eecs.umich.edu 0x1: bpreq(test={{Rs1.sdw == 0}}); 865091Sgblack@eecs.umich.edu 0x2: bprle(test={{Rs1.sdw <= 0}}); 875091Sgblack@eecs.umich.edu 0x3: bprl(test={{Rs1.sdw < 0}}); 885091Sgblack@eecs.umich.edu 0x5: bprne(test={{Rs1.sdw != 0}}); 895091Sgblack@eecs.umich.edu 0x6: bprg(test={{Rs1.sdw > 0}}); 905091Sgblack@eecs.umich.edu 0x7: bprge(test={{Rs1.sdw >= 0}}); 912469SN/A } 922482SN/A } 932516SN/A //SETHI (or NOP if rd == 0 and imm == 0) 943042Sgblack@eecs.umich.edu 0x4: SetHi::sethi({{Rd.udw = imm;}}); 954004Sgblack@eecs.umich.edu //fbpfcc 964004Sgblack@eecs.umich.edu 0x5: decode COND2 { 974004Sgblack@eecs.umich.edu format BranchN { 984004Sgblack@eecs.umich.edu //Branch Always 995091Sgblack@eecs.umich.edu 0x8: fbpa(22, annul_code={{ 1005091Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 1015091Sgblack@eecs.umich.edu NNPC = NPC + 4; 1025091Sgblack@eecs.umich.edu }}); 1034004Sgblack@eecs.umich.edu //Branch Never 1045091Sgblack@eecs.umich.edu 0x0: fbpn(22, {{;}}, 1055091Sgblack@eecs.umich.edu annul_code={{ 1065091Sgblack@eecs.umich.edu NNPC = NPC + 8; 1075091Sgblack@eecs.umich.edu NPC = NPC + 4; 1085091Sgblack@eecs.umich.edu }}); 1094004Sgblack@eecs.umich.edu default: decode BPCC { 1105091Sgblack@eecs.umich.edu 0x0: fbpfcc0(19, test= 1115091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<11:10>, COND2)}}); 1125091Sgblack@eecs.umich.edu 0x1: fbpfcc1(19, test= 1135091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<33:32>, COND2)}}); 1145091Sgblack@eecs.umich.edu 0x2: fbpfcc2(19, test= 1155091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<35:34>, COND2)}}); 1165091Sgblack@eecs.umich.edu 0x3: fbpfcc3(19, test= 1175091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<37:36>, COND2)}}); 1184004Sgblack@eecs.umich.edu } 1194004Sgblack@eecs.umich.edu } 1204004Sgblack@eecs.umich.edu } 1214004Sgblack@eecs.umich.edu //fbfcc 1224004Sgblack@eecs.umich.edu 0x6: decode COND2 { 1234004Sgblack@eecs.umich.edu format BranchN { 1244004Sgblack@eecs.umich.edu //Branch Always 1255091Sgblack@eecs.umich.edu 0x8: fba(22, annul_code={{ 1265091Sgblack@eecs.umich.edu NPC = xc->readPC() + disp; 1275091Sgblack@eecs.umich.edu NNPC = NPC + 4; 1285091Sgblack@eecs.umich.edu }}); 1294004Sgblack@eecs.umich.edu //Branch Never 1305091Sgblack@eecs.umich.edu 0x0: fbn(22, {{;}}, 1315091Sgblack@eecs.umich.edu annul_code={{ 1325091Sgblack@eecs.umich.edu NNPC = NPC + 8; 1335091Sgblack@eecs.umich.edu NPC = NPC + 4; 1345091Sgblack@eecs.umich.edu }}); 1355091Sgblack@eecs.umich.edu default: fbfcc(22, test= 1365091Sgblack@eecs.umich.edu {{passesFpCondition(Fsr<11:10>, COND2)}}); 1374004Sgblack@eecs.umich.edu } 1384004Sgblack@eecs.umich.edu } 1392469SN/A } 1402944Sgblack@eecs.umich.edu 0x1: BranchN::call(30, {{ 1413928Ssaidi@eecs.umich.edu if (Pstate<3:>) 1423928Ssaidi@eecs.umich.edu R15 = (xc->readPC())<31:0>; 1433928Ssaidi@eecs.umich.edu else 1443928Ssaidi@eecs.umich.edu R15 = xc->readPC(); 1452516SN/A NNPC = R15 + disp; 1462469SN/A }}); 1472469SN/A 0x2: decode OP3 { 1482482SN/A format IntOp { 1492482SN/A 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 1502974Sgblack@eecs.umich.edu 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 1512974Sgblack@eecs.umich.edu 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 1522974Sgblack@eecs.umich.edu 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 1532526SN/A 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 1542974Sgblack@eecs.umich.edu 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 1552974Sgblack@eecs.umich.edu 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 1562974Sgblack@eecs.umich.edu 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 1572646Ssaidi@eecs.umich.edu 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 1582974Sgblack@eecs.umich.edu 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 1592469SN/A 0x0A: umul({{ 1602516SN/A Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 1612646Ssaidi@eecs.umich.edu Y = Rd<63:32>; 1622482SN/A }}); 1632469SN/A 0x0B: smul({{ 1643931Ssaidi@eecs.umich.edu Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 1653900Ssaidi@eecs.umich.edu Y = Rd.sdw<63:32>; 1662482SN/A }}); 1672954Sgblack@eecs.umich.edu 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 1682469SN/A 0x0D: udivx({{ 1692516SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 1702516SN/A else Rd.udw = Rs1.udw / Rs2_or_imm13; 1712482SN/A }}); 1722469SN/A 0x0E: udiv({{ 1732516SN/A if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 1742482SN/A else 1752482SN/A { 1762646Ssaidi@eecs.umich.edu Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 1772482SN/A if(Rd.udw >> 32 != 0) 1782482SN/A Rd.udw = 0xFFFFFFFF; 1792482SN/A } 1802482SN/A }}); 1812482SN/A 0x0F: sdiv({{ 1822615SN/A if(Rs2_or_imm13.sdw == 0) 1832469SN/A fault = new DivisionByZero; 1842469SN/A else 1852482SN/A { 1862646Ssaidi@eecs.umich.edu Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 1873929Ssaidi@eecs.umich.edu if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max()) 1882482SN/A Rd.udw = 0x7FFFFFFF; 1893929Ssaidi@eecs.umich.edu else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min()) 1903929Ssaidi@eecs.umich.edu Rd.udw = ULL(0xFFFFFFFF80000000); 1912482SN/A } 1922526SN/A }}); 1932469SN/A } 1942482SN/A format IntOpCc { 1952469SN/A 0x10: addcc({{ 1965093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 1975093Sgblack@eecs.umich.edu Rd = res = op1 + op2; 1985093Sgblack@eecs.umich.edu }}); 1992482SN/A 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 2002482SN/A 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 2012482SN/A 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 2022469SN/A 0x14: subcc({{ 2035093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2045093Sgblack@eecs.umich.edu Rd = res = op1 - op2; 2055093Sgblack@eecs.umich.edu }}, sub=True); 2062482SN/A 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 2072482SN/A 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 2082482SN/A 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 2092469SN/A 0x18: addccc({{ 2105093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2115093Sgblack@eecs.umich.edu Rd = res = op1 + op2 + Ccr<0:>; 2125093Sgblack@eecs.umich.edu }}); 2133765Sgblack@eecs.umich.edu 0x1A: IntOpCcRes::umulcc({{ 2142615SN/A uint64_t resTemp; 2152615SN/A Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 2163765Sgblack@eecs.umich.edu Y = resTemp<63:32>;}}); 2173765Sgblack@eecs.umich.edu 0x1B: IntOpCcRes::smulcc({{ 2182615SN/A int64_t resTemp; 2193931Ssaidi@eecs.umich.edu Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 2203765Sgblack@eecs.umich.edu Y = resTemp<63:32>;}}); 2212469SN/A 0x1C: subccc({{ 2225093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2235093Sgblack@eecs.umich.edu Rd = res = op1 - op2 - Ccr<0:>; 2245093Sgblack@eecs.umich.edu }}, sub=True); 2253765Sgblack@eecs.umich.edu 0x1D: IntOpCcRes::udivxcc({{ 2262615SN/A if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 2273765Sgblack@eecs.umich.edu else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 2285093Sgblack@eecs.umich.edu 0x1E: IntOpCcRes::udivcc({{ 2295093Sgblack@eecs.umich.edu uint32_t resTemp, val2 = Rs2_or_imm13.udw; 2305093Sgblack@eecs.umich.edu int32_t overflow = 0; 2315093Sgblack@eecs.umich.edu if(val2 == 0) fault = new DivisionByZero; 2325093Sgblack@eecs.umich.edu else 2335093Sgblack@eecs.umich.edu { 2345093Sgblack@eecs.umich.edu resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 2355093Sgblack@eecs.umich.edu overflow = (resTemp<63:32> != 0); 2365093Sgblack@eecs.umich.edu if(overflow) Rd = resTemp = 0xFFFFFFFF; 2375093Sgblack@eecs.umich.edu else Rd = resTemp; 2385093Sgblack@eecs.umich.edu } 2395093Sgblack@eecs.umich.edu }}, iv={{overflow}}); 2405093Sgblack@eecs.umich.edu 0x1F: IntOpCcRes::sdivcc({{ 2415093Sgblack@eecs.umich.edu int64_t val2 = Rs2_or_imm13.sdw<31:0>; 2425093Sgblack@eecs.umich.edu bool overflow = false, underflow = false; 2435093Sgblack@eecs.umich.edu if(val2 == 0) fault = new DivisionByZero; 2445093Sgblack@eecs.umich.edu else 2455093Sgblack@eecs.umich.edu { 2465093Sgblack@eecs.umich.edu Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 2475093Sgblack@eecs.umich.edu overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); 2485093Sgblack@eecs.umich.edu underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); 2495093Sgblack@eecs.umich.edu if(overflow) Rd = 0x7FFFFFFF; 2505093Sgblack@eecs.umich.edu else if(underflow) Rd = ULL(0xFFFFFFFF80000000); 2515093Sgblack@eecs.umich.edu } 2525093Sgblack@eecs.umich.edu }}, iv={{overflow || underflow}}); 2532469SN/A 0x20: taddcc({{ 2545093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2555093Sgblack@eecs.umich.edu Rd = res = Rs1 + op2; 2565093Sgblack@eecs.umich.edu }}, iv={{ 2575093Sgblack@eecs.umich.edu (op1 & mask(2)) || (op2 & mask(2)) || 2585093Sgblack@eecs.umich.edu findOverflow(32, res, op1, op2) 2595093Sgblack@eecs.umich.edu }}); 2602469SN/A 0x21: tsubcc({{ 2615093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2625093Sgblack@eecs.umich.edu Rd = res = Rs1 - op2; 2635093Sgblack@eecs.umich.edu }}, iv={{ 2645093Sgblack@eecs.umich.edu (op1 & mask(2)) || (op2 & mask(2)) || 2655093Sgblack@eecs.umich.edu findOverflow(32, res, op1, ~op2) 2665093Sgblack@eecs.umich.edu }}, sub=True); 2672469SN/A 0x22: taddcctv({{ 2685093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2695093Sgblack@eecs.umich.edu Rd = res = op1 + op2; 2705093Sgblack@eecs.umich.edu bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || 2715093Sgblack@eecs.umich.edu findOverflow(32, res, op1, op2); 2725093Sgblack@eecs.umich.edu if(overflow) fault = new TagOverflow; 2735093Sgblack@eecs.umich.edu }}, iv={{overflow}}); 2742469SN/A 0x23: tsubcctv({{ 2755093Sgblack@eecs.umich.edu int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 2765093Sgblack@eecs.umich.edu Rd = res = op1 - op2; 2775093Sgblack@eecs.umich.edu bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || 2785093Sgblack@eecs.umich.edu findOverflow(32, res, op1, ~op2); 2795093Sgblack@eecs.umich.edu if(overflow) fault = new TagOverflow; 2805093Sgblack@eecs.umich.edu }}, iv={{overflow}}, sub=True); 2812469SN/A 0x24: mulscc({{ 2825093Sgblack@eecs.umich.edu int32_t savedLSB = Rs1<0:>; 2834237Sgblack@eecs.umich.edu 2845093Sgblack@eecs.umich.edu //Step 1 2855093Sgblack@eecs.umich.edu int64_t multiplicand = Rs2_or_imm13; 2865093Sgblack@eecs.umich.edu //Step 2 2875093Sgblack@eecs.umich.edu int32_t partialP = Rs1<31:1> | 2885093Sgblack@eecs.umich.edu ((Ccr<3:3> ^ Ccr<1:1>) << 31); 2895093Sgblack@eecs.umich.edu //Step 3 2905093Sgblack@eecs.umich.edu int32_t added = Y<0:> ? multiplicand : 0; 2915093Sgblack@eecs.umich.edu int64_t res, op1 = partialP, op2 = added; 2925093Sgblack@eecs.umich.edu Rd = res = partialP + added; 2935093Sgblack@eecs.umich.edu //Steps 4 & 5 2945093Sgblack@eecs.umich.edu Y = Y<31:1> | (savedLSB << 31); 2955093Sgblack@eecs.umich.edu }}); 2962526SN/A } 2972526SN/A format IntOp 2982526SN/A { 2992526SN/A 0x25: decode X { 3002526SN/A 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 3012526SN/A 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 3022469SN/A } 3032526SN/A 0x26: decode X { 3042526SN/A 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3052526SN/A 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3062526SN/A } 3072526SN/A 0x27: decode X { 3082526SN/A 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 3092526SN/A 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 3102526SN/A } 3112954Sgblack@eecs.umich.edu 0x28: decode RS1 { 3123929Ssaidi@eecs.umich.edu 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); 3133587Sgblack@eecs.umich.edu //1 should cause an illegal instruction exception 3143587Sgblack@eecs.umich.edu 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 3153587Sgblack@eecs.umich.edu 0x03: NoPriv::rdasi({{Rd = Asi;}}); 3165094Sgblack@eecs.umich.edu 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 3173587Sgblack@eecs.umich.edu 0x05: NoPriv::rdpc({{ 3183587Sgblack@eecs.umich.edu if(Pstate<3:>) 3193587Sgblack@eecs.umich.edu Rd = (xc->readPC())<31:0>; 3203587Sgblack@eecs.umich.edu else 3213587Sgblack@eecs.umich.edu Rd = xc->readPC();}}); 3223587Sgblack@eecs.umich.edu 0x06: NoPriv::rdfprs({{ 3233587Sgblack@eecs.umich.edu //Wait for all fpops to finish. 3243587Sgblack@eecs.umich.edu Rd = Fprs; 3253587Sgblack@eecs.umich.edu }}); 3263587Sgblack@eecs.umich.edu //7-14 should cause an illegal instruction exception 3273587Sgblack@eecs.umich.edu 0x0F: decode I { 3284040Ssaidi@eecs.umich.edu 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp); 3294040Ssaidi@eecs.umich.edu 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp); 3302954Sgblack@eecs.umich.edu } 3313587Sgblack@eecs.umich.edu 0x10: Priv::rdpcr({{Rd = Pcr;}}); 3325094Sgblack@eecs.umich.edu 0x11: Priv::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); 3333587Sgblack@eecs.umich.edu //0x12 should cause an illegal instruction exception 3343587Sgblack@eecs.umich.edu 0x13: NoPriv::rdgsr({{ 3354010Ssaidi@eecs.umich.edu fault = checkFpEnableFault(xc); 3364010Ssaidi@eecs.umich.edu if (fault) 3374010Ssaidi@eecs.umich.edu return fault; 3384010Ssaidi@eecs.umich.edu Rd = Gsr; 3392954Sgblack@eecs.umich.edu }}); 3403587Sgblack@eecs.umich.edu //0x14-0x15 should cause an illegal instruction exception 3413587Sgblack@eecs.umich.edu 0x16: Priv::rdsoftint({{Rd = Softint;}}); 3423823Ssaidi@eecs.umich.edu 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 3435094Sgblack@eecs.umich.edu 0x18: Priv::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 3443823Ssaidi@eecs.umich.edu 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 3453598Sgblack@eecs.umich.edu 0x1A: Priv::rdstrand_sts_reg({{ 3463598Sgblack@eecs.umich.edu if(Pstate<2:> && !Hpstate<2:>) 3473598Sgblack@eecs.umich.edu Rd = StrandStsReg<0:>; 3483598Sgblack@eecs.umich.edu else 3493598Sgblack@eecs.umich.edu Rd = StrandStsReg; 3503598Sgblack@eecs.umich.edu }}); 3513598Sgblack@eecs.umich.edu //0x1A is supposed to be reserved, but it reads the strand 3523598Sgblack@eecs.umich.edu //status register. 3533598Sgblack@eecs.umich.edu //0x1B-0x1F should cause an illegal instruction exception 3542954Sgblack@eecs.umich.edu } 3553587Sgblack@eecs.umich.edu 0x29: decode RS1 { 3563587Sgblack@eecs.umich.edu 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); 3575094Sgblack@eecs.umich.edu 0x01: HPriv::rdhprhtstate({{Rd = Htstate;}}, checkTl=true); 3583587Sgblack@eecs.umich.edu //0x02 should cause an illegal instruction exception 3593587Sgblack@eecs.umich.edu 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 3603587Sgblack@eecs.umich.edu //0x04 should cause an illegal instruction exception 3613587Sgblack@eecs.umich.edu 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 3623587Sgblack@eecs.umich.edu 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 3633587Sgblack@eecs.umich.edu //0x07-0x1E should cause an illegal instruction exception 3643823Ssaidi@eecs.umich.edu 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); 3653587Sgblack@eecs.umich.edu } 3663587Sgblack@eecs.umich.edu 0x2A: decode RS1 { 3675094Sgblack@eecs.umich.edu 0x00: Priv::rdprtpc({{Rd = Tpc;}}, checkTl=true); 3685094Sgblack@eecs.umich.edu 0x01: Priv::rdprtnpc({{Rd = Tnpc;}}, checkTl=true); 3695094Sgblack@eecs.umich.edu 0x02: Priv::rdprtstate({{Rd = Tstate;}}, checkTl=true); 3705094Sgblack@eecs.umich.edu 0x03: Priv::rdprtt({{Rd = Tt;}}, checkTl=true); 3713823Ssaidi@eecs.umich.edu 0x04: Priv::rdprtick({{Rd = Tick;}}); 3723587Sgblack@eecs.umich.edu 0x05: Priv::rdprtba({{Rd = Tba;}}); 3733587Sgblack@eecs.umich.edu 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 3743587Sgblack@eecs.umich.edu 0x07: Priv::rdprtl({{Rd = Tl;}}); 3753587Sgblack@eecs.umich.edu 0x08: Priv::rdprpil({{Rd = Pil;}}); 3763587Sgblack@eecs.umich.edu 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 3773587Sgblack@eecs.umich.edu 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 3783587Sgblack@eecs.umich.edu 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 3793587Sgblack@eecs.umich.edu 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); 3803587Sgblack@eecs.umich.edu 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); 3813587Sgblack@eecs.umich.edu 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); 3823587Sgblack@eecs.umich.edu //0x0F should cause an illegal instruction exception 3833587Sgblack@eecs.umich.edu 0x10: Priv::rdprgl({{Rd = Gl;}}); 3843587Sgblack@eecs.umich.edu //0x11-0x1F should cause an illegal instruction exception 3853587Sgblack@eecs.umich.edu } 3862526SN/A 0x2B: BasicOperate::flushw({{ 3873911Ssaidi@eecs.umich.edu if(NWindows - 2 - Cansave != 0) 3882526SN/A { 3892526SN/A if(Otherwin) 3903909Ssaidi@eecs.umich.edu fault = new SpillNOther(4*Wstate<5:3>); 3912526SN/A else 3923909Ssaidi@eecs.umich.edu fault = new SpillNNormal(4*Wstate<2:0>); 3932526SN/A } 3942526SN/A }}); 3952526SN/A 0x2C: decode MOVCC3 3962469SN/A { 3972526SN/A 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 3982526SN/A 0x1: decode CC 3992526SN/A { 4002526SN/A 0x0: movcci({{ 4012646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 4022591SN/A Rd = Rs2_or_imm11; 4032591SN/A else 4042591SN/A Rd = Rd; 4052526SN/A }}); 4062526SN/A 0x2: movccx({{ 4072646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 4082591SN/A Rd = Rs2_or_imm11; 4092591SN/A else 4102591SN/A Rd = Rd; 4112526SN/A }}); 4122224SN/A } 4132526SN/A } 4142526SN/A 0x2D: sdivx({{ 4152615SN/A if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 4162615SN/A else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 4172526SN/A }}); 4183941Ssaidi@eecs.umich.edu 0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 4192526SN/A 0x2F: decode RCOND3 4202526SN/A { 4212615SN/A 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 4222615SN/A 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 4232615SN/A 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 4242615SN/A 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 4252615SN/A 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 4262615SN/A 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 4272526SN/A } 4283587Sgblack@eecs.umich.edu 0x30: decode RD { 4293929Ssaidi@eecs.umich.edu 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); 4303587Sgblack@eecs.umich.edu //0x01 should cause an illegal instruction exception 4313587Sgblack@eecs.umich.edu 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 4323826Ssaidi@eecs.umich.edu 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 4333587Sgblack@eecs.umich.edu //0x04-0x05 should cause an illegal instruction exception 4343587Sgblack@eecs.umich.edu 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 4353587Sgblack@eecs.umich.edu //0x07-0x0E should cause an illegal instruction exception 4363587Sgblack@eecs.umich.edu 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 4373587Sgblack@eecs.umich.edu 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); 4385094Sgblack@eecs.umich.edu 0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); 4393587Sgblack@eecs.umich.edu //0x12 should cause an illegal instruction exception 4403587Sgblack@eecs.umich.edu 0x13: NoPriv::wrgsr({{ 4413587Sgblack@eecs.umich.edu if(Fprs<2:> == 0 || Pstate<4:> == 0) 4423587Sgblack@eecs.umich.edu return new FpDisabled; 4433587Sgblack@eecs.umich.edu Gsr = Rs1 ^ Rs2_or_imm13; 4443587Sgblack@eecs.umich.edu }}); 4453587Sgblack@eecs.umich.edu 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 4463587Sgblack@eecs.umich.edu 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 4473587Sgblack@eecs.umich.edu 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 4483823Ssaidi@eecs.umich.edu 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 4493587Sgblack@eecs.umich.edu 0x18: NoPriv::wrstick({{ 4503587Sgblack@eecs.umich.edu if(!Hpstate<2:>) 4513587Sgblack@eecs.umich.edu return new IllegalInstruction; 4523823Ssaidi@eecs.umich.edu Stick = Rs1 ^ Rs2_or_imm13; 4533587Sgblack@eecs.umich.edu }}); 4543823Ssaidi@eecs.umich.edu 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 4553598Sgblack@eecs.umich.edu 0x1A: Priv::wrstrand_sts_reg({{ 4563598Sgblack@eecs.umich.edu StrandStsReg = Rs1 ^ Rs2_or_imm13; 4573598Sgblack@eecs.umich.edu }}); 4583598Sgblack@eecs.umich.edu //0x1A is supposed to be reserved, but it writes the strand 4593598Sgblack@eecs.umich.edu //status register. 4603598Sgblack@eecs.umich.edu //0x1B-0x1F should cause an illegal instruction exception 4613587Sgblack@eecs.umich.edu } 4622526SN/A 0x31: decode FCN { 4633417Sgblack@eecs.umich.edu 0x0: Priv::saved({{ 4643417Sgblack@eecs.umich.edu assert(Cansave < NWindows - 2); 4653417Sgblack@eecs.umich.edu assert(Otherwin || Canrestore); 4663417Sgblack@eecs.umich.edu Cansave = Cansave + 1; 4673417Sgblack@eecs.umich.edu if(Otherwin == 0) 4683417Sgblack@eecs.umich.edu Canrestore = Canrestore - 1; 4693417Sgblack@eecs.umich.edu else 4703417Sgblack@eecs.umich.edu Otherwin = Otherwin - 1; 4713417Sgblack@eecs.umich.edu }}); 4723598Sgblack@eecs.umich.edu 0x1: Priv::restored({{ 4733417Sgblack@eecs.umich.edu assert(Cansave || Otherwin); 4743417Sgblack@eecs.umich.edu assert(Canrestore < NWindows - 2); 4753417Sgblack@eecs.umich.edu Canrestore = Canrestore + 1; 4763417Sgblack@eecs.umich.edu if(Otherwin == 0) 4773417Sgblack@eecs.umich.edu Cansave = Cansave - 1; 4783417Sgblack@eecs.umich.edu else 4793417Sgblack@eecs.umich.edu Otherwin = Otherwin - 1; 4803928Ssaidi@eecs.umich.edu 4813928Ssaidi@eecs.umich.edu if(Cleanwin < NWindows - 1) 4823928Ssaidi@eecs.umich.edu Cleanwin = Cleanwin + 1; 4833417Sgblack@eecs.umich.edu }}); 4842526SN/A } 4853587Sgblack@eecs.umich.edu 0x32: decode RD { 4865094Sgblack@eecs.umich.edu 0x00: Priv::wrprtpc( 4875094Sgblack@eecs.umich.edu {{Tpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 4885094Sgblack@eecs.umich.edu 0x01: Priv::wrprtnpc( 4895094Sgblack@eecs.umich.edu {{Tnpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 4905094Sgblack@eecs.umich.edu 0x02: Priv::wrprtstate( 4915094Sgblack@eecs.umich.edu {{Tstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 4925094Sgblack@eecs.umich.edu 0x03: Priv::wrprtt( 4935094Sgblack@eecs.umich.edu {{Tt = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 4943823Ssaidi@eecs.umich.edu 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 4953587Sgblack@eecs.umich.edu 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 4963587Sgblack@eecs.umich.edu 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 4973587Sgblack@eecs.umich.edu 0x07: Priv::wrprtl({{ 4983587Sgblack@eecs.umich.edu if(Pstate<2:> && !Hpstate<2:>) 4993587Sgblack@eecs.umich.edu Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 5003587Sgblack@eecs.umich.edu else 5013587Sgblack@eecs.umich.edu Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 5023587Sgblack@eecs.umich.edu }}); 5033587Sgblack@eecs.umich.edu 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 5043587Sgblack@eecs.umich.edu 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 5053587Sgblack@eecs.umich.edu 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 5063587Sgblack@eecs.umich.edu 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 5073587Sgblack@eecs.umich.edu 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 5083587Sgblack@eecs.umich.edu 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 5093587Sgblack@eecs.umich.edu 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 5103587Sgblack@eecs.umich.edu //0x0F should cause an illegal instruction exception 5113587Sgblack@eecs.umich.edu 0x10: Priv::wrprgl({{ 5123587Sgblack@eecs.umich.edu if(Pstate<2:> && !Hpstate<2:>) 5133587Sgblack@eecs.umich.edu Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL); 5143587Sgblack@eecs.umich.edu else 5153587Sgblack@eecs.umich.edu Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL); 5163587Sgblack@eecs.umich.edu }}); 5173587Sgblack@eecs.umich.edu //0x11-0x1F should cause an illegal instruction exception 5183587Sgblack@eecs.umich.edu } 5193587Sgblack@eecs.umich.edu 0x33: decode RD { 5203587Sgblack@eecs.umich.edu 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); 5215094Sgblack@eecs.umich.edu 0x01: HPriv::wrhprhtstate( 5225094Sgblack@eecs.umich.edu {{Htstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 5233587Sgblack@eecs.umich.edu //0x02 should cause an illegal instruction exception 5243587Sgblack@eecs.umich.edu 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 5253587Sgblack@eecs.umich.edu //0x04 should cause an illegal instruction exception 5263587Sgblack@eecs.umich.edu 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 5273587Sgblack@eecs.umich.edu //0x06-0x01D should cause an illegal instruction exception 5283823Ssaidi@eecs.umich.edu 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 5293587Sgblack@eecs.umich.edu } 5302954Sgblack@eecs.umich.edu 0x34: decode OPF{ 5314008Ssaidi@eecs.umich.edu format FpBasic{ 5322963Sgblack@eecs.umich.edu 0x01: fmovs({{ 5333279Sgblack@eecs.umich.edu Frds.uw = Frs2s.uw; 5342963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 5352963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 5362963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 5372963Sgblack@eecs.umich.edu }}); 5382963Sgblack@eecs.umich.edu 0x02: fmovd({{ 5393057Sgblack@eecs.umich.edu Frd.udw = Frs2.udw; 5402963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 5412963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 5422963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 5432963Sgblack@eecs.umich.edu }}); 5443995Sgblack@eecs.umich.edu 0x03: FpUnimpl::fmovq(); 5452963Sgblack@eecs.umich.edu 0x05: fnegs({{ 5463279Sgblack@eecs.umich.edu Frds.uw = Frs2s.uw ^ (1UL << 31); 5472963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 5482963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 5492963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 5502963Sgblack@eecs.umich.edu }}); 5512963Sgblack@eecs.umich.edu 0x06: fnegd({{ 5523057Sgblack@eecs.umich.edu Frd.udw = Frs2.udw ^ (1ULL << 63); 5532963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 5542963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 5552963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 5562963Sgblack@eecs.umich.edu }}); 5573995Sgblack@eecs.umich.edu 0x07: FpUnimpl::fnegq(); 5582963Sgblack@eecs.umich.edu 0x09: fabss({{ 5593279Sgblack@eecs.umich.edu Frds.uw = ((1UL << 31) - 1) & Frs2s.uw; 5602963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 5612963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 5622963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 5632963Sgblack@eecs.umich.edu }}); 5642963Sgblack@eecs.umich.edu 0x0A: fabsd({{ 5653057Sgblack@eecs.umich.edu Frd.udw = ((1ULL << 63) - 1) & Frs2.udw; 5662963Sgblack@eecs.umich.edu //fsr.ftt = fsr.cexc = 0 5672963Sgblack@eecs.umich.edu Fsr &= ~(7 << 14); 5682963Sgblack@eecs.umich.edu Fsr &= ~(0x1F); 5692963Sgblack@eecs.umich.edu }}); 5703995Sgblack@eecs.umich.edu 0x0B: FpUnimpl::fabsq(); 5713918Ssaidi@eecs.umich.edu 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 5723918Ssaidi@eecs.umich.edu 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 5733995Sgblack@eecs.umich.edu 0x2B: FpUnimpl::fsqrtq(); 5743279Sgblack@eecs.umich.edu 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 5752963Sgblack@eecs.umich.edu 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 5763995Sgblack@eecs.umich.edu 0x43: FpUnimpl::faddq(); 5773279Sgblack@eecs.umich.edu 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 5784008Ssaidi@eecs.umich.edu 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }}); 5793995Sgblack@eecs.umich.edu 0x47: FpUnimpl::fsubq(); 5803279Sgblack@eecs.umich.edu 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 5812963Sgblack@eecs.umich.edu 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 5823995Sgblack@eecs.umich.edu 0x4B: FpUnimpl::fmulq(); 5833279Sgblack@eecs.umich.edu 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 5842963Sgblack@eecs.umich.edu 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 5853995Sgblack@eecs.umich.edu 0x4F: FpUnimpl::fdivq(); 5863279Sgblack@eecs.umich.edu 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 5873995Sgblack@eecs.umich.edu 0x6E: FpUnimpl::fdmulq(); 5882963Sgblack@eecs.umich.edu 0x81: fstox({{ 5894008Ssaidi@eecs.umich.edu Frd.sdw = static_cast<int64_t>(Frs2s.sf); 5902963Sgblack@eecs.umich.edu }}); 5912963Sgblack@eecs.umich.edu 0x82: fdtox({{ 5924008Ssaidi@eecs.umich.edu Frd.sdw = static_cast<int64_t>(Frs2.df); 5932963Sgblack@eecs.umich.edu }}); 5943995Sgblack@eecs.umich.edu 0x83: FpUnimpl::fqtox(); 5952963Sgblack@eecs.umich.edu 0x84: fxtos({{ 5964008Ssaidi@eecs.umich.edu Frds.sf = static_cast<float>(Frs2.sdw); 5972963Sgblack@eecs.umich.edu }}); 5982963Sgblack@eecs.umich.edu 0x88: fxtod({{ 5994008Ssaidi@eecs.umich.edu Frd.df = static_cast<double>(Frs2.sdw); 6002963Sgblack@eecs.umich.edu }}); 6013995Sgblack@eecs.umich.edu 0x8C: FpUnimpl::fxtoq(); 6022963Sgblack@eecs.umich.edu 0xC4: fitos({{ 6034008Ssaidi@eecs.umich.edu Frds.sf = static_cast<float>(Frs2s.sw); 6042963Sgblack@eecs.umich.edu }}); 6053279Sgblack@eecs.umich.edu 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 6063995Sgblack@eecs.umich.edu 0xC7: FpUnimpl::fqtos(); 6072963Sgblack@eecs.umich.edu 0xC8: fitod({{ 6084008Ssaidi@eecs.umich.edu Frd.df = static_cast<double>(Frs2s.sw); 6092963Sgblack@eecs.umich.edu }}); 6103279Sgblack@eecs.umich.edu 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 6113995Sgblack@eecs.umich.edu 0xCB: FpUnimpl::fqtod(); 6123995Sgblack@eecs.umich.edu 0xCC: FpUnimpl::fitoq(); 6133995Sgblack@eecs.umich.edu 0xCD: FpUnimpl::fstoq(); 6143995Sgblack@eecs.umich.edu 0xCE: FpUnimpl::fdtoq(); 6152963Sgblack@eecs.umich.edu 0xD1: fstoi({{ 6164008Ssaidi@eecs.umich.edu Frds.sw = static_cast<int32_t>(Frs2s.sf); 6174008Ssaidi@eecs.umich.edu float t = Frds.sw; 6184008Ssaidi@eecs.umich.edu if (t != Frs2s.sf) 6194008Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr, 4,0, 0x01); 6202963Sgblack@eecs.umich.edu }}); 6212963Sgblack@eecs.umich.edu 0xD2: fdtoi({{ 6224008Ssaidi@eecs.umich.edu Frds.sw = static_cast<int32_t>(Frs2.df); 6234008Ssaidi@eecs.umich.edu double t = Frds.sw; 6244008Ssaidi@eecs.umich.edu if (t != Frs2.df) 6254008Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr, 4,0, 0x01); 6262963Sgblack@eecs.umich.edu }}); 6273995Sgblack@eecs.umich.edu 0xD3: FpUnimpl::fqtoi(); 6283941Ssaidi@eecs.umich.edu default: FailUnimpl::fpop1(); 6292963Sgblack@eecs.umich.edu } 6302954Sgblack@eecs.umich.edu } 6313992Sgblack@eecs.umich.edu 0x35: decode OPF{ 6324008Ssaidi@eecs.umich.edu format FpBasic{ 6334204Sgblack@eecs.umich.edu 0x01: fmovs_fcc0({{ 6344204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<11:10>, COND4)) 6354204Sgblack@eecs.umich.edu Frds = Frs2s; 6364204Sgblack@eecs.umich.edu else 6374204Sgblack@eecs.umich.edu Frds = Frds; 6384204Sgblack@eecs.umich.edu }}); 6394204Sgblack@eecs.umich.edu 0x02: fmovd_fcc0({{ 6404204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<11:10>, COND4)) 6414204Sgblack@eecs.umich.edu Frd = Frs2; 6424204Sgblack@eecs.umich.edu else 6434204Sgblack@eecs.umich.edu Frd = Frd; 6444204Sgblack@eecs.umich.edu }}); 6454204Sgblack@eecs.umich.edu 0x03: FpUnimpl::fmovq_fcc0(); 6464204Sgblack@eecs.umich.edu 0x25: fmovrsz({{ 6474204Sgblack@eecs.umich.edu if(Rs1 == 0) 6484204Sgblack@eecs.umich.edu Frds = Frs2s; 6494204Sgblack@eecs.umich.edu else 6504204Sgblack@eecs.umich.edu Frds = Frds; 6514204Sgblack@eecs.umich.edu }}); 6524204Sgblack@eecs.umich.edu 0x26: fmovrdz({{ 6534204Sgblack@eecs.umich.edu if(Rs1 == 0) 6544204Sgblack@eecs.umich.edu Frd = Frs2; 6554204Sgblack@eecs.umich.edu else 6564204Sgblack@eecs.umich.edu Frd = Frd; 6574204Sgblack@eecs.umich.edu }}); 6584204Sgblack@eecs.umich.edu 0x27: FpUnimpl::fmovrqz(); 6594204Sgblack@eecs.umich.edu 0x41: fmovs_fcc1({{ 6604204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<33:32>, COND4)) 6614204Sgblack@eecs.umich.edu Frds = Frs2s; 6624204Sgblack@eecs.umich.edu else 6634204Sgblack@eecs.umich.edu Frds = Frds; 6644204Sgblack@eecs.umich.edu }}); 6654204Sgblack@eecs.umich.edu 0x42: fmovd_fcc1({{ 6664204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<33:32>, COND4)) 6674204Sgblack@eecs.umich.edu Frd = Frs2; 6684204Sgblack@eecs.umich.edu else 6694204Sgblack@eecs.umich.edu Frd = Frd; 6704204Sgblack@eecs.umich.edu }}); 6714204Sgblack@eecs.umich.edu 0x43: FpUnimpl::fmovq_fcc1(); 6724204Sgblack@eecs.umich.edu 0x45: fmovrslez({{ 6734204Sgblack@eecs.umich.edu if(Rs1 <= 0) 6744204Sgblack@eecs.umich.edu Frds = Frs2s; 6754204Sgblack@eecs.umich.edu else 6764204Sgblack@eecs.umich.edu Frds = Frds; 6774204Sgblack@eecs.umich.edu }}); 6784204Sgblack@eecs.umich.edu 0x46: fmovrdlez({{ 6794204Sgblack@eecs.umich.edu if(Rs1 <= 0) 6804204Sgblack@eecs.umich.edu Frd = Frs2; 6814204Sgblack@eecs.umich.edu else 6824204Sgblack@eecs.umich.edu Frd = Frd; 6834204Sgblack@eecs.umich.edu }}); 6844204Sgblack@eecs.umich.edu 0x47: FpUnimpl::fmovrqlez(); 6853992Sgblack@eecs.umich.edu 0x51: fcmps({{ 6863992Sgblack@eecs.umich.edu uint8_t fcc; 6873998Ssaidi@eecs.umich.edu if(isnan(Frs1s) || isnan(Frs2s)) 6883992Sgblack@eecs.umich.edu fcc = 3; 6893992Sgblack@eecs.umich.edu else if(Frs1s < Frs2s) 6903992Sgblack@eecs.umich.edu fcc = 1; 6913992Sgblack@eecs.umich.edu else if(Frs1s > Frs2s) 6923992Sgblack@eecs.umich.edu fcc = 2; 6933992Sgblack@eecs.umich.edu else 6943992Sgblack@eecs.umich.edu fcc = 0; 6953992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 6963992Sgblack@eecs.umich.edu if(FCMPCC) 6973992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 6983992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 6993992Sgblack@eecs.umich.edu }}); 7003992Sgblack@eecs.umich.edu 0x52: fcmpd({{ 7013992Sgblack@eecs.umich.edu uint8_t fcc; 7024008Ssaidi@eecs.umich.edu if(isnan(Frs1) || isnan(Frs2)) 7033992Sgblack@eecs.umich.edu fcc = 3; 7044008Ssaidi@eecs.umich.edu else if(Frs1 < Frs2) 7053992Sgblack@eecs.umich.edu fcc = 1; 7064008Ssaidi@eecs.umich.edu else if(Frs1 > Frs2) 7073992Sgblack@eecs.umich.edu fcc = 2; 7083992Sgblack@eecs.umich.edu else 7093992Sgblack@eecs.umich.edu fcc = 0; 7103992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7113992Sgblack@eecs.umich.edu if(FCMPCC) 7123992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7133992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7143992Sgblack@eecs.umich.edu }}); 7153995Sgblack@eecs.umich.edu 0x53: FpUnimpl::fcmpq(); 7163997Ssaidi@eecs.umich.edu 0x55: fcmpes({{ 7173992Sgblack@eecs.umich.edu uint8_t fcc = 0; 7183998Ssaidi@eecs.umich.edu if(isnan(Frs1s) || isnan(Frs2s)) 7193992Sgblack@eecs.umich.edu fault = new FpExceptionIEEE754; 7203992Sgblack@eecs.umich.edu if(Frs1s < Frs2s) 7213992Sgblack@eecs.umich.edu fcc = 1; 7223992Sgblack@eecs.umich.edu else if(Frs1s > Frs2s) 7233992Sgblack@eecs.umich.edu fcc = 2; 7243992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7253992Sgblack@eecs.umich.edu if(FCMPCC) 7263992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7273992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7283992Sgblack@eecs.umich.edu }}); 7293997Ssaidi@eecs.umich.edu 0x56: fcmped({{ 7303992Sgblack@eecs.umich.edu uint8_t fcc = 0; 7314008Ssaidi@eecs.umich.edu if(isnan(Frs1) || isnan(Frs2)) 7323992Sgblack@eecs.umich.edu fault = new FpExceptionIEEE754; 7334008Ssaidi@eecs.umich.edu if(Frs1 < Frs2) 7343992Sgblack@eecs.umich.edu fcc = 1; 7354008Ssaidi@eecs.umich.edu else if(Frs1 > Frs2) 7363992Sgblack@eecs.umich.edu fcc = 2; 7373992Sgblack@eecs.umich.edu uint8_t firstbit = 10; 7383992Sgblack@eecs.umich.edu if(FCMPCC) 7393992Sgblack@eecs.umich.edu firstbit = FCMPCC * 2 + 30; 7403992Sgblack@eecs.umich.edu Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 7413992Sgblack@eecs.umich.edu }}); 7423997Ssaidi@eecs.umich.edu 0x57: FpUnimpl::fcmpeq(); 7434204Sgblack@eecs.umich.edu 0x65: fmovrslz({{ 7444204Sgblack@eecs.umich.edu if(Rs1 < 0) 7454204Sgblack@eecs.umich.edu Frds = Frs2s; 7464204Sgblack@eecs.umich.edu else 7474204Sgblack@eecs.umich.edu Frds = Frds; 7484204Sgblack@eecs.umich.edu }}); 7494204Sgblack@eecs.umich.edu 0x66: fmovrdlz({{ 7504204Sgblack@eecs.umich.edu if(Rs1 < 0) 7514204Sgblack@eecs.umich.edu Frd = Frs2; 7524204Sgblack@eecs.umich.edu else 7534204Sgblack@eecs.umich.edu Frd = Frd; 7544204Sgblack@eecs.umich.edu }}); 7554204Sgblack@eecs.umich.edu 0x67: FpUnimpl::fmovrqlz(); 7564204Sgblack@eecs.umich.edu 0x81: fmovs_fcc2({{ 7574204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<35:34>, COND4)) 7584204Sgblack@eecs.umich.edu Frds = Frs2s; 7594204Sgblack@eecs.umich.edu else 7604204Sgblack@eecs.umich.edu Frds = Frds; 7614204Sgblack@eecs.umich.edu }}); 7624204Sgblack@eecs.umich.edu 0x82: fmovd_fcc2({{ 7634204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<35:34>, COND4)) 7644204Sgblack@eecs.umich.edu Frd = Frs2; 7654204Sgblack@eecs.umich.edu else 7664204Sgblack@eecs.umich.edu Frd = Frd; 7674204Sgblack@eecs.umich.edu }}); 7684204Sgblack@eecs.umich.edu 0x83: FpUnimpl::fmovq_fcc2(); 7694204Sgblack@eecs.umich.edu 0xA5: fmovrsnz({{ 7704204Sgblack@eecs.umich.edu if(Rs1 != 0) 7714204Sgblack@eecs.umich.edu Frds = Frs2s; 7724204Sgblack@eecs.umich.edu else 7734204Sgblack@eecs.umich.edu Frds = Frds; 7744204Sgblack@eecs.umich.edu }}); 7754204Sgblack@eecs.umich.edu 0xA6: fmovrdnz({{ 7764204Sgblack@eecs.umich.edu if(Rs1 != 0) 7774204Sgblack@eecs.umich.edu Frd = Frs2; 7784204Sgblack@eecs.umich.edu else 7794204Sgblack@eecs.umich.edu Frd = Frd; 7804204Sgblack@eecs.umich.edu }}); 7814204Sgblack@eecs.umich.edu 0xA7: FpUnimpl::fmovrqnz(); 7824204Sgblack@eecs.umich.edu 0xC1: fmovs_fcc3({{ 7834204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<37:36>, COND4)) 7844204Sgblack@eecs.umich.edu Frds = Frs2s; 7854204Sgblack@eecs.umich.edu else 7864204Sgblack@eecs.umich.edu Frds = Frds; 7874204Sgblack@eecs.umich.edu }}); 7884204Sgblack@eecs.umich.edu 0xC2: fmovd_fcc3({{ 7894204Sgblack@eecs.umich.edu if(passesFpCondition(Fsr<37:36>, COND4)) 7904204Sgblack@eecs.umich.edu Frd = Frs2; 7914204Sgblack@eecs.umich.edu else 7924204Sgblack@eecs.umich.edu Frd = Frd; 7934204Sgblack@eecs.umich.edu }}); 7944204Sgblack@eecs.umich.edu 0xC3: FpUnimpl::fmovq_fcc3(); 7954204Sgblack@eecs.umich.edu 0xC5: fmovrsgz({{ 7964204Sgblack@eecs.umich.edu if(Rs1 > 0) 7974204Sgblack@eecs.umich.edu Frds = Frs2s; 7984204Sgblack@eecs.umich.edu else 7994204Sgblack@eecs.umich.edu Frds = Frds; 8004204Sgblack@eecs.umich.edu }}); 8014204Sgblack@eecs.umich.edu 0xC6: fmovrdgz({{ 8024204Sgblack@eecs.umich.edu if(Rs1 > 0) 8034204Sgblack@eecs.umich.edu Frd = Frs2; 8044204Sgblack@eecs.umich.edu else 8054204Sgblack@eecs.umich.edu Frd = Frd; 8064204Sgblack@eecs.umich.edu }}); 8074204Sgblack@eecs.umich.edu 0xC7: FpUnimpl::fmovrqgz(); 8084204Sgblack@eecs.umich.edu 0xE5: fmovrsgez({{ 8094204Sgblack@eecs.umich.edu if(Rs1 >= 0) 8104204Sgblack@eecs.umich.edu Frds = Frs2s; 8114204Sgblack@eecs.umich.edu else 8124204Sgblack@eecs.umich.edu Frds = Frds; 8134204Sgblack@eecs.umich.edu }}); 8144204Sgblack@eecs.umich.edu 0xE6: fmovrdgez({{ 8154204Sgblack@eecs.umich.edu if(Rs1 >= 0) 8164204Sgblack@eecs.umich.edu Frd = Frs2; 8174204Sgblack@eecs.umich.edu else 8184204Sgblack@eecs.umich.edu Frd = Frd; 8194204Sgblack@eecs.umich.edu }}); 8204204Sgblack@eecs.umich.edu 0xE7: FpUnimpl::fmovrqgez(); 8214204Sgblack@eecs.umich.edu 0x101: fmovs_icc({{ 8224204Sgblack@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 8234204Sgblack@eecs.umich.edu Frds = Frs2s; 8244204Sgblack@eecs.umich.edu else 8254204Sgblack@eecs.umich.edu Frds = Frds; 8264204Sgblack@eecs.umich.edu }}); 8274204Sgblack@eecs.umich.edu 0x102: fmovd_icc({{ 8284204Sgblack@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND4)) 8294204Sgblack@eecs.umich.edu Frd = Frs2; 8304204Sgblack@eecs.umich.edu else 8314204Sgblack@eecs.umich.edu Frd = Frd; 8324204Sgblack@eecs.umich.edu }}); 8334204Sgblack@eecs.umich.edu 0x103: FpUnimpl::fmovq_icc(); 8344204Sgblack@eecs.umich.edu 0x181: fmovs_xcc({{ 8354204Sgblack@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 8364204Sgblack@eecs.umich.edu Frds = Frs2s; 8374204Sgblack@eecs.umich.edu else 8384204Sgblack@eecs.umich.edu Frds = Frds; 8394204Sgblack@eecs.umich.edu }}); 8404204Sgblack@eecs.umich.edu 0x182: fmovd_xcc({{ 8414204Sgblack@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND4)) 8424204Sgblack@eecs.umich.edu Frd = Frs2; 8434204Sgblack@eecs.umich.edu else 8444204Sgblack@eecs.umich.edu Frd = Frd; 8454204Sgblack@eecs.umich.edu }}); 8464204Sgblack@eecs.umich.edu 0x183: FpUnimpl::fmovq_xcc(); 8473992Sgblack@eecs.umich.edu default: FailUnimpl::fpop2(); 8483992Sgblack@eecs.umich.edu } 8493992Sgblack@eecs.umich.edu } 8502954Sgblack@eecs.umich.edu //This used to be just impdep1, but now it's a whole bunch 8512954Sgblack@eecs.umich.edu //of instructions 8522954Sgblack@eecs.umich.edu 0x36: decode OPF{ 8533941Ssaidi@eecs.umich.edu 0x00: FailUnimpl::edge8(); 8543941Ssaidi@eecs.umich.edu 0x01: FailUnimpl::edge8n(); 8553941Ssaidi@eecs.umich.edu 0x02: FailUnimpl::edge8l(); 8563941Ssaidi@eecs.umich.edu 0x03: FailUnimpl::edge8ln(); 8573941Ssaidi@eecs.umich.edu 0x04: FailUnimpl::edge16(); 8583941Ssaidi@eecs.umich.edu 0x05: FailUnimpl::edge16n(); 8593941Ssaidi@eecs.umich.edu 0x06: FailUnimpl::edge16l(); 8603941Ssaidi@eecs.umich.edu 0x07: FailUnimpl::edge16ln(); 8613941Ssaidi@eecs.umich.edu 0x08: FailUnimpl::edge32(); 8623941Ssaidi@eecs.umich.edu 0x09: FailUnimpl::edge32n(); 8633941Ssaidi@eecs.umich.edu 0x0A: FailUnimpl::edge32l(); 8643941Ssaidi@eecs.umich.edu 0x0B: FailUnimpl::edge32ln(); 8653941Ssaidi@eecs.umich.edu 0x10: FailUnimpl::array8(); 8663941Ssaidi@eecs.umich.edu 0x12: FailUnimpl::array16(); 8673941Ssaidi@eecs.umich.edu 0x14: FailUnimpl::array32(); 8683042Sgblack@eecs.umich.edu 0x18: BasicOperate::alignaddr({{ 8692963Sgblack@eecs.umich.edu uint64_t sum = Rs1 + Rs2; 8703042Sgblack@eecs.umich.edu Rd = sum & ~7; 8712963Sgblack@eecs.umich.edu Gsr = (Gsr & ~7) | (sum & 7); 8722963Sgblack@eecs.umich.edu }}); 8733941Ssaidi@eecs.umich.edu 0x19: FailUnimpl::bmask(); 8742963Sgblack@eecs.umich.edu 0x1A: BasicOperate::alignaddresslittle({{ 8752963Sgblack@eecs.umich.edu uint64_t sum = Rs1 + Rs2; 8763042Sgblack@eecs.umich.edu Rd = sum & ~7; 8772963Sgblack@eecs.umich.edu Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 8782963Sgblack@eecs.umich.edu }}); 8793941Ssaidi@eecs.umich.edu 0x20: FailUnimpl::fcmple16(); 8803941Ssaidi@eecs.umich.edu 0x22: FailUnimpl::fcmpne16(); 8813941Ssaidi@eecs.umich.edu 0x24: FailUnimpl::fcmple32(); 8823941Ssaidi@eecs.umich.edu 0x26: FailUnimpl::fcmpne32(); 8833941Ssaidi@eecs.umich.edu 0x28: FailUnimpl::fcmpgt16(); 8843941Ssaidi@eecs.umich.edu 0x2A: FailUnimpl::fcmpeq16(); 8853941Ssaidi@eecs.umich.edu 0x2C: FailUnimpl::fcmpgt32(); 8863941Ssaidi@eecs.umich.edu 0x2E: FailUnimpl::fcmpeq32(); 8873941Ssaidi@eecs.umich.edu 0x31: FailUnimpl::fmul8x16(); 8883941Ssaidi@eecs.umich.edu 0x33: FailUnimpl::fmul8x16au(); 8893941Ssaidi@eecs.umich.edu 0x35: FailUnimpl::fmul8x16al(); 8903941Ssaidi@eecs.umich.edu 0x36: FailUnimpl::fmul8sux16(); 8913941Ssaidi@eecs.umich.edu 0x37: FailUnimpl::fmul8ulx16(); 8923941Ssaidi@eecs.umich.edu 0x38: FailUnimpl::fmuld8sux16(); 8933941Ssaidi@eecs.umich.edu 0x39: FailUnimpl::fmuld8ulx16(); 8942954Sgblack@eecs.umich.edu 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 8952954Sgblack@eecs.umich.edu 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 8962954Sgblack@eecs.umich.edu 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 8972954Sgblack@eecs.umich.edu 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 8982963Sgblack@eecs.umich.edu 0x48: BasicOperate::faligndata({{ 8993057Sgblack@eecs.umich.edu uint64_t msbX = Frs1.udw; 9003057Sgblack@eecs.umich.edu uint64_t lsbX = Frs2.udw; 9013057Sgblack@eecs.umich.edu //Some special cases need to be split out, first 9023057Sgblack@eecs.umich.edu //because they're the most likely to be used, and 9033057Sgblack@eecs.umich.edu //second because otherwise, we end up shifting by 9043057Sgblack@eecs.umich.edu //greater than the width of the type being shifted, 9053057Sgblack@eecs.umich.edu //namely 64, which produces undefined results according 9063057Sgblack@eecs.umich.edu //to the C standard. 9073057Sgblack@eecs.umich.edu switch(Gsr<2:0>) 9083057Sgblack@eecs.umich.edu { 9093057Sgblack@eecs.umich.edu case 0: 9103057Sgblack@eecs.umich.edu Frd.udw = msbX; 9113057Sgblack@eecs.umich.edu break; 9123057Sgblack@eecs.umich.edu case 8: 9133057Sgblack@eecs.umich.edu Frd.udw = lsbX; 9143057Sgblack@eecs.umich.edu break; 9153057Sgblack@eecs.umich.edu default: 9163057Sgblack@eecs.umich.edu uint64_t msbShift = Gsr<2:0> * 8; 9173057Sgblack@eecs.umich.edu uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 9183057Sgblack@eecs.umich.edu uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 9193057Sgblack@eecs.umich.edu uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 9203057Sgblack@eecs.umich.edu Frd.udw = ((msbX & msbMask) << msbShift) | 9213057Sgblack@eecs.umich.edu ((lsbX & lsbMask) >> lsbShift); 9223057Sgblack@eecs.umich.edu } 9232963Sgblack@eecs.umich.edu }}); 9242954Sgblack@eecs.umich.edu 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 9253941Ssaidi@eecs.umich.edu 0x4C: FailUnimpl::bshuffle(); 9263941Ssaidi@eecs.umich.edu 0x4D: FailUnimpl::fexpand(); 9273941Ssaidi@eecs.umich.edu 0x50: FailUnimpl::fpadd16(); 9283941Ssaidi@eecs.umich.edu 0x51: FailUnimpl::fpadd16s(); 9293941Ssaidi@eecs.umich.edu 0x52: FailUnimpl::fpadd32(); 9303941Ssaidi@eecs.umich.edu 0x53: FailUnimpl::fpadd32s(); 9313941Ssaidi@eecs.umich.edu 0x54: FailUnimpl::fpsub16(); 9323941Ssaidi@eecs.umich.edu 0x55: FailUnimpl::fpsub16s(); 9333941Ssaidi@eecs.umich.edu 0x56: FailUnimpl::fpsub32(); 9343941Ssaidi@eecs.umich.edu 0x57: FailUnimpl::fpsub32s(); 9354008Ssaidi@eecs.umich.edu 0x60: FpBasic::fzero({{Frd.df = 0;}}); 9364008Ssaidi@eecs.umich.edu 0x61: FpBasic::fzeros({{Frds.sf = 0;}}); 9373941Ssaidi@eecs.umich.edu 0x62: FailUnimpl::fnor(); 9383941Ssaidi@eecs.umich.edu 0x63: FailUnimpl::fnors(); 9393941Ssaidi@eecs.umich.edu 0x64: FailUnimpl::fandnot2(); 9403941Ssaidi@eecs.umich.edu 0x65: FailUnimpl::fandnot2s(); 9414008Ssaidi@eecs.umich.edu 0x66: FpBasic::fnot2({{ 9422963Sgblack@eecs.umich.edu Frd.df = (double)(~((uint64_t)Frs2.df)); 9432963Sgblack@eecs.umich.edu }}); 9444008Ssaidi@eecs.umich.edu 0x67: FpBasic::fnot2s({{ 9453279Sgblack@eecs.umich.edu Frds.sf = (float)(~((uint32_t)Frs2s.sf)); 9462963Sgblack@eecs.umich.edu }}); 9473941Ssaidi@eecs.umich.edu 0x68: FailUnimpl::fandnot1(); 9483941Ssaidi@eecs.umich.edu 0x69: FailUnimpl::fandnot1s(); 9494008Ssaidi@eecs.umich.edu 0x6A: FpBasic::fnot1({{ 9502963Sgblack@eecs.umich.edu Frd.df = (double)(~((uint64_t)Frs1.df)); 9512963Sgblack@eecs.umich.edu }}); 9524008Ssaidi@eecs.umich.edu 0x6B: FpBasic::fnot1s({{ 9533279Sgblack@eecs.umich.edu Frds.sf = (float)(~((uint32_t)Frs1s.sf)); 9542963Sgblack@eecs.umich.edu }}); 9553941Ssaidi@eecs.umich.edu 0x6C: FailUnimpl::fxor(); 9563941Ssaidi@eecs.umich.edu 0x6D: FailUnimpl::fxors(); 9573941Ssaidi@eecs.umich.edu 0x6E: FailUnimpl::fnand(); 9583941Ssaidi@eecs.umich.edu 0x6F: FailUnimpl::fnands(); 9593941Ssaidi@eecs.umich.edu 0x70: FailUnimpl::fand(); 9603941Ssaidi@eecs.umich.edu 0x71: FailUnimpl::fands(); 9613941Ssaidi@eecs.umich.edu 0x72: FailUnimpl::fxnor(); 9623941Ssaidi@eecs.umich.edu 0x73: FailUnimpl::fxnors(); 9634008Ssaidi@eecs.umich.edu 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}}); 9644008Ssaidi@eecs.umich.edu 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}}); 9653941Ssaidi@eecs.umich.edu 0x76: FailUnimpl::fornot2(); 9663941Ssaidi@eecs.umich.edu 0x77: FailUnimpl::fornot2s(); 9674008Ssaidi@eecs.umich.edu 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}}); 9684008Ssaidi@eecs.umich.edu 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}}); 9693941Ssaidi@eecs.umich.edu 0x7A: FailUnimpl::fornot1(); 9703941Ssaidi@eecs.umich.edu 0x7B: FailUnimpl::fornot1s(); 9713941Ssaidi@eecs.umich.edu 0x7C: FailUnimpl::for(); 9723941Ssaidi@eecs.umich.edu 0x7D: FailUnimpl::fors(); 9734008Ssaidi@eecs.umich.edu 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}}); 9744008Ssaidi@eecs.umich.edu 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}}); 9752954Sgblack@eecs.umich.edu 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 9763941Ssaidi@eecs.umich.edu 0x81: FailUnimpl::siam(); 9772954Sgblack@eecs.umich.edu } 9784090Ssaidi@eecs.umich.edu // M5 special opcodes use the reserved IMPDEP2A opcode space 9794090Ssaidi@eecs.umich.edu 0x37: decode M5FUNC { 9804096Sgblack@eecs.umich.edu#if FULL_SYSTEM 9814113Sgblack@eecs.umich.edu format BasicOperate { 9824113Sgblack@eecs.umich.edu // we have 7 bits of space here to play with... 9834113Sgblack@eecs.umich.edu 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); 9844113Sgblack@eecs.umich.edu }}, No_OpClass, IsNonSpeculative); 9854113Sgblack@eecs.umich.edu 0x50: m5readfile({{ 9864113Sgblack@eecs.umich.edu O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2); 9874113Sgblack@eecs.umich.edu }}, IsNonSpeculative); 9884113Sgblack@eecs.umich.edu 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase()); 9894113Sgblack@eecs.umich.edu }}, IsNonSpeculative); 9904113Sgblack@eecs.umich.edu 0x54: m5panic({{ 9914113Sgblack@eecs.umich.edu panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 9924113Sgblack@eecs.umich.edu }}, No_OpClass, IsNonSpeculative); 9934113Sgblack@eecs.umich.edu } 9944096Sgblack@eecs.umich.edu#endif 9954096Sgblack@eecs.umich.edu default: Trap::impdep2({{fault = new IllegalInstruction;}}); 9964090Ssaidi@eecs.umich.edu } 9972526SN/A 0x38: Branch::jmpl({{ 9982526SN/A Addr target = Rs1 + Rs2_or_imm13; 9992526SN/A if(target & 0x3) 10002526SN/A fault = new MemAddressNotAligned; 10012526SN/A else 10022526SN/A { 10033928Ssaidi@eecs.umich.edu if (Pstate<3:>) 10043929Ssaidi@eecs.umich.edu Rd = (xc->readPC())<31:0>; 10053928Ssaidi@eecs.umich.edu else 10063928Ssaidi@eecs.umich.edu Rd = xc->readPC(); 10072526SN/A NNPC = target; 10082526SN/A } 10092526SN/A }}); 10102526SN/A 0x39: Branch::return({{ 10112526SN/A Addr target = Rs1 + Rs2_or_imm13; 10122561SN/A if(fault == NoFault) 10132561SN/A { 10143765Sgblack@eecs.umich.edu //Check for fills which are higher priority than alignment 10153765Sgblack@eecs.umich.edu //faults. 10162561SN/A if(Canrestore == 0) 10172561SN/A { 10182561SN/A if(Otherwin) 10193909Ssaidi@eecs.umich.edu fault = new FillNOther(4*Wstate<5:3>); 10202561SN/A else 10213909Ssaidi@eecs.umich.edu fault = new FillNNormal(4*Wstate<2:0>); 10222561SN/A } 10233765Sgblack@eecs.umich.edu //Check for alignment faults 10243765Sgblack@eecs.umich.edu else if(target & 0x3) 10253765Sgblack@eecs.umich.edu fault = new MemAddressNotAligned; 10262561SN/A else 10272561SN/A { 10283765Sgblack@eecs.umich.edu NNPC = target; 10293417Sgblack@eecs.umich.edu Cwp = (Cwp - 1 + NWindows) % NWindows; 10302561SN/A Cansave = Cansave + 1; 10312561SN/A Canrestore = Canrestore - 1; 10322561SN/A } 10332561SN/A } 10342526SN/A }}); 10352526SN/A 0x3A: decode CC 10362526SN/A { 10372526SN/A 0x0: Trap::tcci({{ 10382646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<3:0>, COND2)) 10392561SN/A { 10402561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 10412561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 10423531Sgblack@eecs.umich.edu fault = new TrapInstruction(lTrapNum); 10432561SN/A } 10444828Sgblack@eecs.umich.edu }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 10452526SN/A 0x2: Trap::tccx({{ 10462646Ssaidi@eecs.umich.edu if(passesCondition(Ccr<7:4>, COND2)) 10472561SN/A { 10482561SN/A int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 10492561SN/A DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 10503531Sgblack@eecs.umich.edu fault = new TrapInstruction(lTrapNum); 10512526SN/A } 10524828Sgblack@eecs.umich.edu }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 10532526SN/A } 10544090Ssaidi@eecs.umich.edu 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, 10554090Ssaidi@eecs.umich.edu MemWriteOp); 10562526SN/A 0x3C: save({{ 10572526SN/A if(Cansave == 0) 10582526SN/A { 10592526SN/A if(Otherwin) 10603909Ssaidi@eecs.umich.edu fault = new SpillNOther(4*Wstate<5:3>); 10612526SN/A else 10623909Ssaidi@eecs.umich.edu fault = new SpillNNormal(4*Wstate<2:0>); 10632526SN/A } 10642526SN/A else if(Cleanwin - Canrestore == 0) 10652526SN/A { 10662526SN/A fault = new CleanWindow; 10672526SN/A } 10682526SN/A else 10692526SN/A { 10702526SN/A Cwp = (Cwp + 1) % NWindows; 10713765Sgblack@eecs.umich.edu Rd_next = Rs1 + Rs2_or_imm13; 10722561SN/A Cansave = Cansave - 1; 10732561SN/A Canrestore = Canrestore + 1; 10742526SN/A } 10752526SN/A }}); 10762526SN/A 0x3D: restore({{ 10772526SN/A if(Canrestore == 0) 10782526SN/A { 10792526SN/A if(Otherwin) 10803909Ssaidi@eecs.umich.edu fault = new FillNOther(4*Wstate<5:3>); 10812526SN/A else 10823909Ssaidi@eecs.umich.edu fault = new FillNNormal(4*Wstate<2:0>); 10832526SN/A } 10842526SN/A else 10852526SN/A { 10863417Sgblack@eecs.umich.edu Cwp = (Cwp - 1 + NWindows) % NWindows; 10873765Sgblack@eecs.umich.edu Rd_prev = Rs1 + Rs2_or_imm13; 10882561SN/A Cansave = Cansave + 1; 10892561SN/A Canrestore = Canrestore - 1; 10902526SN/A } 10912526SN/A }}); 10922526SN/A 0x3E: decode FCN { 10932526SN/A 0x0: Priv::done({{ 10942646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 10952646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 10962646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 10972646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 10982646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 10993825Ssaidi@eecs.umich.edu Hpstate = Htstate; 11002646Ssaidi@eecs.umich.edu NPC = Tnpc; 11012646Ssaidi@eecs.umich.edu NNPC = Tnpc + 4; 11022526SN/A Tl = Tl - 1; 11035094Sgblack@eecs.umich.edu }}, checkTl=true); 11042938Sgblack@eecs.umich.edu 0x1: Priv::retry({{ 11052646Ssaidi@eecs.umich.edu Cwp = Tstate<4:0>; 11062646Ssaidi@eecs.umich.edu Pstate = Tstate<20:8>; 11072646Ssaidi@eecs.umich.edu Asi = Tstate<31:24>; 11082646Ssaidi@eecs.umich.edu Ccr = Tstate<39:32>; 11092646Ssaidi@eecs.umich.edu Gl = Tstate<42:40>; 11103826Ssaidi@eecs.umich.edu Hpstate = Htstate; 11112646Ssaidi@eecs.umich.edu NPC = Tpc; 11123417Sgblack@eecs.umich.edu NNPC = Tnpc; 11132526SN/A Tl = Tl - 1; 11145094Sgblack@eecs.umich.edu }}, checkTl=true); 11152526SN/A } 11162526SN/A } 11172469SN/A } 11182469SN/A 0x3: decode OP3 { 11192526SN/A format Load { 11203272Sgblack@eecs.umich.edu 0x00: lduw({{Rd = Mem.uw;}}); 11213272Sgblack@eecs.umich.edu 0x01: ldub({{Rd = Mem.ub;}}); 11223272Sgblack@eecs.umich.edu 0x02: lduh({{Rd = Mem.uhw;}}); 11233835Sgblack@eecs.umich.edu 0x03: ldtw({{ 11244115Ssaidi@eecs.umich.edu RdLow = (Mem.tuw).a; 11254115Ssaidi@eecs.umich.edu RdHigh = (Mem.tuw).b; 11263272Sgblack@eecs.umich.edu }}); 11272526SN/A } 11282526SN/A format Store { 11293272Sgblack@eecs.umich.edu 0x04: stw({{Mem.uw = Rd.sw;}}); 11303272Sgblack@eecs.umich.edu 0x05: stb({{Mem.ub = Rd.sb;}}); 11313272Sgblack@eecs.umich.edu 0x06: sth({{Mem.uhw = Rd.shw;}}); 11324224Sgblack@eecs.umich.edu 0x07: sttw({{ 11334256Sgblack@eecs.umich.edu //This temporary needs to be here so that the parser 11344256Sgblack@eecs.umich.edu //will correctly identify this instruction as a store. 11354256Sgblack@eecs.umich.edu //It's probably either the parenthesis or referencing 11364256Sgblack@eecs.umich.edu //the member variable that throws confuses it. 11374256Sgblack@eecs.umich.edu Twin32_t temp; 11384256Sgblack@eecs.umich.edu temp.a = RdLow<31:0>; 11394256Sgblack@eecs.umich.edu temp.b = RdHigh<31:0>; 11404256Sgblack@eecs.umich.edu Mem.tuw = temp; 11414224Sgblack@eecs.umich.edu }}); 11422526SN/A } 11432526SN/A format Load { 11443272Sgblack@eecs.umich.edu 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 11453272Sgblack@eecs.umich.edu 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 11463272Sgblack@eecs.umich.edu 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 11473272Sgblack@eecs.umich.edu 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 11482526SN/A } 11494040Ssaidi@eecs.umich.edu 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}}, 11504040Ssaidi@eecs.umich.edu {{ 11514040Ssaidi@eecs.umich.edu uint8_t tmp = mem_data; 11524040Ssaidi@eecs.umich.edu Rd.ub = tmp; 11534040Ssaidi@eecs.umich.edu }}, MEM_SWAP); 11543272Sgblack@eecs.umich.edu 0x0E: Store::stx({{Mem.udw = Rd}}); 11554040Ssaidi@eecs.umich.edu 0x0F: Swap::swap({{Mem.uw = Rd.uw}}, 11564040Ssaidi@eecs.umich.edu {{ 11574040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 11584040Ssaidi@eecs.umich.edu Rd.uw = tmp; 11594040Ssaidi@eecs.umich.edu }}, MEM_SWAP); 11603810Sgblack@eecs.umich.edu format LoadAlt { 11613810Sgblack@eecs.umich.edu 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 11623810Sgblack@eecs.umich.edu 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); 11633810Sgblack@eecs.umich.edu 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); 11643856Ssaidi@eecs.umich.edu 0x13: decode EXT_ASI { 11653926Ssaidi@eecs.umich.edu //ASI_LDTD_AIUP 11663926Ssaidi@eecs.umich.edu 0x22: TwinLoad::ldtx_aiup( 11674040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11684040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 11693926Ssaidi@eecs.umich.edu //ASI_LDTD_AIUS 11703926Ssaidi@eecs.umich.edu 0x23: TwinLoad::ldtx_aius( 11714040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11724040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 11733856Ssaidi@eecs.umich.edu //ASI_QUAD_LDD 11743856Ssaidi@eecs.umich.edu 0x24: TwinLoad::ldtx_quad_ldd( 11754040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11764040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 11773856Ssaidi@eecs.umich.edu //ASI_LDTX_REAL 11783856Ssaidi@eecs.umich.edu 0x26: TwinLoad::ldtx_real( 11794040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11804040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 11814040Ssaidi@eecs.umich.edu //ASI_LDTX_N 11824040Ssaidi@eecs.umich.edu 0x27: TwinLoad::ldtx_n( 11834040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11844040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 11854040Ssaidi@eecs.umich.edu //ASI_LDTX_AIUP_L 11864040Ssaidi@eecs.umich.edu 0x2A: TwinLoad::ldtx_aiup_l( 11874040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11884040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 11894040Ssaidi@eecs.umich.edu //ASI_LDTX_AIUS_L 11904040Ssaidi@eecs.umich.edu 0x2B: TwinLoad::ldtx_aius_l( 11914040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11924040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 11934040Ssaidi@eecs.umich.edu //ASI_LDTX_L 11944040Ssaidi@eecs.umich.edu 0x2C: TwinLoad::ldtx_l( 11954040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 11964040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 11973856Ssaidi@eecs.umich.edu //ASI_LDTX_REAL_L 11983856Ssaidi@eecs.umich.edu 0x2E: TwinLoad::ldtx_real_l( 11994040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12004040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12013856Ssaidi@eecs.umich.edu //ASI_LDTX_N_L 12023856Ssaidi@eecs.umich.edu 0x2F: TwinLoad::ldtx_n_l( 12034040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12044040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12053901Ssaidi@eecs.umich.edu //ASI_LDTX_P 12063901Ssaidi@eecs.umich.edu 0xE2: TwinLoad::ldtx_p( 12074040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12084040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12093926Ssaidi@eecs.umich.edu //ASI_LDTX_S 12103926Ssaidi@eecs.umich.edu 0xE3: TwinLoad::ldtx_s( 12114040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12124040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12134040Ssaidi@eecs.umich.edu //ASI_LDTX_PL 12144040Ssaidi@eecs.umich.edu 0xEA: TwinLoad::ldtx_pl( 12154040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12164040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12174040Ssaidi@eecs.umich.edu //ASI_LDTX_SL 12184040Ssaidi@eecs.umich.edu 0xEB: TwinLoad::ldtx_sl( 12194040Ssaidi@eecs.umich.edu {{RdLow.udw = (Mem.tudw).a; 12204040Ssaidi@eecs.umich.edu RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 12213856Ssaidi@eecs.umich.edu default: ldtwa({{ 12224115Ssaidi@eecs.umich.edu RdLow = (Mem.tuw).a; 12234115Ssaidi@eecs.umich.edu RdHigh = (Mem.tuw).b; 12243856Ssaidi@eecs.umich.edu }}, {{EXT_ASI}}); 12253856Ssaidi@eecs.umich.edu } 12262526SN/A } 12273810Sgblack@eecs.umich.edu format StoreAlt { 12283810Sgblack@eecs.umich.edu 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}}); 12293810Sgblack@eecs.umich.edu 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}}); 12303810Sgblack@eecs.umich.edu 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}}); 12314224Sgblack@eecs.umich.edu 0x17: sttwa({{ 12324256Sgblack@eecs.umich.edu //This temporary needs to be here so that the parser 12334256Sgblack@eecs.umich.edu //will correctly identify this instruction as a store. 12344256Sgblack@eecs.umich.edu //It's probably either the parenthesis or referencing 12354256Sgblack@eecs.umich.edu //the member variable that throws confuses it. 12364256Sgblack@eecs.umich.edu Twin32_t temp; 12374256Sgblack@eecs.umich.edu temp.a = RdLow<31:0>; 12384256Sgblack@eecs.umich.edu temp.b = RdHigh<31:0>; 12394256Sgblack@eecs.umich.edu Mem.tuw = temp; 12404224Sgblack@eecs.umich.edu }}, {{EXT_ASI}}); 12412526SN/A } 12423810Sgblack@eecs.umich.edu format LoadAlt { 12433810Sgblack@eecs.umich.edu 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}}); 12443810Sgblack@eecs.umich.edu 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}}); 12453810Sgblack@eecs.umich.edu 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}}); 12463810Sgblack@eecs.umich.edu 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}}); 12472526SN/A } 12484040Ssaidi@eecs.umich.edu 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, 12494040Ssaidi@eecs.umich.edu {{ 12504040Ssaidi@eecs.umich.edu uint8_t tmp = mem_data; 12514040Ssaidi@eecs.umich.edu Rd.ub = tmp; 12524040Ssaidi@eecs.umich.edu }}, {{EXT_ASI}}, MEM_SWAP); 12533810Sgblack@eecs.umich.edu 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}}); 12544040Ssaidi@eecs.umich.edu 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}}, 12554040Ssaidi@eecs.umich.edu {{ 12564040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 12574040Ssaidi@eecs.umich.edu Rd.uw = tmp; 12584040Ssaidi@eecs.umich.edu }}, {{EXT_ASI}}, MEM_SWAP); 12594040Ssaidi@eecs.umich.edu 12602526SN/A format Trap { 12613931Ssaidi@eecs.umich.edu 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); 12624008Ssaidi@eecs.umich.edu 0x21: decode RD { 12634011Ssaidi@eecs.umich.edu 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc); 12644011Ssaidi@eecs.umich.edu if (fault) 12654011Ssaidi@eecs.umich.edu return fault; 12664011Ssaidi@eecs.umich.edu Fsr = Mem.uw | Fsr<63:32>;}}); 12674011Ssaidi@eecs.umich.edu 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc); 12684011Ssaidi@eecs.umich.edu if (fault) 12694011Ssaidi@eecs.umich.edu return fault; 12704011Ssaidi@eecs.umich.edu Fsr = Mem.udw;}}); 12714008Ssaidi@eecs.umich.edu default: FailUnimpl::ldfsrOther(); 12722469SN/A } 12732526SN/A 0x22: ldqf({{fault = new FpDisabled;}}); 12743272Sgblack@eecs.umich.edu 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 12753931Ssaidi@eecs.umich.edu 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 12764008Ssaidi@eecs.umich.edu 0x25: decode RD { 12774011Ssaidi@eecs.umich.edu 0x0: Store::stfsr({{fault = checkFpEnableFault(xc); 12784011Ssaidi@eecs.umich.edu if (fault) 12794011Ssaidi@eecs.umich.edu return fault; 12804011Ssaidi@eecs.umich.edu Mem.uw = Fsr<31:0>; 12814008Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr,16,14,0);}}); 12824011Ssaidi@eecs.umich.edu 0x1: Store::stxfsr({{fault = checkFpEnableFault(xc); 12834011Ssaidi@eecs.umich.edu if (fault) 12844011Ssaidi@eecs.umich.edu return fault; 12854011Ssaidi@eecs.umich.edu Mem.udw = Fsr; 12864011Ssaidi@eecs.umich.edu Fsr = insertBits(Fsr,16,14,0);}}); 12874008Ssaidi@eecs.umich.edu default: FailUnimpl::stfsrOther(); 12882526SN/A } 12892526SN/A 0x26: stqf({{fault = new FpDisabled;}}); 12903272Sgblack@eecs.umich.edu 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 12912526SN/A 0x2D: Nop::prefetch({{ }}); 12923931Ssaidi@eecs.umich.edu 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}}); 12932526SN/A 0x32: ldqfa({{fault = new FpDisabled;}}); 12943272Sgblack@eecs.umich.edu format LoadAlt { 12953272Sgblack@eecs.umich.edu 0x33: decode EXT_ASI { 12963272Sgblack@eecs.umich.edu //ASI_NUCLEUS 12973272Sgblack@eecs.umich.edu 0x04: FailUnimpl::lddfa_n(); 12983272Sgblack@eecs.umich.edu //ASI_NUCLEUS_LITTLE 12993272Sgblack@eecs.umich.edu 0x0C: FailUnimpl::lddfa_nl(); 13003272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY 13013272Sgblack@eecs.umich.edu 0x10: FailUnimpl::lddfa_aiup(); 13023272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY_LITTLE 13033272Sgblack@eecs.umich.edu 0x18: FailUnimpl::lddfa_aiupl(); 13043272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY 13053272Sgblack@eecs.umich.edu 0x11: FailUnimpl::lddfa_aius(); 13063272Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY_LITTLE 13073272Sgblack@eecs.umich.edu 0x19: FailUnimpl::lddfa_aiusl(); 13083272Sgblack@eecs.umich.edu //ASI_REAL 13093272Sgblack@eecs.umich.edu 0x14: FailUnimpl::lddfa_real(); 13103272Sgblack@eecs.umich.edu //ASI_REAL_LITTLE 13113272Sgblack@eecs.umich.edu 0x1C: FailUnimpl::lddfa_real_l(); 13123272Sgblack@eecs.umich.edu //ASI_REAL_IO 13133272Sgblack@eecs.umich.edu 0x15: FailUnimpl::lddfa_real_io(); 13143272Sgblack@eecs.umich.edu //ASI_REAL_IO_LITTLE 13153272Sgblack@eecs.umich.edu 0x1D: FailUnimpl::lddfa_real_io_l(); 13163272Sgblack@eecs.umich.edu //ASI_PRIMARY 13173272Sgblack@eecs.umich.edu 0x80: FailUnimpl::lddfa_p(); 13183272Sgblack@eecs.umich.edu //ASI_PRIMARY_LITTLE 13193272Sgblack@eecs.umich.edu 0x88: FailUnimpl::lddfa_pl(); 13203272Sgblack@eecs.umich.edu //ASI_SECONDARY 13213272Sgblack@eecs.umich.edu 0x81: FailUnimpl::lddfa_s(); 13223272Sgblack@eecs.umich.edu //ASI_SECONDARY_LITTLE 13233272Sgblack@eecs.umich.edu 0x89: FailUnimpl::lddfa_sl(); 13243272Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT 13253272Sgblack@eecs.umich.edu 0x82: FailUnimpl::lddfa_pnf(); 13263272Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT_LITTLE 13273272Sgblack@eecs.umich.edu 0x8A: FailUnimpl::lddfa_pnfl(); 13283272Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT 13293272Sgblack@eecs.umich.edu 0x83: FailUnimpl::lddfa_snf(); 13303272Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT_LITTLE 13313272Sgblack@eecs.umich.edu 0x8B: FailUnimpl::lddfa_snfl(); 13323272Sgblack@eecs.umich.edu 13333272Sgblack@eecs.umich.edu format BlockLoad { 13343272Sgblack@eecs.umich.edu // LDBLOCKF 13353272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY 13363272Sgblack@eecs.umich.edu 0x16: FailUnimpl::ldblockf_aiup(); 13373272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY 13383272Sgblack@eecs.umich.edu 0x17: FailUnimpl::ldblockf_aius(); 13393272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 13403272Sgblack@eecs.umich.edu 0x1E: FailUnimpl::ldblockf_aiupl(); 13413272Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 13423272Sgblack@eecs.umich.edu 0x1F: FailUnimpl::ldblockf_aiusl(); 13433272Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY 13443810Sgblack@eecs.umich.edu 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}}); 13453272Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY 13463272Sgblack@eecs.umich.edu 0xF1: FailUnimpl::ldblockf_s(); 13473272Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY_LITTLE 13483272Sgblack@eecs.umich.edu 0xF8: FailUnimpl::ldblockf_pl(); 13493272Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY_LITTLE 13503272Sgblack@eecs.umich.edu 0xF9: FailUnimpl::ldblockf_sl(); 13513272Sgblack@eecs.umich.edu } 13523272Sgblack@eecs.umich.edu 13533272Sgblack@eecs.umich.edu //LDSHORTF 13543272Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY 13553272Sgblack@eecs.umich.edu 0xD0: FailUnimpl::ldshortf_8p(); 13563272Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY 13573272Sgblack@eecs.umich.edu 0xD1: FailUnimpl::ldshortf_8s(); 13583272Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY_LITTLE 13593272Sgblack@eecs.umich.edu 0xD8: FailUnimpl::ldshortf_8pl(); 13603272Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY_LITTLE 13613272Sgblack@eecs.umich.edu 0xD9: FailUnimpl::ldshortf_8sl(); 13623272Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY 13633272Sgblack@eecs.umich.edu 0xD2: FailUnimpl::ldshortf_16p(); 13643272Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY 13653272Sgblack@eecs.umich.edu 0xD3: FailUnimpl::ldshortf_16s(); 13663272Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY_LITTLE 13673272Sgblack@eecs.umich.edu 0xDA: FailUnimpl::ldshortf_16pl(); 13683272Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY_LITTLE 13693272Sgblack@eecs.umich.edu 0xDB: FailUnimpl::ldshortf_16sl(); 13703272Sgblack@eecs.umich.edu //Not an ASI which is legal with lddfa 13713378Sgblack@eecs.umich.edu default: Trap::lddfa_bad_asi( 13723378Sgblack@eecs.umich.edu {{fault = new DataAccessException;}}); 13733272Sgblack@eecs.umich.edu } 13743272Sgblack@eecs.umich.edu } 13753931Ssaidi@eecs.umich.edu 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); 13762954Sgblack@eecs.umich.edu 0x36: stqfa({{fault = new FpDisabled;}}); 13773378Sgblack@eecs.umich.edu format StoreAlt { 13783378Sgblack@eecs.umich.edu 0x37: decode EXT_ASI { 13793378Sgblack@eecs.umich.edu //ASI_NUCLEUS 13803378Sgblack@eecs.umich.edu 0x04: FailUnimpl::stdfa_n(); 13813378Sgblack@eecs.umich.edu //ASI_NUCLEUS_LITTLE 13823378Sgblack@eecs.umich.edu 0x0C: FailUnimpl::stdfa_nl(); 13833378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY 13843378Sgblack@eecs.umich.edu 0x10: FailUnimpl::stdfa_aiup(); 13853378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_PRIMARY_LITTLE 13863378Sgblack@eecs.umich.edu 0x18: FailUnimpl::stdfa_aiupl(); 13873378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY 13883378Sgblack@eecs.umich.edu 0x11: FailUnimpl::stdfa_aius(); 13893378Sgblack@eecs.umich.edu //ASI_AS_IF_USER_SECONDARY_LITTLE 13903378Sgblack@eecs.umich.edu 0x19: FailUnimpl::stdfa_aiusl(); 13913378Sgblack@eecs.umich.edu //ASI_REAL 13923378Sgblack@eecs.umich.edu 0x14: FailUnimpl::stdfa_real(); 13933378Sgblack@eecs.umich.edu //ASI_REAL_LITTLE 13943378Sgblack@eecs.umich.edu 0x1C: FailUnimpl::stdfa_real_l(); 13953378Sgblack@eecs.umich.edu //ASI_REAL_IO 13963378Sgblack@eecs.umich.edu 0x15: FailUnimpl::stdfa_real_io(); 13973378Sgblack@eecs.umich.edu //ASI_REAL_IO_LITTLE 13983378Sgblack@eecs.umich.edu 0x1D: FailUnimpl::stdfa_real_io_l(); 13993378Sgblack@eecs.umich.edu //ASI_PRIMARY 14003378Sgblack@eecs.umich.edu 0x80: FailUnimpl::stdfa_p(); 14013378Sgblack@eecs.umich.edu //ASI_PRIMARY_LITTLE 14023378Sgblack@eecs.umich.edu 0x88: FailUnimpl::stdfa_pl(); 14033378Sgblack@eecs.umich.edu //ASI_SECONDARY 14043378Sgblack@eecs.umich.edu 0x81: FailUnimpl::stdfa_s(); 14053378Sgblack@eecs.umich.edu //ASI_SECONDARY_LITTLE 14063378Sgblack@eecs.umich.edu 0x89: FailUnimpl::stdfa_sl(); 14073378Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT 14083378Sgblack@eecs.umich.edu 0x82: FailUnimpl::stdfa_pnf(); 14093378Sgblack@eecs.umich.edu //ASI_PRIMARY_NO_FAULT_LITTLE 14103378Sgblack@eecs.umich.edu 0x8A: FailUnimpl::stdfa_pnfl(); 14113378Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT 14123378Sgblack@eecs.umich.edu 0x83: FailUnimpl::stdfa_snf(); 14133378Sgblack@eecs.umich.edu //ASI_SECONDARY_NO_FAULT_LITTLE 14143378Sgblack@eecs.umich.edu 0x8B: FailUnimpl::stdfa_snfl(); 14153378Sgblack@eecs.umich.edu 14163378Sgblack@eecs.umich.edu format BlockStore { 14173378Sgblack@eecs.umich.edu // STBLOCKF 14183378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY 14193378Sgblack@eecs.umich.edu 0x16: FailUnimpl::stblockf_aiup(); 14203378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY 14213378Sgblack@eecs.umich.edu 0x17: FailUnimpl::stblockf_aius(); 14223378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 14233378Sgblack@eecs.umich.edu 0x1E: FailUnimpl::stblockf_aiupl(); 14243378Sgblack@eecs.umich.edu //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 14253378Sgblack@eecs.umich.edu 0x1F: FailUnimpl::stblockf_aiusl(); 14263378Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY 14273810Sgblack@eecs.umich.edu 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}}); 14283378Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY 14293378Sgblack@eecs.umich.edu 0xF1: FailUnimpl::stblockf_s(); 14303378Sgblack@eecs.umich.edu //ASI_BLOCK_PRIMARY_LITTLE 14313378Sgblack@eecs.umich.edu 0xF8: FailUnimpl::stblockf_pl(); 14323378Sgblack@eecs.umich.edu //ASI_BLOCK_SECONDARY_LITTLE 14333378Sgblack@eecs.umich.edu 0xF9: FailUnimpl::stblockf_sl(); 14343378Sgblack@eecs.umich.edu } 14353378Sgblack@eecs.umich.edu 14363378Sgblack@eecs.umich.edu //STSHORTF 14373378Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY 14383378Sgblack@eecs.umich.edu 0xD0: FailUnimpl::stshortf_8p(); 14393378Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY 14403378Sgblack@eecs.umich.edu 0xD1: FailUnimpl::stshortf_8s(); 14413378Sgblack@eecs.umich.edu //ASI_FL8_PRIMARY_LITTLE 14423378Sgblack@eecs.umich.edu 0xD8: FailUnimpl::stshortf_8pl(); 14433378Sgblack@eecs.umich.edu //ASI_FL8_SECONDARY_LITTLE 14443378Sgblack@eecs.umich.edu 0xD9: FailUnimpl::stshortf_8sl(); 14453378Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY 14463378Sgblack@eecs.umich.edu 0xD2: FailUnimpl::stshortf_16p(); 14473378Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY 14483378Sgblack@eecs.umich.edu 0xD3: FailUnimpl::stshortf_16s(); 14493378Sgblack@eecs.umich.edu //ASI_FL16_PRIMARY_LITTLE 14503378Sgblack@eecs.umich.edu 0xDA: FailUnimpl::stshortf_16pl(); 14513378Sgblack@eecs.umich.edu //ASI_FL16_SECONDARY_LITTLE 14523378Sgblack@eecs.umich.edu 0xDB: FailUnimpl::stshortf_16sl(); 14533378Sgblack@eecs.umich.edu //Not an ASI which is legal with lddfa 14543378Sgblack@eecs.umich.edu default: Trap::stdfa_bad_asi( 14553378Sgblack@eecs.umich.edu {{fault = new DataAccessException;}}); 14563378Sgblack@eecs.umich.edu } 14573378Sgblack@eecs.umich.edu } 14584040Ssaidi@eecs.umich.edu 0x3C: CasAlt::casa({{ 14594040Ssaidi@eecs.umich.edu mem_data = htog(Rs2.uw); 14604040Ssaidi@eecs.umich.edu Mem.uw = Rd.uw;}}, 14614040Ssaidi@eecs.umich.edu {{ 14624040Ssaidi@eecs.umich.edu uint32_t tmp = mem_data; 14634040Ssaidi@eecs.umich.edu Rd.uw = tmp; 14644040Ssaidi@eecs.umich.edu }}, {{EXT_ASI}}, MEM_SWAP_COND); 14652526SN/A 0x3D: Nop::prefetcha({{ }}); 14664040Ssaidi@eecs.umich.edu 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); 14674040Ssaidi@eecs.umich.edu Mem.udw = Rd.udw; }}, 14684040Ssaidi@eecs.umich.edu {{ Rd.udw = mem_data; }}, {{EXT_ASI}}, MEM_SWAP_COND); 14692526SN/A } 14702469SN/A } 14712022SN/A} 1472