decoder.isa revision 5094
1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual decoder specification 34// 35 36decode OP default Unknown::unknown() 37{ 38 0x0: decode OP2 39 { 40 //Throw an illegal instruction acception 41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 42 format BranchN 43 { 44 //bpcc 45 0x1: decode COND2 46 { 47 //Branch Always 48 0x8: bpa(19, annul_code={{ 49 NPC = xc->readPC() + disp; 50 NNPC = NPC + 4; 51 }}); 52 //Branch Never 53 0x0: bpn(19, {{;}}, 54 annul_code={{ 55 NNPC = NPC + 8; 56 NPC = NPC + 4; 57 }}); 58 default: decode BPCC 59 { 60 0x0: bpcci(19, test={{passesCondition(Ccr<3:0>, COND2)}}); 61 0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}}); 62 } 63 } 64 //bicc 65 0x2: decode COND2 66 { 67 //Branch Always 68 0x8: ba(22, annul_code={{ 69 NPC = xc->readPC() + disp; 70 NNPC = NPC + 4; 71 }}); 72 //Branch Never 73 0x0: bn(22, {{;}}, 74 annul_code={{ 75 NNPC = NPC + 8; 76 NPC = NPC + 4; 77 }}); 78 default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}}); 79 } 80 } 81 0x3: decode RCOND2 82 { 83 format BranchSplit 84 { 85 0x1: bpreq(test={{Rs1.sdw == 0}}); 86 0x2: bprle(test={{Rs1.sdw <= 0}}); 87 0x3: bprl(test={{Rs1.sdw < 0}}); 88 0x5: bprne(test={{Rs1.sdw != 0}}); 89 0x6: bprg(test={{Rs1.sdw > 0}}); 90 0x7: bprge(test={{Rs1.sdw >= 0}}); 91 } 92 } 93 //SETHI (or NOP if rd == 0 and imm == 0) 94 0x4: SetHi::sethi({{Rd.udw = imm;}}); 95 //fbpfcc 96 0x5: decode COND2 { 97 format BranchN { 98 //Branch Always 99 0x8: fbpa(22, annul_code={{ 100 NPC = xc->readPC() + disp; 101 NNPC = NPC + 4; 102 }}); 103 //Branch Never 104 0x0: fbpn(22, {{;}}, 105 annul_code={{ 106 NNPC = NPC + 8; 107 NPC = NPC + 4; 108 }}); 109 default: decode BPCC { 110 0x0: fbpfcc0(19, test= 111 {{passesFpCondition(Fsr<11:10>, COND2)}}); 112 0x1: fbpfcc1(19, test= 113 {{passesFpCondition(Fsr<33:32>, COND2)}}); 114 0x2: fbpfcc2(19, test= 115 {{passesFpCondition(Fsr<35:34>, COND2)}}); 116 0x3: fbpfcc3(19, test= 117 {{passesFpCondition(Fsr<37:36>, COND2)}}); 118 } 119 } 120 } 121 //fbfcc 122 0x6: decode COND2 { 123 format BranchN { 124 //Branch Always 125 0x8: fba(22, annul_code={{ 126 NPC = xc->readPC() + disp; 127 NNPC = NPC + 4; 128 }}); 129 //Branch Never 130 0x0: fbn(22, {{;}}, 131 annul_code={{ 132 NNPC = NPC + 8; 133 NPC = NPC + 4; 134 }}); 135 default: fbfcc(22, test= 136 {{passesFpCondition(Fsr<11:10>, COND2)}}); 137 } 138 } 139 } 140 0x1: BranchN::call(30, {{ 141 if (Pstate<3:>) 142 R15 = (xc->readPC())<31:0>; 143 else 144 R15 = xc->readPC(); 145 NNPC = R15 + disp; 146 }}); 147 0x2: decode OP3 { 148 format IntOp { 149 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 150 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 151 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 152 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 153 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 154 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 155 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 156 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 157 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 158 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 159 0x0A: umul({{ 160 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 161 Y = Rd<63:32>; 162 }}); 163 0x0B: smul({{ 164 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 165 Y = Rd.sdw<63:32>; 166 }}); 167 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 168 0x0D: udivx({{ 169 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 170 else Rd.udw = Rs1.udw / Rs2_or_imm13; 171 }}); 172 0x0E: udiv({{ 173 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 174 else 175 { 176 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 177 if(Rd.udw >> 32 != 0) 178 Rd.udw = 0xFFFFFFFF; 179 } 180 }}); 181 0x0F: sdiv({{ 182 if(Rs2_or_imm13.sdw == 0) 183 fault = new DivisionByZero; 184 else 185 { 186 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 187 if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max()) 188 Rd.udw = 0x7FFFFFFF; 189 else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min()) 190 Rd.udw = ULL(0xFFFFFFFF80000000); 191 } 192 }}); 193 } 194 format IntOpCc { 195 0x10: addcc({{ 196 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 197 Rd = res = op1 + op2; 198 }}); 199 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 200 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 201 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 202 0x14: subcc({{ 203 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 204 Rd = res = op1 - op2; 205 }}, sub=True); 206 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 207 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 208 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 209 0x18: addccc({{ 210 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 211 Rd = res = op1 + op2 + Ccr<0:>; 212 }}); 213 0x1A: IntOpCcRes::umulcc({{ 214 uint64_t resTemp; 215 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 216 Y = resTemp<63:32>;}}); 217 0x1B: IntOpCcRes::smulcc({{ 218 int64_t resTemp; 219 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 220 Y = resTemp<63:32>;}}); 221 0x1C: subccc({{ 222 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 223 Rd = res = op1 - op2 - Ccr<0:>; 224 }}, sub=True); 225 0x1D: IntOpCcRes::udivxcc({{ 226 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 227 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 228 0x1E: IntOpCcRes::udivcc({{ 229 uint32_t resTemp, val2 = Rs2_or_imm13.udw; 230 int32_t overflow = 0; 231 if(val2 == 0) fault = new DivisionByZero; 232 else 233 { 234 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 235 overflow = (resTemp<63:32> != 0); 236 if(overflow) Rd = resTemp = 0xFFFFFFFF; 237 else Rd = resTemp; 238 } 239 }}, iv={{overflow}}); 240 0x1F: IntOpCcRes::sdivcc({{ 241 int64_t val2 = Rs2_or_imm13.sdw<31:0>; 242 bool overflow = false, underflow = false; 243 if(val2 == 0) fault = new DivisionByZero; 244 else 245 { 246 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 247 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); 248 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); 249 if(overflow) Rd = 0x7FFFFFFF; 250 else if(underflow) Rd = ULL(0xFFFFFFFF80000000); 251 } 252 }}, iv={{overflow || underflow}}); 253 0x20: taddcc({{ 254 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 255 Rd = res = Rs1 + op2; 256 }}, iv={{ 257 (op1 & mask(2)) || (op2 & mask(2)) || 258 findOverflow(32, res, op1, op2) 259 }}); 260 0x21: tsubcc({{ 261 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 262 Rd = res = Rs1 - op2; 263 }}, iv={{ 264 (op1 & mask(2)) || (op2 & mask(2)) || 265 findOverflow(32, res, op1, ~op2) 266 }}, sub=True); 267 0x22: taddcctv({{ 268 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 269 Rd = res = op1 + op2; 270 bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || 271 findOverflow(32, res, op1, op2); 272 if(overflow) fault = new TagOverflow; 273 }}, iv={{overflow}}); 274 0x23: tsubcctv({{ 275 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; 276 Rd = res = op1 - op2; 277 bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || 278 findOverflow(32, res, op1, ~op2); 279 if(overflow) fault = new TagOverflow; 280 }}, iv={{overflow}}, sub=True); 281 0x24: mulscc({{ 282 int32_t savedLSB = Rs1<0:>; 283 284 //Step 1 285 int64_t multiplicand = Rs2_or_imm13; 286 //Step 2 287 int32_t partialP = Rs1<31:1> | 288 ((Ccr<3:3> ^ Ccr<1:1>) << 31); 289 //Step 3 290 int32_t added = Y<0:> ? multiplicand : 0; 291 int64_t res, op1 = partialP, op2 = added; 292 Rd = res = partialP + added; 293 //Steps 4 & 5 294 Y = Y<31:1> | (savedLSB << 31); 295 }}); 296 } 297 format IntOp 298 { 299 0x25: decode X { 300 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 301 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 302 } 303 0x26: decode X { 304 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 305 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 306 } 307 0x27: decode X { 308 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 309 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 310 } 311 0x28: decode RS1 { 312 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); 313 //1 should cause an illegal instruction exception 314 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 315 0x03: NoPriv::rdasi({{Rd = Asi;}}); 316 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 317 0x05: NoPriv::rdpc({{ 318 if(Pstate<3:>) 319 Rd = (xc->readPC())<31:0>; 320 else 321 Rd = xc->readPC();}}); 322 0x06: NoPriv::rdfprs({{ 323 //Wait for all fpops to finish. 324 Rd = Fprs; 325 }}); 326 //7-14 should cause an illegal instruction exception 327 0x0F: decode I { 328 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp); 329 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp); 330 } 331 0x10: Priv::rdpcr({{Rd = Pcr;}}); 332 0x11: Priv::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); 333 //0x12 should cause an illegal instruction exception 334 0x13: NoPriv::rdgsr({{ 335 fault = checkFpEnableFault(xc); 336 if (fault) 337 return fault; 338 Rd = Gsr; 339 }}); 340 //0x14-0x15 should cause an illegal instruction exception 341 0x16: Priv::rdsoftint({{Rd = Softint;}}); 342 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 343 0x18: Priv::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 344 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 345 0x1A: Priv::rdstrand_sts_reg({{ 346 if(Pstate<2:> && !Hpstate<2:>) 347 Rd = StrandStsReg<0:>; 348 else 349 Rd = StrandStsReg; 350 }}); 351 //0x1A is supposed to be reserved, but it reads the strand 352 //status register. 353 //0x1B-0x1F should cause an illegal instruction exception 354 } 355 0x29: decode RS1 { 356 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); 357 0x01: HPriv::rdhprhtstate({{Rd = Htstate;}}, checkTl=true); 358 //0x02 should cause an illegal instruction exception 359 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 360 //0x04 should cause an illegal instruction exception 361 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 362 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 363 //0x07-0x1E should cause an illegal instruction exception 364 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); 365 } 366 0x2A: decode RS1 { 367 0x00: Priv::rdprtpc({{Rd = Tpc;}}, checkTl=true); 368 0x01: Priv::rdprtnpc({{Rd = Tnpc;}}, checkTl=true); 369 0x02: Priv::rdprtstate({{Rd = Tstate;}}, checkTl=true); 370 0x03: Priv::rdprtt({{Rd = Tt;}}, checkTl=true); 371 0x04: Priv::rdprtick({{Rd = Tick;}}); 372 0x05: Priv::rdprtba({{Rd = Tba;}}); 373 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 374 0x07: Priv::rdprtl({{Rd = Tl;}}); 375 0x08: Priv::rdprpil({{Rd = Pil;}}); 376 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 377 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 378 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 379 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); 380 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); 381 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); 382 //0x0F should cause an illegal instruction exception 383 0x10: Priv::rdprgl({{Rd = Gl;}}); 384 //0x11-0x1F should cause an illegal instruction exception 385 } 386 0x2B: BasicOperate::flushw({{ 387 if(NWindows - 2 - Cansave != 0) 388 { 389 if(Otherwin) 390 fault = new SpillNOther(4*Wstate<5:3>); 391 else 392 fault = new SpillNNormal(4*Wstate<2:0>); 393 } 394 }}); 395 0x2C: decode MOVCC3 396 { 397 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 398 0x1: decode CC 399 { 400 0x0: movcci({{ 401 if(passesCondition(Ccr<3:0>, COND4)) 402 Rd = Rs2_or_imm11; 403 else 404 Rd = Rd; 405 }}); 406 0x2: movccx({{ 407 if(passesCondition(Ccr<7:4>, COND4)) 408 Rd = Rs2_or_imm11; 409 else 410 Rd = Rd; 411 }}); 412 } 413 } 414 0x2D: sdivx({{ 415 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 416 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 417 }}); 418 0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 419 0x2F: decode RCOND3 420 { 421 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 422 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 423 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 424 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 425 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 426 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 427 } 428 0x30: decode RD { 429 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); 430 //0x01 should cause an illegal instruction exception 431 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 432 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 433 //0x04-0x05 should cause an illegal instruction exception 434 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 435 //0x07-0x0E should cause an illegal instruction exception 436 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 437 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); 438 0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); 439 //0x12 should cause an illegal instruction exception 440 0x13: NoPriv::wrgsr({{ 441 if(Fprs<2:> == 0 || Pstate<4:> == 0) 442 return new FpDisabled; 443 Gsr = Rs1 ^ Rs2_or_imm13; 444 }}); 445 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 446 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 447 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 448 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 449 0x18: NoPriv::wrstick({{ 450 if(!Hpstate<2:>) 451 return new IllegalInstruction; 452 Stick = Rs1 ^ Rs2_or_imm13; 453 }}); 454 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 455 0x1A: Priv::wrstrand_sts_reg({{ 456 StrandStsReg = Rs1 ^ Rs2_or_imm13; 457 }}); 458 //0x1A is supposed to be reserved, but it writes the strand 459 //status register. 460 //0x1B-0x1F should cause an illegal instruction exception 461 } 462 0x31: decode FCN { 463 0x0: Priv::saved({{ 464 assert(Cansave < NWindows - 2); 465 assert(Otherwin || Canrestore); 466 Cansave = Cansave + 1; 467 if(Otherwin == 0) 468 Canrestore = Canrestore - 1; 469 else 470 Otherwin = Otherwin - 1; 471 }}); 472 0x1: Priv::restored({{ 473 assert(Cansave || Otherwin); 474 assert(Canrestore < NWindows - 2); 475 Canrestore = Canrestore + 1; 476 if(Otherwin == 0) 477 Cansave = Cansave - 1; 478 else 479 Otherwin = Otherwin - 1; 480 481 if(Cleanwin < NWindows - 1) 482 Cleanwin = Cleanwin + 1; 483 }}); 484 } 485 0x32: decode RD { 486 0x00: Priv::wrprtpc( 487 {{Tpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 488 0x01: Priv::wrprtnpc( 489 {{Tnpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 490 0x02: Priv::wrprtstate( 491 {{Tstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 492 0x03: Priv::wrprtt( 493 {{Tt = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 494 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 495 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 496 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 497 0x07: Priv::wrprtl({{ 498 if(Pstate<2:> && !Hpstate<2:>) 499 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 500 else 501 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 502 }}); 503 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 504 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 505 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 506 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 507 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 508 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 509 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 510 //0x0F should cause an illegal instruction exception 511 0x10: Priv::wrprgl({{ 512 if(Pstate<2:> && !Hpstate<2:>) 513 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL); 514 else 515 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL); 516 }}); 517 //0x11-0x1F should cause an illegal instruction exception 518 } 519 0x33: decode RD { 520 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); 521 0x01: HPriv::wrhprhtstate( 522 {{Htstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 523 //0x02 should cause an illegal instruction exception 524 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 525 //0x04 should cause an illegal instruction exception 526 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 527 //0x06-0x01D should cause an illegal instruction exception 528 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 529 } 530 0x34: decode OPF{ 531 format FpBasic{ 532 0x01: fmovs({{ 533 Frds.uw = Frs2s.uw; 534 //fsr.ftt = fsr.cexc = 0 535 Fsr &= ~(7 << 14); 536 Fsr &= ~(0x1F); 537 }}); 538 0x02: fmovd({{ 539 Frd.udw = Frs2.udw; 540 //fsr.ftt = fsr.cexc = 0 541 Fsr &= ~(7 << 14); 542 Fsr &= ~(0x1F); 543 }}); 544 0x03: FpUnimpl::fmovq(); 545 0x05: fnegs({{ 546 Frds.uw = Frs2s.uw ^ (1UL << 31); 547 //fsr.ftt = fsr.cexc = 0 548 Fsr &= ~(7 << 14); 549 Fsr &= ~(0x1F); 550 }}); 551 0x06: fnegd({{ 552 Frd.udw = Frs2.udw ^ (1ULL << 63); 553 //fsr.ftt = fsr.cexc = 0 554 Fsr &= ~(7 << 14); 555 Fsr &= ~(0x1F); 556 }}); 557 0x07: FpUnimpl::fnegq(); 558 0x09: fabss({{ 559 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw; 560 //fsr.ftt = fsr.cexc = 0 561 Fsr &= ~(7 << 14); 562 Fsr &= ~(0x1F); 563 }}); 564 0x0A: fabsd({{ 565 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw; 566 //fsr.ftt = fsr.cexc = 0 567 Fsr &= ~(7 << 14); 568 Fsr &= ~(0x1F); 569 }}); 570 0x0B: FpUnimpl::fabsq(); 571 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 572 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 573 0x2B: FpUnimpl::fsqrtq(); 574 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 575 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 576 0x43: FpUnimpl::faddq(); 577 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 578 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }}); 579 0x47: FpUnimpl::fsubq(); 580 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 581 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 582 0x4B: FpUnimpl::fmulq(); 583 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 584 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 585 0x4F: FpUnimpl::fdivq(); 586 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 587 0x6E: FpUnimpl::fdmulq(); 588 0x81: fstox({{ 589 Frd.sdw = static_cast<int64_t>(Frs2s.sf); 590 }}); 591 0x82: fdtox({{ 592 Frd.sdw = static_cast<int64_t>(Frs2.df); 593 }}); 594 0x83: FpUnimpl::fqtox(); 595 0x84: fxtos({{ 596 Frds.sf = static_cast<float>(Frs2.sdw); 597 }}); 598 0x88: fxtod({{ 599 Frd.df = static_cast<double>(Frs2.sdw); 600 }}); 601 0x8C: FpUnimpl::fxtoq(); 602 0xC4: fitos({{ 603 Frds.sf = static_cast<float>(Frs2s.sw); 604 }}); 605 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 606 0xC7: FpUnimpl::fqtos(); 607 0xC8: fitod({{ 608 Frd.df = static_cast<double>(Frs2s.sw); 609 }}); 610 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 611 0xCB: FpUnimpl::fqtod(); 612 0xCC: FpUnimpl::fitoq(); 613 0xCD: FpUnimpl::fstoq(); 614 0xCE: FpUnimpl::fdtoq(); 615 0xD1: fstoi({{ 616 Frds.sw = static_cast<int32_t>(Frs2s.sf); 617 float t = Frds.sw; 618 if (t != Frs2s.sf) 619 Fsr = insertBits(Fsr, 4,0, 0x01); 620 }}); 621 0xD2: fdtoi({{ 622 Frds.sw = static_cast<int32_t>(Frs2.df); 623 double t = Frds.sw; 624 if (t != Frs2.df) 625 Fsr = insertBits(Fsr, 4,0, 0x01); 626 }}); 627 0xD3: FpUnimpl::fqtoi(); 628 default: FailUnimpl::fpop1(); 629 } 630 } 631 0x35: decode OPF{ 632 format FpBasic{ 633 0x01: fmovs_fcc0({{ 634 if(passesFpCondition(Fsr<11:10>, COND4)) 635 Frds = Frs2s; 636 else 637 Frds = Frds; 638 }}); 639 0x02: fmovd_fcc0({{ 640 if(passesFpCondition(Fsr<11:10>, COND4)) 641 Frd = Frs2; 642 else 643 Frd = Frd; 644 }}); 645 0x03: FpUnimpl::fmovq_fcc0(); 646 0x25: fmovrsz({{ 647 if(Rs1 == 0) 648 Frds = Frs2s; 649 else 650 Frds = Frds; 651 }}); 652 0x26: fmovrdz({{ 653 if(Rs1 == 0) 654 Frd = Frs2; 655 else 656 Frd = Frd; 657 }}); 658 0x27: FpUnimpl::fmovrqz(); 659 0x41: fmovs_fcc1({{ 660 if(passesFpCondition(Fsr<33:32>, COND4)) 661 Frds = Frs2s; 662 else 663 Frds = Frds; 664 }}); 665 0x42: fmovd_fcc1({{ 666 if(passesFpCondition(Fsr<33:32>, COND4)) 667 Frd = Frs2; 668 else 669 Frd = Frd; 670 }}); 671 0x43: FpUnimpl::fmovq_fcc1(); 672 0x45: fmovrslez({{ 673 if(Rs1 <= 0) 674 Frds = Frs2s; 675 else 676 Frds = Frds; 677 }}); 678 0x46: fmovrdlez({{ 679 if(Rs1 <= 0) 680 Frd = Frs2; 681 else 682 Frd = Frd; 683 }}); 684 0x47: FpUnimpl::fmovrqlez(); 685 0x51: fcmps({{ 686 uint8_t fcc; 687 if(isnan(Frs1s) || isnan(Frs2s)) 688 fcc = 3; 689 else if(Frs1s < Frs2s) 690 fcc = 1; 691 else if(Frs1s > Frs2s) 692 fcc = 2; 693 else 694 fcc = 0; 695 uint8_t firstbit = 10; 696 if(FCMPCC) 697 firstbit = FCMPCC * 2 + 30; 698 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 699 }}); 700 0x52: fcmpd({{ 701 uint8_t fcc; 702 if(isnan(Frs1) || isnan(Frs2)) 703 fcc = 3; 704 else if(Frs1 < Frs2) 705 fcc = 1; 706 else if(Frs1 > Frs2) 707 fcc = 2; 708 else 709 fcc = 0; 710 uint8_t firstbit = 10; 711 if(FCMPCC) 712 firstbit = FCMPCC * 2 + 30; 713 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 714 }}); 715 0x53: FpUnimpl::fcmpq(); 716 0x55: fcmpes({{ 717 uint8_t fcc = 0; 718 if(isnan(Frs1s) || isnan(Frs2s)) 719 fault = new FpExceptionIEEE754; 720 if(Frs1s < Frs2s) 721 fcc = 1; 722 else if(Frs1s > Frs2s) 723 fcc = 2; 724 uint8_t firstbit = 10; 725 if(FCMPCC) 726 firstbit = FCMPCC * 2 + 30; 727 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 728 }}); 729 0x56: fcmped({{ 730 uint8_t fcc = 0; 731 if(isnan(Frs1) || isnan(Frs2)) 732 fault = new FpExceptionIEEE754; 733 if(Frs1 < Frs2) 734 fcc = 1; 735 else if(Frs1 > Frs2) 736 fcc = 2; 737 uint8_t firstbit = 10; 738 if(FCMPCC) 739 firstbit = FCMPCC * 2 + 30; 740 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 741 }}); 742 0x57: FpUnimpl::fcmpeq(); 743 0x65: fmovrslz({{ 744 if(Rs1 < 0) 745 Frds = Frs2s; 746 else 747 Frds = Frds; 748 }}); 749 0x66: fmovrdlz({{ 750 if(Rs1 < 0) 751 Frd = Frs2; 752 else 753 Frd = Frd; 754 }}); 755 0x67: FpUnimpl::fmovrqlz(); 756 0x81: fmovs_fcc2({{ 757 if(passesFpCondition(Fsr<35:34>, COND4)) 758 Frds = Frs2s; 759 else 760 Frds = Frds; 761 }}); 762 0x82: fmovd_fcc2({{ 763 if(passesFpCondition(Fsr<35:34>, COND4)) 764 Frd = Frs2; 765 else 766 Frd = Frd; 767 }}); 768 0x83: FpUnimpl::fmovq_fcc2(); 769 0xA5: fmovrsnz({{ 770 if(Rs1 != 0) 771 Frds = Frs2s; 772 else 773 Frds = Frds; 774 }}); 775 0xA6: fmovrdnz({{ 776 if(Rs1 != 0) 777 Frd = Frs2; 778 else 779 Frd = Frd; 780 }}); 781 0xA7: FpUnimpl::fmovrqnz(); 782 0xC1: fmovs_fcc3({{ 783 if(passesFpCondition(Fsr<37:36>, COND4)) 784 Frds = Frs2s; 785 else 786 Frds = Frds; 787 }}); 788 0xC2: fmovd_fcc3({{ 789 if(passesFpCondition(Fsr<37:36>, COND4)) 790 Frd = Frs2; 791 else 792 Frd = Frd; 793 }}); 794 0xC3: FpUnimpl::fmovq_fcc3(); 795 0xC5: fmovrsgz({{ 796 if(Rs1 > 0) 797 Frds = Frs2s; 798 else 799 Frds = Frds; 800 }}); 801 0xC6: fmovrdgz({{ 802 if(Rs1 > 0) 803 Frd = Frs2; 804 else 805 Frd = Frd; 806 }}); 807 0xC7: FpUnimpl::fmovrqgz(); 808 0xE5: fmovrsgez({{ 809 if(Rs1 >= 0) 810 Frds = Frs2s; 811 else 812 Frds = Frds; 813 }}); 814 0xE6: fmovrdgez({{ 815 if(Rs1 >= 0) 816 Frd = Frs2; 817 else 818 Frd = Frd; 819 }}); 820 0xE7: FpUnimpl::fmovrqgez(); 821 0x101: fmovs_icc({{ 822 if(passesCondition(Ccr<3:0>, COND4)) 823 Frds = Frs2s; 824 else 825 Frds = Frds; 826 }}); 827 0x102: fmovd_icc({{ 828 if(passesCondition(Ccr<3:0>, COND4)) 829 Frd = Frs2; 830 else 831 Frd = Frd; 832 }}); 833 0x103: FpUnimpl::fmovq_icc(); 834 0x181: fmovs_xcc({{ 835 if(passesCondition(Ccr<7:4>, COND4)) 836 Frds = Frs2s; 837 else 838 Frds = Frds; 839 }}); 840 0x182: fmovd_xcc({{ 841 if(passesCondition(Ccr<7:4>, COND4)) 842 Frd = Frs2; 843 else 844 Frd = Frd; 845 }}); 846 0x183: FpUnimpl::fmovq_xcc(); 847 default: FailUnimpl::fpop2(); 848 } 849 } 850 //This used to be just impdep1, but now it's a whole bunch 851 //of instructions 852 0x36: decode OPF{ 853 0x00: FailUnimpl::edge8(); 854 0x01: FailUnimpl::edge8n(); 855 0x02: FailUnimpl::edge8l(); 856 0x03: FailUnimpl::edge8ln(); 857 0x04: FailUnimpl::edge16(); 858 0x05: FailUnimpl::edge16n(); 859 0x06: FailUnimpl::edge16l(); 860 0x07: FailUnimpl::edge16ln(); 861 0x08: FailUnimpl::edge32(); 862 0x09: FailUnimpl::edge32n(); 863 0x0A: FailUnimpl::edge32l(); 864 0x0B: FailUnimpl::edge32ln(); 865 0x10: FailUnimpl::array8(); 866 0x12: FailUnimpl::array16(); 867 0x14: FailUnimpl::array32(); 868 0x18: BasicOperate::alignaddr({{ 869 uint64_t sum = Rs1 + Rs2; 870 Rd = sum & ~7; 871 Gsr = (Gsr & ~7) | (sum & 7); 872 }}); 873 0x19: FailUnimpl::bmask(); 874 0x1A: BasicOperate::alignaddresslittle({{ 875 uint64_t sum = Rs1 + Rs2; 876 Rd = sum & ~7; 877 Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 878 }}); 879 0x20: FailUnimpl::fcmple16(); 880 0x22: FailUnimpl::fcmpne16(); 881 0x24: FailUnimpl::fcmple32(); 882 0x26: FailUnimpl::fcmpne32(); 883 0x28: FailUnimpl::fcmpgt16(); 884 0x2A: FailUnimpl::fcmpeq16(); 885 0x2C: FailUnimpl::fcmpgt32(); 886 0x2E: FailUnimpl::fcmpeq32(); 887 0x31: FailUnimpl::fmul8x16(); 888 0x33: FailUnimpl::fmul8x16au(); 889 0x35: FailUnimpl::fmul8x16al(); 890 0x36: FailUnimpl::fmul8sux16(); 891 0x37: FailUnimpl::fmul8ulx16(); 892 0x38: FailUnimpl::fmuld8sux16(); 893 0x39: FailUnimpl::fmuld8ulx16(); 894 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 895 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 896 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 897 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 898 0x48: BasicOperate::faligndata({{ 899 uint64_t msbX = Frs1.udw; 900 uint64_t lsbX = Frs2.udw; 901 //Some special cases need to be split out, first 902 //because they're the most likely to be used, and 903 //second because otherwise, we end up shifting by 904 //greater than the width of the type being shifted, 905 //namely 64, which produces undefined results according 906 //to the C standard. 907 switch(Gsr<2:0>) 908 { 909 case 0: 910 Frd.udw = msbX; 911 break; 912 case 8: 913 Frd.udw = lsbX; 914 break; 915 default: 916 uint64_t msbShift = Gsr<2:0> * 8; 917 uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 918 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 919 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 920 Frd.udw = ((msbX & msbMask) << msbShift) | 921 ((lsbX & lsbMask) >> lsbShift); 922 } 923 }}); 924 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 925 0x4C: FailUnimpl::bshuffle(); 926 0x4D: FailUnimpl::fexpand(); 927 0x50: FailUnimpl::fpadd16(); 928 0x51: FailUnimpl::fpadd16s(); 929 0x52: FailUnimpl::fpadd32(); 930 0x53: FailUnimpl::fpadd32s(); 931 0x54: FailUnimpl::fpsub16(); 932 0x55: FailUnimpl::fpsub16s(); 933 0x56: FailUnimpl::fpsub32(); 934 0x57: FailUnimpl::fpsub32s(); 935 0x60: FpBasic::fzero({{Frd.df = 0;}}); 936 0x61: FpBasic::fzeros({{Frds.sf = 0;}}); 937 0x62: FailUnimpl::fnor(); 938 0x63: FailUnimpl::fnors(); 939 0x64: FailUnimpl::fandnot2(); 940 0x65: FailUnimpl::fandnot2s(); 941 0x66: FpBasic::fnot2({{ 942 Frd.df = (double)(~((uint64_t)Frs2.df)); 943 }}); 944 0x67: FpBasic::fnot2s({{ 945 Frds.sf = (float)(~((uint32_t)Frs2s.sf)); 946 }}); 947 0x68: FailUnimpl::fandnot1(); 948 0x69: FailUnimpl::fandnot1s(); 949 0x6A: FpBasic::fnot1({{ 950 Frd.df = (double)(~((uint64_t)Frs1.df)); 951 }}); 952 0x6B: FpBasic::fnot1s({{ 953 Frds.sf = (float)(~((uint32_t)Frs1s.sf)); 954 }}); 955 0x6C: FailUnimpl::fxor(); 956 0x6D: FailUnimpl::fxors(); 957 0x6E: FailUnimpl::fnand(); 958 0x6F: FailUnimpl::fnands(); 959 0x70: FailUnimpl::fand(); 960 0x71: FailUnimpl::fands(); 961 0x72: FailUnimpl::fxnor(); 962 0x73: FailUnimpl::fxnors(); 963 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}}); 964 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}}); 965 0x76: FailUnimpl::fornot2(); 966 0x77: FailUnimpl::fornot2s(); 967 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}}); 968 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}}); 969 0x7A: FailUnimpl::fornot1(); 970 0x7B: FailUnimpl::fornot1s(); 971 0x7C: FailUnimpl::for(); 972 0x7D: FailUnimpl::fors(); 973 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}}); 974 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}}); 975 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 976 0x81: FailUnimpl::siam(); 977 } 978 // M5 special opcodes use the reserved IMPDEP2A opcode space 979 0x37: decode M5FUNC { 980#if FULL_SYSTEM 981 format BasicOperate { 982 // we have 7 bits of space here to play with... 983 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); 984 }}, No_OpClass, IsNonSpeculative); 985 0x50: m5readfile({{ 986 O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2); 987 }}, IsNonSpeculative); 988 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase()); 989 }}, IsNonSpeculative); 990 0x54: m5panic({{ 991 panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 992 }}, No_OpClass, IsNonSpeculative); 993 } 994#endif 995 default: Trap::impdep2({{fault = new IllegalInstruction;}}); 996 } 997 0x38: Branch::jmpl({{ 998 Addr target = Rs1 + Rs2_or_imm13; 999 if(target & 0x3) 1000 fault = new MemAddressNotAligned; 1001 else 1002 { 1003 if (Pstate<3:>) 1004 Rd = (xc->readPC())<31:0>; 1005 else 1006 Rd = xc->readPC(); 1007 NNPC = target; 1008 } 1009 }}); 1010 0x39: Branch::return({{ 1011 Addr target = Rs1 + Rs2_or_imm13; 1012 if(fault == NoFault) 1013 { 1014 //Check for fills which are higher priority than alignment 1015 //faults. 1016 if(Canrestore == 0) 1017 { 1018 if(Otherwin) 1019 fault = new FillNOther(4*Wstate<5:3>); 1020 else 1021 fault = new FillNNormal(4*Wstate<2:0>); 1022 } 1023 //Check for alignment faults 1024 else if(target & 0x3) 1025 fault = new MemAddressNotAligned; 1026 else 1027 { 1028 NNPC = target; 1029 Cwp = (Cwp - 1 + NWindows) % NWindows; 1030 Cansave = Cansave + 1; 1031 Canrestore = Canrestore - 1; 1032 } 1033 } 1034 }}); 1035 0x3A: decode CC 1036 { 1037 0x0: Trap::tcci({{ 1038 if(passesCondition(Ccr<3:0>, COND2)) 1039 { 1040 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 1041 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 1042 fault = new TrapInstruction(lTrapNum); 1043 } 1044 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 1045 0x2: Trap::tccx({{ 1046 if(passesCondition(Ccr<7:4>, COND2)) 1047 { 1048 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 1049 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 1050 fault = new TrapInstruction(lTrapNum); 1051 } 1052 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 1053 } 1054 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, 1055 MemWriteOp); 1056 0x3C: save({{ 1057 if(Cansave == 0) 1058 { 1059 if(Otherwin) 1060 fault = new SpillNOther(4*Wstate<5:3>); 1061 else 1062 fault = new SpillNNormal(4*Wstate<2:0>); 1063 } 1064 else if(Cleanwin - Canrestore == 0) 1065 { 1066 fault = new CleanWindow; 1067 } 1068 else 1069 { 1070 Cwp = (Cwp + 1) % NWindows; 1071 Rd_next = Rs1 + Rs2_or_imm13; 1072 Cansave = Cansave - 1; 1073 Canrestore = Canrestore + 1; 1074 } 1075 }}); 1076 0x3D: restore({{ 1077 if(Canrestore == 0) 1078 { 1079 if(Otherwin) 1080 fault = new FillNOther(4*Wstate<5:3>); 1081 else 1082 fault = new FillNNormal(4*Wstate<2:0>); 1083 } 1084 else 1085 { 1086 Cwp = (Cwp - 1 + NWindows) % NWindows; 1087 Rd_prev = Rs1 + Rs2_or_imm13; 1088 Cansave = Cansave + 1; 1089 Canrestore = Canrestore - 1; 1090 } 1091 }}); 1092 0x3E: decode FCN { 1093 0x0: Priv::done({{ 1094 Cwp = Tstate<4:0>; 1095 Pstate = Tstate<20:8>; 1096 Asi = Tstate<31:24>; 1097 Ccr = Tstate<39:32>; 1098 Gl = Tstate<42:40>; 1099 Hpstate = Htstate; 1100 NPC = Tnpc; 1101 NNPC = Tnpc + 4; 1102 Tl = Tl - 1; 1103 }}, checkTl=true); 1104 0x1: Priv::retry({{ 1105 Cwp = Tstate<4:0>; 1106 Pstate = Tstate<20:8>; 1107 Asi = Tstate<31:24>; 1108 Ccr = Tstate<39:32>; 1109 Gl = Tstate<42:40>; 1110 Hpstate = Htstate; 1111 NPC = Tpc; 1112 NNPC = Tnpc; 1113 Tl = Tl - 1; 1114 }}, checkTl=true); 1115 } 1116 } 1117 } 1118 0x3: decode OP3 { 1119 format Load { 1120 0x00: lduw({{Rd = Mem.uw;}}); 1121 0x01: ldub({{Rd = Mem.ub;}}); 1122 0x02: lduh({{Rd = Mem.uhw;}}); 1123 0x03: ldtw({{ 1124 RdLow = (Mem.tuw).a; 1125 RdHigh = (Mem.tuw).b; 1126 }}); 1127 } 1128 format Store { 1129 0x04: stw({{Mem.uw = Rd.sw;}}); 1130 0x05: stb({{Mem.ub = Rd.sb;}}); 1131 0x06: sth({{Mem.uhw = Rd.shw;}}); 1132 0x07: sttw({{ 1133 //This temporary needs to be here so that the parser 1134 //will correctly identify this instruction as a store. 1135 //It's probably either the parenthesis or referencing 1136 //the member variable that throws confuses it. 1137 Twin32_t temp; 1138 temp.a = RdLow<31:0>; 1139 temp.b = RdHigh<31:0>; 1140 Mem.tuw = temp; 1141 }}); 1142 } 1143 format Load { 1144 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 1145 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 1146 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 1147 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 1148 } 1149 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}}, 1150 {{ 1151 uint8_t tmp = mem_data; 1152 Rd.ub = tmp; 1153 }}, MEM_SWAP); 1154 0x0E: Store::stx({{Mem.udw = Rd}}); 1155 0x0F: Swap::swap({{Mem.uw = Rd.uw}}, 1156 {{ 1157 uint32_t tmp = mem_data; 1158 Rd.uw = tmp; 1159 }}, MEM_SWAP); 1160 format LoadAlt { 1161 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 1162 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); 1163 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); 1164 0x13: decode EXT_ASI { 1165 //ASI_LDTD_AIUP 1166 0x22: TwinLoad::ldtx_aiup( 1167 {{RdLow.udw = (Mem.tudw).a; 1168 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1169 //ASI_LDTD_AIUS 1170 0x23: TwinLoad::ldtx_aius( 1171 {{RdLow.udw = (Mem.tudw).a; 1172 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1173 //ASI_QUAD_LDD 1174 0x24: TwinLoad::ldtx_quad_ldd( 1175 {{RdLow.udw = (Mem.tudw).a; 1176 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1177 //ASI_LDTX_REAL 1178 0x26: TwinLoad::ldtx_real( 1179 {{RdLow.udw = (Mem.tudw).a; 1180 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1181 //ASI_LDTX_N 1182 0x27: TwinLoad::ldtx_n( 1183 {{RdLow.udw = (Mem.tudw).a; 1184 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1185 //ASI_LDTX_AIUP_L 1186 0x2A: TwinLoad::ldtx_aiup_l( 1187 {{RdLow.udw = (Mem.tudw).a; 1188 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1189 //ASI_LDTX_AIUS_L 1190 0x2B: TwinLoad::ldtx_aius_l( 1191 {{RdLow.udw = (Mem.tudw).a; 1192 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1193 //ASI_LDTX_L 1194 0x2C: TwinLoad::ldtx_l( 1195 {{RdLow.udw = (Mem.tudw).a; 1196 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1197 //ASI_LDTX_REAL_L 1198 0x2E: TwinLoad::ldtx_real_l( 1199 {{RdLow.udw = (Mem.tudw).a; 1200 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1201 //ASI_LDTX_N_L 1202 0x2F: TwinLoad::ldtx_n_l( 1203 {{RdLow.udw = (Mem.tudw).a; 1204 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1205 //ASI_LDTX_P 1206 0xE2: TwinLoad::ldtx_p( 1207 {{RdLow.udw = (Mem.tudw).a; 1208 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1209 //ASI_LDTX_S 1210 0xE3: TwinLoad::ldtx_s( 1211 {{RdLow.udw = (Mem.tudw).a; 1212 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1213 //ASI_LDTX_PL 1214 0xEA: TwinLoad::ldtx_pl( 1215 {{RdLow.udw = (Mem.tudw).a; 1216 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1217 //ASI_LDTX_SL 1218 0xEB: TwinLoad::ldtx_sl( 1219 {{RdLow.udw = (Mem.tudw).a; 1220 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1221 default: ldtwa({{ 1222 RdLow = (Mem.tuw).a; 1223 RdHigh = (Mem.tuw).b; 1224 }}, {{EXT_ASI}}); 1225 } 1226 } 1227 format StoreAlt { 1228 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}}); 1229 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}}); 1230 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}}); 1231 0x17: sttwa({{ 1232 //This temporary needs to be here so that the parser 1233 //will correctly identify this instruction as a store. 1234 //It's probably either the parenthesis or referencing 1235 //the member variable that throws confuses it. 1236 Twin32_t temp; 1237 temp.a = RdLow<31:0>; 1238 temp.b = RdHigh<31:0>; 1239 Mem.tuw = temp; 1240 }}, {{EXT_ASI}}); 1241 } 1242 format LoadAlt { 1243 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}}); 1244 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}}); 1245 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}}); 1246 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}}); 1247 } 1248 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, 1249 {{ 1250 uint8_t tmp = mem_data; 1251 Rd.ub = tmp; 1252 }}, {{EXT_ASI}}, MEM_SWAP); 1253 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}}); 1254 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}}, 1255 {{ 1256 uint32_t tmp = mem_data; 1257 Rd.uw = tmp; 1258 }}, {{EXT_ASI}}, MEM_SWAP); 1259 1260 format Trap { 1261 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); 1262 0x21: decode RD { 1263 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc); 1264 if (fault) 1265 return fault; 1266 Fsr = Mem.uw | Fsr<63:32>;}}); 1267 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc); 1268 if (fault) 1269 return fault; 1270 Fsr = Mem.udw;}}); 1271 default: FailUnimpl::ldfsrOther(); 1272 } 1273 0x22: ldqf({{fault = new FpDisabled;}}); 1274 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 1275 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 1276 0x25: decode RD { 1277 0x0: Store::stfsr({{fault = checkFpEnableFault(xc); 1278 if (fault) 1279 return fault; 1280 Mem.uw = Fsr<31:0>; 1281 Fsr = insertBits(Fsr,16,14,0);}}); 1282 0x1: Store::stxfsr({{fault = checkFpEnableFault(xc); 1283 if (fault) 1284 return fault; 1285 Mem.udw = Fsr; 1286 Fsr = insertBits(Fsr,16,14,0);}}); 1287 default: FailUnimpl::stfsrOther(); 1288 } 1289 0x26: stqf({{fault = new FpDisabled;}}); 1290 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 1291 0x2D: Nop::prefetch({{ }}); 1292 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}}); 1293 0x32: ldqfa({{fault = new FpDisabled;}}); 1294 format LoadAlt { 1295 0x33: decode EXT_ASI { 1296 //ASI_NUCLEUS 1297 0x04: FailUnimpl::lddfa_n(); 1298 //ASI_NUCLEUS_LITTLE 1299 0x0C: FailUnimpl::lddfa_nl(); 1300 //ASI_AS_IF_USER_PRIMARY 1301 0x10: FailUnimpl::lddfa_aiup(); 1302 //ASI_AS_IF_USER_PRIMARY_LITTLE 1303 0x18: FailUnimpl::lddfa_aiupl(); 1304 //ASI_AS_IF_USER_SECONDARY 1305 0x11: FailUnimpl::lddfa_aius(); 1306 //ASI_AS_IF_USER_SECONDARY_LITTLE 1307 0x19: FailUnimpl::lddfa_aiusl(); 1308 //ASI_REAL 1309 0x14: FailUnimpl::lddfa_real(); 1310 //ASI_REAL_LITTLE 1311 0x1C: FailUnimpl::lddfa_real_l(); 1312 //ASI_REAL_IO 1313 0x15: FailUnimpl::lddfa_real_io(); 1314 //ASI_REAL_IO_LITTLE 1315 0x1D: FailUnimpl::lddfa_real_io_l(); 1316 //ASI_PRIMARY 1317 0x80: FailUnimpl::lddfa_p(); 1318 //ASI_PRIMARY_LITTLE 1319 0x88: FailUnimpl::lddfa_pl(); 1320 //ASI_SECONDARY 1321 0x81: FailUnimpl::lddfa_s(); 1322 //ASI_SECONDARY_LITTLE 1323 0x89: FailUnimpl::lddfa_sl(); 1324 //ASI_PRIMARY_NO_FAULT 1325 0x82: FailUnimpl::lddfa_pnf(); 1326 //ASI_PRIMARY_NO_FAULT_LITTLE 1327 0x8A: FailUnimpl::lddfa_pnfl(); 1328 //ASI_SECONDARY_NO_FAULT 1329 0x83: FailUnimpl::lddfa_snf(); 1330 //ASI_SECONDARY_NO_FAULT_LITTLE 1331 0x8B: FailUnimpl::lddfa_snfl(); 1332 1333 format BlockLoad { 1334 // LDBLOCKF 1335 //ASI_BLOCK_AS_IF_USER_PRIMARY 1336 0x16: FailUnimpl::ldblockf_aiup(); 1337 //ASI_BLOCK_AS_IF_USER_SECONDARY 1338 0x17: FailUnimpl::ldblockf_aius(); 1339 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1340 0x1E: FailUnimpl::ldblockf_aiupl(); 1341 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1342 0x1F: FailUnimpl::ldblockf_aiusl(); 1343 //ASI_BLOCK_PRIMARY 1344 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}}); 1345 //ASI_BLOCK_SECONDARY 1346 0xF1: FailUnimpl::ldblockf_s(); 1347 //ASI_BLOCK_PRIMARY_LITTLE 1348 0xF8: FailUnimpl::ldblockf_pl(); 1349 //ASI_BLOCK_SECONDARY_LITTLE 1350 0xF9: FailUnimpl::ldblockf_sl(); 1351 } 1352 1353 //LDSHORTF 1354 //ASI_FL8_PRIMARY 1355 0xD0: FailUnimpl::ldshortf_8p(); 1356 //ASI_FL8_SECONDARY 1357 0xD1: FailUnimpl::ldshortf_8s(); 1358 //ASI_FL8_PRIMARY_LITTLE 1359 0xD8: FailUnimpl::ldshortf_8pl(); 1360 //ASI_FL8_SECONDARY_LITTLE 1361 0xD9: FailUnimpl::ldshortf_8sl(); 1362 //ASI_FL16_PRIMARY 1363 0xD2: FailUnimpl::ldshortf_16p(); 1364 //ASI_FL16_SECONDARY 1365 0xD3: FailUnimpl::ldshortf_16s(); 1366 //ASI_FL16_PRIMARY_LITTLE 1367 0xDA: FailUnimpl::ldshortf_16pl(); 1368 //ASI_FL16_SECONDARY_LITTLE 1369 0xDB: FailUnimpl::ldshortf_16sl(); 1370 //Not an ASI which is legal with lddfa 1371 default: Trap::lddfa_bad_asi( 1372 {{fault = new DataAccessException;}}); 1373 } 1374 } 1375 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); 1376 0x36: stqfa({{fault = new FpDisabled;}}); 1377 format StoreAlt { 1378 0x37: decode EXT_ASI { 1379 //ASI_NUCLEUS 1380 0x04: FailUnimpl::stdfa_n(); 1381 //ASI_NUCLEUS_LITTLE 1382 0x0C: FailUnimpl::stdfa_nl(); 1383 //ASI_AS_IF_USER_PRIMARY 1384 0x10: FailUnimpl::stdfa_aiup(); 1385 //ASI_AS_IF_USER_PRIMARY_LITTLE 1386 0x18: FailUnimpl::stdfa_aiupl(); 1387 //ASI_AS_IF_USER_SECONDARY 1388 0x11: FailUnimpl::stdfa_aius(); 1389 //ASI_AS_IF_USER_SECONDARY_LITTLE 1390 0x19: FailUnimpl::stdfa_aiusl(); 1391 //ASI_REAL 1392 0x14: FailUnimpl::stdfa_real(); 1393 //ASI_REAL_LITTLE 1394 0x1C: FailUnimpl::stdfa_real_l(); 1395 //ASI_REAL_IO 1396 0x15: FailUnimpl::stdfa_real_io(); 1397 //ASI_REAL_IO_LITTLE 1398 0x1D: FailUnimpl::stdfa_real_io_l(); 1399 //ASI_PRIMARY 1400 0x80: FailUnimpl::stdfa_p(); 1401 //ASI_PRIMARY_LITTLE 1402 0x88: FailUnimpl::stdfa_pl(); 1403 //ASI_SECONDARY 1404 0x81: FailUnimpl::stdfa_s(); 1405 //ASI_SECONDARY_LITTLE 1406 0x89: FailUnimpl::stdfa_sl(); 1407 //ASI_PRIMARY_NO_FAULT 1408 0x82: FailUnimpl::stdfa_pnf(); 1409 //ASI_PRIMARY_NO_FAULT_LITTLE 1410 0x8A: FailUnimpl::stdfa_pnfl(); 1411 //ASI_SECONDARY_NO_FAULT 1412 0x83: FailUnimpl::stdfa_snf(); 1413 //ASI_SECONDARY_NO_FAULT_LITTLE 1414 0x8B: FailUnimpl::stdfa_snfl(); 1415 1416 format BlockStore { 1417 // STBLOCKF 1418 //ASI_BLOCK_AS_IF_USER_PRIMARY 1419 0x16: FailUnimpl::stblockf_aiup(); 1420 //ASI_BLOCK_AS_IF_USER_SECONDARY 1421 0x17: FailUnimpl::stblockf_aius(); 1422 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1423 0x1E: FailUnimpl::stblockf_aiupl(); 1424 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1425 0x1F: FailUnimpl::stblockf_aiusl(); 1426 //ASI_BLOCK_PRIMARY 1427 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}}); 1428 //ASI_BLOCK_SECONDARY 1429 0xF1: FailUnimpl::stblockf_s(); 1430 //ASI_BLOCK_PRIMARY_LITTLE 1431 0xF8: FailUnimpl::stblockf_pl(); 1432 //ASI_BLOCK_SECONDARY_LITTLE 1433 0xF9: FailUnimpl::stblockf_sl(); 1434 } 1435 1436 //STSHORTF 1437 //ASI_FL8_PRIMARY 1438 0xD0: FailUnimpl::stshortf_8p(); 1439 //ASI_FL8_SECONDARY 1440 0xD1: FailUnimpl::stshortf_8s(); 1441 //ASI_FL8_PRIMARY_LITTLE 1442 0xD8: FailUnimpl::stshortf_8pl(); 1443 //ASI_FL8_SECONDARY_LITTLE 1444 0xD9: FailUnimpl::stshortf_8sl(); 1445 //ASI_FL16_PRIMARY 1446 0xD2: FailUnimpl::stshortf_16p(); 1447 //ASI_FL16_SECONDARY 1448 0xD3: FailUnimpl::stshortf_16s(); 1449 //ASI_FL16_PRIMARY_LITTLE 1450 0xDA: FailUnimpl::stshortf_16pl(); 1451 //ASI_FL16_SECONDARY_LITTLE 1452 0xDB: FailUnimpl::stshortf_16sl(); 1453 //Not an ASI which is legal with lddfa 1454 default: Trap::stdfa_bad_asi( 1455 {{fault = new DataAccessException;}}); 1456 } 1457 } 1458 0x3C: CasAlt::casa({{ 1459 mem_data = htog(Rs2.uw); 1460 Mem.uw = Rd.uw;}}, 1461 {{ 1462 uint32_t tmp = mem_data; 1463 Rd.uw = tmp; 1464 }}, {{EXT_ASI}}, MEM_SWAP_COND); 1465 0x3D: Nop::prefetcha({{ }}); 1466 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); 1467 Mem.udw = Rd.udw; }}, 1468 {{ Rd.udw = mem_data; }}, {{EXT_ASI}}, MEM_SWAP_COND); 1469 } 1470 } 1471} 1472