utility.hh revision 12119
111723Sar4jc@virginia.edu/* 211723Sar4jc@virginia.edu * Copyright (c) 2013 ARM Limited 311723Sar4jc@virginia.edu * Copyright (c) 2014-2015 Sven Karlsson 411723Sar4jc@virginia.edu * All rights reserved 511723Sar4jc@virginia.edu * 611723Sar4jc@virginia.edu * The license below extends only to copyright in the software and shall 711723Sar4jc@virginia.edu * not be construed as granting a license to any other intellectual 811723Sar4jc@virginia.edu * property including but not limited to intellectual property relating 911723Sar4jc@virginia.edu * to a hardware implementation of the functionality of the software 1011723Sar4jc@virginia.edu * licensed hereunder. You may use the software subject to the license 1111723Sar4jc@virginia.edu * terms below provided that you ensure that this notice is replicated 1211723Sar4jc@virginia.edu * unmodified and in its entirety in all distributions of the software, 1311723Sar4jc@virginia.edu * modified or unmodified, in source code or in binary form. 1411723Sar4jc@virginia.edu * 1512119Sar4jc@virginia.edu * Copyright (c) 2016-2017 The University of Virginia 1611723Sar4jc@virginia.edu * All rights reserved. 1711723Sar4jc@virginia.edu * 1811723Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without 1911723Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are 2011723Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright 2111723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer; 2211723Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright 2311723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the 2411723Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution; 2511723Sar4jc@virginia.edu * neither the name of the copyright holders nor the names of its 2611723Sar4jc@virginia.edu * contributors may be used to endorse or promote products derived from 2711723Sar4jc@virginia.edu * this software without specific prior written permission. 2811723Sar4jc@virginia.edu * 2911723Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3011723Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3111723Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3211723Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3311723Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3411723Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3511723Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3611723Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3711723Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3811723Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3911723Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4011723Sar4jc@virginia.edu * 4111723Sar4jc@virginia.edu * Authors: Andreas Hansson 4211723Sar4jc@virginia.edu * Sven Karlsson 4311723Sar4jc@virginia.edu * Alec Roelke 4411723Sar4jc@virginia.edu */ 4511723Sar4jc@virginia.edu 4611723Sar4jc@virginia.edu#ifndef __ARCH_RISCV_UTILITY_HH__ 4711723Sar4jc@virginia.edu#define __ARCH_RISCV_UTILITY_HH__ 4811723Sar4jc@virginia.edu 4911723Sar4jc@virginia.edu#include <cmath> 5011723Sar4jc@virginia.edu#include <cstdint> 5112119Sar4jc@virginia.edu#include <string> 5211723Sar4jc@virginia.edu 5312119Sar4jc@virginia.edu#include "arch/riscv/registers.hh" 5411723Sar4jc@virginia.edu#include "base/types.hh" 5512119Sar4jc@virginia.edu#include "cpu/reg_class.hh" 5611723Sar4jc@virginia.edu#include "cpu/static_inst.hh" 5711723Sar4jc@virginia.edu#include "cpu/thread_context.hh" 5811723Sar4jc@virginia.edu 5911723Sar4jc@virginia.edunamespace RiscvISA 6011723Sar4jc@virginia.edu{ 6111723Sar4jc@virginia.edu 6211725Sar4jc@virginia.edutemplate<typename T> inline bool 6311725Sar4jc@virginia.eduisquietnan(T val) 6411725Sar4jc@virginia.edu{ 6511725Sar4jc@virginia.edu return false; 6611725Sar4jc@virginia.edu} 6711725Sar4jc@virginia.edu 6811725Sar4jc@virginia.edutemplate<> inline bool 6911725Sar4jc@virginia.eduisquietnan<float>(float val) 7011725Sar4jc@virginia.edu{ 7111725Sar4jc@virginia.edu return std::isnan(val) 7211725Sar4jc@virginia.edu && (reinterpret_cast<uint32_t&>(val)&0x00400000); 7311725Sar4jc@virginia.edu} 7411725Sar4jc@virginia.edu 7511725Sar4jc@virginia.edutemplate<> inline bool 7611725Sar4jc@virginia.eduisquietnan<double>(double val) 7711725Sar4jc@virginia.edu{ 7811725Sar4jc@virginia.edu return std::isnan(val) 7911725Sar4jc@virginia.edu && (reinterpret_cast<uint64_t&>(val)&0x0008000000000000ULL); 8011725Sar4jc@virginia.edu} 8111725Sar4jc@virginia.edu 8211725Sar4jc@virginia.edutemplate<typename T> inline bool 8311725Sar4jc@virginia.eduissignalingnan(T val) 8411725Sar4jc@virginia.edu{ 8511725Sar4jc@virginia.edu return false; 8611725Sar4jc@virginia.edu} 8711725Sar4jc@virginia.edu 8811725Sar4jc@virginia.edutemplate<> inline bool 8911725Sar4jc@virginia.eduissignalingnan<float>(float val) 9011725Sar4jc@virginia.edu{ 9111725Sar4jc@virginia.edu return std::isnan(val) 9211725Sar4jc@virginia.edu && (reinterpret_cast<uint32_t&>(val)&0x00200000); 9311725Sar4jc@virginia.edu} 9411725Sar4jc@virginia.edu 9511725Sar4jc@virginia.edutemplate<> inline bool 9611725Sar4jc@virginia.eduissignalingnan<double>(double val) 9711725Sar4jc@virginia.edu{ 9811725Sar4jc@virginia.edu return std::isnan(val) 9911725Sar4jc@virginia.edu && (reinterpret_cast<uint64_t&>(val)&0x0004000000000000ULL); 10011725Sar4jc@virginia.edu} 10111725Sar4jc@virginia.edu 10211723Sar4jc@virginia.eduinline PCState 10311723Sar4jc@virginia.edubuildRetPC(const PCState &curPC, const PCState &callPC) 10411723Sar4jc@virginia.edu{ 10511723Sar4jc@virginia.edu PCState retPC = callPC; 10611723Sar4jc@virginia.edu retPC.advance(); 10711723Sar4jc@virginia.edu retPC.pc(curPC.npc()); 10811723Sar4jc@virginia.edu return retPC; 10911723Sar4jc@virginia.edu} 11011723Sar4jc@virginia.edu 11111723Sar4jc@virginia.eduinline uint64_t 11211723Sar4jc@virginia.edugetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 11311723Sar4jc@virginia.edu{ 11411723Sar4jc@virginia.edu return 0; 11511723Sar4jc@virginia.edu} 11611723Sar4jc@virginia.edu 11711723Sar4jc@virginia.eduinline void startupCPU(ThreadContext *tc, int cpuId) 11811723Sar4jc@virginia.edu{ 11911723Sar4jc@virginia.edu} 12011723Sar4jc@virginia.edu 12111723Sar4jc@virginia.eduinline void 12211723Sar4jc@virginia.educopyRegs(ThreadContext *src, ThreadContext *dest) 12311723Sar4jc@virginia.edu{ 12411723Sar4jc@virginia.edu // First loop through the integer registers. 12511723Sar4jc@virginia.edu for (int i = 0; i < NumIntRegs; ++i) 12611723Sar4jc@virginia.edu dest->setIntReg(i, src->readIntReg(i)); 12711723Sar4jc@virginia.edu 12811723Sar4jc@virginia.edu // Lastly copy PC/NPC 12911723Sar4jc@virginia.edu dest->pcState(src->pcState()); 13011723Sar4jc@virginia.edu} 13111723Sar4jc@virginia.edu 13212119Sar4jc@virginia.eduinline std::string 13312119Sar4jc@virginia.eduregisterName(RegId reg) 13412119Sar4jc@virginia.edu{ 13512119Sar4jc@virginia.edu if (reg.isIntReg()) { 13612119Sar4jc@virginia.edu return IntRegNames[reg.index()]; 13712119Sar4jc@virginia.edu } else { 13812119Sar4jc@virginia.edu return FloatRegNames[reg.index()]; 13912119Sar4jc@virginia.edu } 14012119Sar4jc@virginia.edu} 14112119Sar4jc@virginia.edu 14211723Sar4jc@virginia.eduinline void 14311723Sar4jc@virginia.eduskipFunction(ThreadContext *tc) 14411723Sar4jc@virginia.edu{ 14511723Sar4jc@virginia.edu panic("Not Implemented for Riscv"); 14611723Sar4jc@virginia.edu} 14711723Sar4jc@virginia.edu 14811723Sar4jc@virginia.eduinline void 14911723Sar4jc@virginia.eduadvancePC(PCState &pc, const StaticInstPtr &inst) 15011723Sar4jc@virginia.edu{ 15111723Sar4jc@virginia.edu inst->advancePC(pc); 15211723Sar4jc@virginia.edu} 15311723Sar4jc@virginia.edu 15411723Sar4jc@virginia.edustatic inline bool 15511723Sar4jc@virginia.eduinUserMode(ThreadContext *tc) 15611723Sar4jc@virginia.edu{ 15711723Sar4jc@virginia.edu return true; 15811723Sar4jc@virginia.edu} 15911723Sar4jc@virginia.edu 16011723Sar4jc@virginia.eduinline uint64_t 16111723Sar4jc@virginia.edugetExecutingAsid(ThreadContext *tc) 16211723Sar4jc@virginia.edu{ 16311723Sar4jc@virginia.edu return 0; 16411723Sar4jc@virginia.edu} 16511723Sar4jc@virginia.edu 16611723Sar4jc@virginia.eduinline void 16711723Sar4jc@virginia.eduinitCPU(ThreadContext *, int cpuId) 16811723Sar4jc@virginia.edu{ 16911723Sar4jc@virginia.edu panic("initCPU not implemented for Riscv.\n"); 17011723Sar4jc@virginia.edu} 17111723Sar4jc@virginia.edu 17211723Sar4jc@virginia.edu} // namespace RiscvISA 17311723Sar4jc@virginia.edu 17411723Sar4jc@virginia.edu#endif // __ARCH_RISCV_UTILITY_HH__ 175