utility.hh revision 12119 
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2016-2017 The University of Virginia
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Andreas Hansson
42 *          Sven Karlsson
43 *          Alec Roelke
44 */
45
46#ifndef __ARCH_RISCV_UTILITY_HH__
47#define __ARCH_RISCV_UTILITY_HH__
48
49#include <cmath>
50#include <cstdint>
51#include <string>
52
53#include "arch/riscv/registers.hh"
54#include "base/types.hh"
55#include "cpu/reg_class.hh"
56#include "cpu/static_inst.hh"
57#include "cpu/thread_context.hh"
58
59namespace RiscvISA
60{
61
62template<typename T> inline bool
63isquietnan(T val)
64{
65    return false;
66}
67
68template<> inline bool
69isquietnan<float>(float val)
70{
71    return std::isnan(val)
72        && (reinterpret_cast<uint32_t&>(val)&0x00400000);
73}
74
75template<> inline bool
76isquietnan<double>(double val)
77{
78    return std::isnan(val)
79        && (reinterpret_cast<uint64_t&>(val)&0x0008000000000000ULL);
80}
81
82template<typename T> inline bool
83issignalingnan(T val)
84{
85    return false;
86}
87
88template<> inline bool
89issignalingnan<float>(float val)
90{
91    return std::isnan(val)
92        && (reinterpret_cast<uint32_t&>(val)&0x00200000);
93}
94
95template<> inline bool
96issignalingnan<double>(double val)
97{
98    return std::isnan(val)
99        && (reinterpret_cast<uint64_t&>(val)&0x0004000000000000ULL);
100}
101
102inline PCState
103buildRetPC(const PCState &curPC, const PCState &callPC)
104{
105    PCState retPC = callPC;
106    retPC.advance();
107    retPC.pc(curPC.npc());
108    return retPC;
109}
110
111inline uint64_t
112getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
113{
114    return 0;
115}
116
117inline void startupCPU(ThreadContext *tc, int cpuId)
118{
119}
120
121inline void
122copyRegs(ThreadContext *src, ThreadContext *dest)
123{
124    // First loop through the integer registers.
125    for (int i = 0; i < NumIntRegs; ++i)
126        dest->setIntReg(i, src->readIntReg(i));
127
128    // Lastly copy PC/NPC
129    dest->pcState(src->pcState());
130}
131
132inline std::string
133registerName(RegId reg)
134{
135    if (reg.isIntReg()) {
136        return IntRegNames[reg.index()];
137    } else {
138        return FloatRegNames[reg.index()];
139    }
140}
141
142inline void
143skipFunction(ThreadContext *tc)
144{
145    panic("Not Implemented for Riscv");
146}
147
148inline void
149advancePC(PCState &pc, const StaticInstPtr &inst)
150{
151    inst->advancePC(pc);
152}
153
154static inline bool
155inUserMode(ThreadContext *tc)
156{
157    return true;
158}
159
160inline uint64_t
161getExecutingAsid(ThreadContext *tc)
162{
163    return 0;
164}
165
166inline void
167initCPU(ThreadContext *, int cpuId)
168{
169    panic("initCPU not implemented for Riscv.\n");
170}
171
172} // namespace RiscvISA
173
174#endif // __ARCH_RISCV_UTILITY_HH__
175