decoder.isa revision 12136
111723Sar4jc@virginia.edu// -*- mode:c++ -*- 211723Sar4jc@virginia.edu 311723Sar4jc@virginia.edu// Copyright (c) 2015 RISC-V Foundation 412120Sar4jc@virginia.edu// Copyright (c) 2017 The University of Virginia 511723Sar4jc@virginia.edu// All rights reserved. 611723Sar4jc@virginia.edu// 711723Sar4jc@virginia.edu// Redistribution and use in source and binary forms, with or without 811723Sar4jc@virginia.edu// modification, are permitted provided that the following conditions are 911723Sar4jc@virginia.edu// met: redistributions of source code must retain the above copyright 1011723Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer; 1111723Sar4jc@virginia.edu// redistributions in binary form must reproduce the above copyright 1211723Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer in the 1311723Sar4jc@virginia.edu// documentation and/or other materials provided with the distribution; 1411723Sar4jc@virginia.edu// neither the name of the copyright holders nor the names of its 1511723Sar4jc@virginia.edu// contributors may be used to endorse or promote products derived from 1611723Sar4jc@virginia.edu// this software without specific prior written permission. 1711723Sar4jc@virginia.edu// 1811723Sar4jc@virginia.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1911723Sar4jc@virginia.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2011723Sar4jc@virginia.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2111723Sar4jc@virginia.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2211723Sar4jc@virginia.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2311723Sar4jc@virginia.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2411723Sar4jc@virginia.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2511723Sar4jc@virginia.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2611723Sar4jc@virginia.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2711723Sar4jc@virginia.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2811723Sar4jc@virginia.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2911723Sar4jc@virginia.edu// 3011723Sar4jc@virginia.edu// Authors: Alec Roelke 3111723Sar4jc@virginia.edu 3211723Sar4jc@virginia.edu//////////////////////////////////////////////////////////////////// 3311723Sar4jc@virginia.edu// 3411723Sar4jc@virginia.edu// The RISC-V ISA decoder 3511723Sar4jc@virginia.edu// 3611723Sar4jc@virginia.edu 3712120Sar4jc@virginia.edudecode QUADRANT default Unknown::unknown() { 3812120Sar4jc@virginia.edu 0x0: decode COPCODE { 3912120Sar4jc@virginia.edu 0x0: CUIOp::c_addi4spn({{ 4012120Sar4jc@virginia.edu imm = CIMM8<1:1> << 2 | 4112120Sar4jc@virginia.edu CIMM8<0:0> << 3 | 4212120Sar4jc@virginia.edu CIMM8<7:6> << 4 | 4312120Sar4jc@virginia.edu CIMM8<5:2> << 6; 4412120Sar4jc@virginia.edu }}, {{ 4512136Sar4jc@virginia.edu if (machInst == 0) 4612136Sar4jc@virginia.edu fault = make_shared<IllegalInstFault>("zero instruction"); 4712120Sar4jc@virginia.edu Rp2 = sp + imm; 4812120Sar4jc@virginia.edu }}); 4912120Sar4jc@virginia.edu format CompressedLoad { 5012120Sar4jc@virginia.edu 0x1: c_fld({{ 5112120Sar4jc@virginia.edu ldisp = CIMM3 << 3 | CIMM2 << 6; 5212120Sar4jc@virginia.edu }}, {{ 5312120Sar4jc@virginia.edu Fp2_bits = Mem; 5412120Sar4jc@virginia.edu }}, {{ 5512120Sar4jc@virginia.edu EA = Rp1 + ldisp; 5611723Sar4jc@virginia.edu }}); 5712120Sar4jc@virginia.edu 0x2: c_lw({{ 5812120Sar4jc@virginia.edu ldisp = CIMM2<1:1> << 2 | 5912120Sar4jc@virginia.edu CIMM3 << 3 | 6012120Sar4jc@virginia.edu CIMM2<0:0> << 6; 6112120Sar4jc@virginia.edu }}, {{ 6212120Sar4jc@virginia.edu Rp2_sd = Mem_sw; 6312120Sar4jc@virginia.edu }}, {{ 6412120Sar4jc@virginia.edu EA = Rp1 + ldisp; 6511723Sar4jc@virginia.edu }}); 6612120Sar4jc@virginia.edu 0x3: c_ld({{ 6712120Sar4jc@virginia.edu ldisp = CIMM3 << 3 | CIMM2 << 6; 6812120Sar4jc@virginia.edu }}, {{ 6912120Sar4jc@virginia.edu Rp2_sd = Mem_sd; 7012120Sar4jc@virginia.edu }}, {{ 7112120Sar4jc@virginia.edu EA = Rp1 + ldisp; 7211723Sar4jc@virginia.edu }}); 7312120Sar4jc@virginia.edu } 7412120Sar4jc@virginia.edu format CompressedStore { 7512120Sar4jc@virginia.edu 0x5: c_fsd({{ 7612120Sar4jc@virginia.edu sdisp = CIMM3 << 3 | CIMM2 << 6; 7712120Sar4jc@virginia.edu }}, {{ 7812120Sar4jc@virginia.edu Mem = Fp2_bits; 7912120Sar4jc@virginia.edu }}, {{ 8012120Sar4jc@virginia.edu EA = Rp1 + sdisp; 8111723Sar4jc@virginia.edu }}); 8212120Sar4jc@virginia.edu 0x6: c_sw({{ 8312120Sar4jc@virginia.edu sdisp = CIMM2<1:1> << 2 | 8412120Sar4jc@virginia.edu CIMM3 << 3 | 8512120Sar4jc@virginia.edu CIMM2<0:0> << 6; 8612120Sar4jc@virginia.edu }}, {{ 8712120Sar4jc@virginia.edu Mem_uw = Rp2_uw; 8812120Sar4jc@virginia.edu }}, ea_code={{ 8912120Sar4jc@virginia.edu EA = Rp1 + sdisp; 9011723Sar4jc@virginia.edu }}); 9112120Sar4jc@virginia.edu 0x7: c_sd({{ 9212120Sar4jc@virginia.edu sdisp = CIMM3 << 3 | CIMM2 << 6; 9312120Sar4jc@virginia.edu }}, {{ 9412120Sar4jc@virginia.edu Mem_ud = Rp2_ud; 9512120Sar4jc@virginia.edu }}, {{ 9612120Sar4jc@virginia.edu EA = Rp1 + sdisp; 9711723Sar4jc@virginia.edu }}); 9811723Sar4jc@virginia.edu } 9911723Sar4jc@virginia.edu } 10012120Sar4jc@virginia.edu 0x1: decode COPCODE { 10112120Sar4jc@virginia.edu format CIOp { 10212120Sar4jc@virginia.edu 0x0: c_addi({{ 10312120Sar4jc@virginia.edu imm = CIMM5; 10412120Sar4jc@virginia.edu if (CIMM1 > 0) 10512120Sar4jc@virginia.edu imm |= ~((uint64_t)0x1F); 10612120Sar4jc@virginia.edu }}, {{ 10712136Sar4jc@virginia.edu if ((RC1 == 0) != (imm == 0)) { 10812136Sar4jc@virginia.edu if (RC1 == 0) { 10912136Sar4jc@virginia.edu fault = make_shared<IllegalInstFault>("source reg x0"); 11012136Sar4jc@virginia.edu } else // imm == 0 11112136Sar4jc@virginia.edu fault = make_shared<IllegalInstFault>("immediate = 0"); 11212136Sar4jc@virginia.edu } 11312120Sar4jc@virginia.edu Rc1_sd = Rc1_sd + imm; 11412120Sar4jc@virginia.edu }}); 11512120Sar4jc@virginia.edu 0x1: c_addiw({{ 11612120Sar4jc@virginia.edu imm = CIMM5; 11712120Sar4jc@virginia.edu if (CIMM1 > 0) 11812120Sar4jc@virginia.edu imm |= ~((uint64_t)0x1F); 11912120Sar4jc@virginia.edu }}, {{ 12012120Sar4jc@virginia.edu assert(RC1 != 0); 12112120Sar4jc@virginia.edu Rc1_sd = (int32_t)Rc1_sd + imm; 12212120Sar4jc@virginia.edu }}); 12312120Sar4jc@virginia.edu 0x2: c_li({{ 12412120Sar4jc@virginia.edu imm = CIMM5; 12512120Sar4jc@virginia.edu if (CIMM1 > 0) 12612120Sar4jc@virginia.edu imm |= ~((uint64_t)0x1F); 12712120Sar4jc@virginia.edu }}, {{ 12812120Sar4jc@virginia.edu assert(RC1 != 0); 12912120Sar4jc@virginia.edu Rc1_sd = imm; 13012120Sar4jc@virginia.edu }}); 13112120Sar4jc@virginia.edu 0x3: decode RC1 { 13212120Sar4jc@virginia.edu 0x2: c_addi16sp({{ 13312120Sar4jc@virginia.edu imm = CIMM5<4:4> << 4 | 13412120Sar4jc@virginia.edu CIMM5<0:0> << 5 | 13512120Sar4jc@virginia.edu CIMM5<3:3> << 6 | 13612120Sar4jc@virginia.edu CIMM5<2:1> << 7; 13712120Sar4jc@virginia.edu if (CIMM1 > 0) 13812120Sar4jc@virginia.edu imm |= ~((int64_t)0x1FF); 13912120Sar4jc@virginia.edu }}, {{ 14012120Sar4jc@virginia.edu assert(imm != 0); 14112120Sar4jc@virginia.edu sp_sd = sp_sd + imm; 14212120Sar4jc@virginia.edu }}); 14312120Sar4jc@virginia.edu default: c_lui({{ 14412120Sar4jc@virginia.edu imm = CIMM5 << 12; 14512120Sar4jc@virginia.edu if (CIMM1 > 0) 14612120Sar4jc@virginia.edu imm |= ~((uint64_t)0x1FFFF); 14712120Sar4jc@virginia.edu }}, {{ 14812120Sar4jc@virginia.edu assert(RC1 != 0 && RC1 != 2); 14912120Sar4jc@virginia.edu assert(imm != 0); 15012120Sar4jc@virginia.edu Rc1_sd = imm; 15112120Sar4jc@virginia.edu }}); 15212120Sar4jc@virginia.edu } 15312120Sar4jc@virginia.edu } 15412120Sar4jc@virginia.edu 0x4: decode CFUNCT2HIGH { 15512120Sar4jc@virginia.edu format CUIOp { 15612120Sar4jc@virginia.edu 0x0: c_srli({{ 15712120Sar4jc@virginia.edu imm = CIMM5 | (CIMM1 << 5); 15812120Sar4jc@virginia.edu assert(imm != 0); 15912120Sar4jc@virginia.edu }}, {{ 16012120Sar4jc@virginia.edu Rp1 = Rp1 >> imm; 16112120Sar4jc@virginia.edu }}); 16212120Sar4jc@virginia.edu 0x1: c_srai({{ 16312120Sar4jc@virginia.edu imm = CIMM5 | (CIMM1 << 5); 16412120Sar4jc@virginia.edu assert(imm != 0); 16512120Sar4jc@virginia.edu }}, {{ 16612120Sar4jc@virginia.edu Rp1_sd = Rp1_sd >> imm; 16712120Sar4jc@virginia.edu }}); 16812120Sar4jc@virginia.edu 0x2: c_andi({{ 16912120Sar4jc@virginia.edu imm = CIMM5; 17012120Sar4jc@virginia.edu if (CIMM1 > 0) 17112120Sar4jc@virginia.edu imm |= ~((uint64_t)0x1F); 17212120Sar4jc@virginia.edu }}, {{ 17312120Sar4jc@virginia.edu Rp1 = Rp1 & imm; 17412120Sar4jc@virginia.edu }}); 17512120Sar4jc@virginia.edu } 17612120Sar4jc@virginia.edu format ROp { 17712120Sar4jc@virginia.edu 0x3: decode CFUNCT1 { 17812120Sar4jc@virginia.edu 0x0: decode CFUNCT2LOW { 17912120Sar4jc@virginia.edu 0x0: c_sub({{ 18012120Sar4jc@virginia.edu Rp1 = Rp1 - Rp2; 18112120Sar4jc@virginia.edu }}); 18212120Sar4jc@virginia.edu 0x1: c_xor({{ 18312120Sar4jc@virginia.edu Rp1 = Rp1 ^ Rp2; 18412120Sar4jc@virginia.edu }}); 18512120Sar4jc@virginia.edu 0x2: c_or({{ 18612120Sar4jc@virginia.edu Rp1 = Rp1 | Rp2; 18712120Sar4jc@virginia.edu }}); 18812120Sar4jc@virginia.edu 0x3: c_and({{ 18912120Sar4jc@virginia.edu Rp1 = Rp1 & Rp2; 19012120Sar4jc@virginia.edu }}); 19112120Sar4jc@virginia.edu } 19212120Sar4jc@virginia.edu 0x1: decode CFUNCT2LOW { 19312120Sar4jc@virginia.edu 0x0: c_subw({{ 19412120Sar4jc@virginia.edu Rp1_sd = (int32_t)Rp1_sd - Rp2_sw; 19512120Sar4jc@virginia.edu }}); 19612120Sar4jc@virginia.edu 0x1: c_addw({{ 19712120Sar4jc@virginia.edu Rp1_sd = (int32_t)Rp1_sd + Rp2_sw; 19812120Sar4jc@virginia.edu }}); 19912120Sar4jc@virginia.edu } 20012120Sar4jc@virginia.edu } 20112120Sar4jc@virginia.edu } 20212120Sar4jc@virginia.edu } 20312120Sar4jc@virginia.edu 0x5: JOp::c_j({{ 20412120Sar4jc@virginia.edu int64_t offset = CJUMPIMM<3:1> << 1 | 20512120Sar4jc@virginia.edu CJUMPIMM<9:9> << 4 | 20612120Sar4jc@virginia.edu CJUMPIMM<0:0> << 5 | 20712120Sar4jc@virginia.edu CJUMPIMM<5:5> << 6 | 20812120Sar4jc@virginia.edu CJUMPIMM<4:4> << 7 | 20912120Sar4jc@virginia.edu CJUMPIMM<8:7> << 8 | 21012120Sar4jc@virginia.edu CJUMPIMM<6:6> << 10; 21112120Sar4jc@virginia.edu if (CJUMPIMM<10:10> > 0) 21212120Sar4jc@virginia.edu offset |= ~((int64_t)0x7FF); 21312120Sar4jc@virginia.edu NPC = PC + offset; 21412120Sar4jc@virginia.edu }}, IsIndirectControl, IsUncondControl, IsCall); 21512120Sar4jc@virginia.edu format BOp { 21612120Sar4jc@virginia.edu 0x6: c_beqz({{ 21712120Sar4jc@virginia.edu int64_t offset = CIMM5<2:1> << 1 | 21812120Sar4jc@virginia.edu CIMM3<1:0> << 3 | 21912120Sar4jc@virginia.edu CIMM5<0:0> << 5 | 22012120Sar4jc@virginia.edu CIMM5<4:3> << 6; 22112120Sar4jc@virginia.edu if (CIMM3<2:2> > 0) 22212120Sar4jc@virginia.edu offset |= ~((int64_t)0xFF); 22311723Sar4jc@virginia.edu 22412120Sar4jc@virginia.edu if (Rp1 == 0) 22512120Sar4jc@virginia.edu NPC = PC + offset; 22612120Sar4jc@virginia.edu else 22712120Sar4jc@virginia.edu NPC = NPC; 22812120Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 22912120Sar4jc@virginia.edu 0x7: c_bnez({{ 23012120Sar4jc@virginia.edu int64_t offset = CIMM5<2:1> << 1 | 23112120Sar4jc@virginia.edu CIMM3<1:0> << 3 | 23212120Sar4jc@virginia.edu CIMM5<0:0> << 5 | 23312120Sar4jc@virginia.edu CIMM5<4:3> << 6; 23412120Sar4jc@virginia.edu if (CIMM3<2:2> > 0) 23512120Sar4jc@virginia.edu offset |= ~((int64_t)0xFF); 23612120Sar4jc@virginia.edu 23712120Sar4jc@virginia.edu if (Rp1 != 0) 23812120Sar4jc@virginia.edu NPC = PC + offset; 23912120Sar4jc@virginia.edu else 24012120Sar4jc@virginia.edu NPC = NPC; 24112120Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 24212120Sar4jc@virginia.edu } 24312120Sar4jc@virginia.edu } 24412120Sar4jc@virginia.edu 0x2: decode COPCODE { 24512120Sar4jc@virginia.edu 0x0: CUIOp::c_slli({{ 24612120Sar4jc@virginia.edu imm = CIMM5 | (CIMM1 << 5); 24712120Sar4jc@virginia.edu assert(imm != 0); 24812120Sar4jc@virginia.edu }}, {{ 24912120Sar4jc@virginia.edu assert(RC1 != 0); 25012120Sar4jc@virginia.edu Rc1 = Rc1 << imm; 25112120Sar4jc@virginia.edu }}); 25212120Sar4jc@virginia.edu format CompressedLoad { 25312120Sar4jc@virginia.edu 0x1: c_fldsp({{ 25412120Sar4jc@virginia.edu ldisp = CIMM5<4:3> << 3 | 25512120Sar4jc@virginia.edu CIMM1 << 5 | 25612120Sar4jc@virginia.edu CIMM5<2:0> << 6; 25712120Sar4jc@virginia.edu }}, {{ 25812120Sar4jc@virginia.edu Fc1_bits = Mem; 25912120Sar4jc@virginia.edu }}, {{ 26012120Sar4jc@virginia.edu EA = sp + ldisp; 26111725Sar4jc@virginia.edu }}); 26212120Sar4jc@virginia.edu 0x2: c_lwsp({{ 26312120Sar4jc@virginia.edu ldisp = CIMM5<4:2> << 2 | 26412120Sar4jc@virginia.edu CIMM1 << 5 | 26512120Sar4jc@virginia.edu CIMM5<1:0> << 6; 26612120Sar4jc@virginia.edu }}, {{ 26712120Sar4jc@virginia.edu assert(RC1 != 0); 26812120Sar4jc@virginia.edu Rc1_sd = Mem_sw; 26912120Sar4jc@virginia.edu }}, {{ 27012120Sar4jc@virginia.edu EA = sp + ldisp; 27112120Sar4jc@virginia.edu }}); 27212120Sar4jc@virginia.edu 0x3: c_ldsp({{ 27312120Sar4jc@virginia.edu ldisp = CIMM5<4:3> << 3 | 27412120Sar4jc@virginia.edu CIMM1 << 5 | 27512120Sar4jc@virginia.edu CIMM5<2:0> << 6; 27612120Sar4jc@virginia.edu }}, {{ 27712120Sar4jc@virginia.edu assert(RC1 != 0); 27812120Sar4jc@virginia.edu Rc1_sd = Mem_sd; 27912120Sar4jc@virginia.edu }}, {{ 28012120Sar4jc@virginia.edu EA = sp + ldisp; 28112120Sar4jc@virginia.edu }}); 28212120Sar4jc@virginia.edu } 28312120Sar4jc@virginia.edu 0x4: decode CFUNCT1 { 28412120Sar4jc@virginia.edu 0x0: decode RC2 { 28512120Sar4jc@virginia.edu 0x0: Jump::c_jr({{ 28612120Sar4jc@virginia.edu assert(RC1 != 0); 28712120Sar4jc@virginia.edu NPC = Rc1; 28812120Sar4jc@virginia.edu }}, IsIndirectControl, IsUncondControl, IsCall); 28912120Sar4jc@virginia.edu default: CROp::c_mv({{ 29012120Sar4jc@virginia.edu assert(RC1 != 0); 29112120Sar4jc@virginia.edu Rc1 = Rc2; 29212120Sar4jc@virginia.edu }}); 29312120Sar4jc@virginia.edu } 29412120Sar4jc@virginia.edu 0x1: decode RC1 { 29512120Sar4jc@virginia.edu 0x0: SystemOp::c_ebreak({{ 29612120Sar4jc@virginia.edu assert(RC2 == 0); 29712120Sar4jc@virginia.edu fault = make_shared<BreakpointFault>(); 29812120Sar4jc@virginia.edu }}, IsSerializeAfter, IsNonSpeculative, No_OpClass); 29912120Sar4jc@virginia.edu default: decode RC2 { 30012120Sar4jc@virginia.edu 0x0: Jump::c_jalr({{ 30112120Sar4jc@virginia.edu assert(RC1 != 0); 30212120Sar4jc@virginia.edu ra = NPC; 30312120Sar4jc@virginia.edu NPC = Rc1; 30412120Sar4jc@virginia.edu }}, IsIndirectControl, IsUncondControl, IsCall); 30512120Sar4jc@virginia.edu default: ROp::c_add({{ 30612120Sar4jc@virginia.edu Rc1_sd = Rc1_sd + Rc2_sd; 30712120Sar4jc@virginia.edu }}); 30812120Sar4jc@virginia.edu } 30912120Sar4jc@virginia.edu } 31012120Sar4jc@virginia.edu } 31112120Sar4jc@virginia.edu format CompressedStore { 31212120Sar4jc@virginia.edu 0x5: c_fsdsp({{ 31312120Sar4jc@virginia.edu sdisp = CIMM6<5:3> << 3 | 31412120Sar4jc@virginia.edu CIMM6<2:0> << 6; 31512120Sar4jc@virginia.edu }}, {{ 31612120Sar4jc@virginia.edu Mem_ud = Fc2_bits; 31712120Sar4jc@virginia.edu }}, {{ 31812120Sar4jc@virginia.edu EA = sp + sdisp; 31912120Sar4jc@virginia.edu }}); 32012120Sar4jc@virginia.edu 0x6: c_swsp({{ 32112120Sar4jc@virginia.edu sdisp = CIMM6<5:2> << 2 | 32212120Sar4jc@virginia.edu CIMM6<1:0> << 6; 32312120Sar4jc@virginia.edu }}, {{ 32412120Sar4jc@virginia.edu Mem_uw = Rc2_uw; 32512120Sar4jc@virginia.edu }}, {{ 32612120Sar4jc@virginia.edu EA = sp + sdisp; 32712120Sar4jc@virginia.edu }}); 32812120Sar4jc@virginia.edu 0x7: c_sdsp({{ 32912120Sar4jc@virginia.edu sdisp = CIMM6<5:3> << 3 | 33012120Sar4jc@virginia.edu CIMM6<2:0> << 6; 33112120Sar4jc@virginia.edu }}, {{ 33212120Sar4jc@virginia.edu Mem = Rc2; 33312120Sar4jc@virginia.edu }}, {{ 33412120Sar4jc@virginia.edu EA = sp + sdisp; 33511725Sar4jc@virginia.edu }}); 33611725Sar4jc@virginia.edu } 33711725Sar4jc@virginia.edu } 33812120Sar4jc@virginia.edu 0x3: decode OPCODE { 33912120Sar4jc@virginia.edu 0x00: decode FUNCT3 { 34012120Sar4jc@virginia.edu format Load { 34112120Sar4jc@virginia.edu 0x0: lb({{ 34212120Sar4jc@virginia.edu Rd_sd = Mem_sb; 34311723Sar4jc@virginia.edu }}); 34412120Sar4jc@virginia.edu 0x1: lh({{ 34512120Sar4jc@virginia.edu Rd_sd = Mem_sh; 34611723Sar4jc@virginia.edu }}); 34712120Sar4jc@virginia.edu 0x2: lw({{ 34812120Sar4jc@virginia.edu Rd_sd = Mem_sw; 34911723Sar4jc@virginia.edu }}); 35012120Sar4jc@virginia.edu 0x3: ld({{ 35112120Sar4jc@virginia.edu Rd_sd = Mem_sd; 35212120Sar4jc@virginia.edu }}); 35312120Sar4jc@virginia.edu 0x4: lbu({{ 35412120Sar4jc@virginia.edu Rd = Mem_ub; 35512120Sar4jc@virginia.edu }}); 35612120Sar4jc@virginia.edu 0x5: lhu({{ 35712120Sar4jc@virginia.edu Rd = Mem_uh; 35812120Sar4jc@virginia.edu }}); 35912120Sar4jc@virginia.edu 0x6: lwu({{ 36012120Sar4jc@virginia.edu Rd = Mem_uw; 36111723Sar4jc@virginia.edu }}); 36211723Sar4jc@virginia.edu } 36311723Sar4jc@virginia.edu } 36411723Sar4jc@virginia.edu 36512120Sar4jc@virginia.edu 0x01: decode FUNCT3 { 36612120Sar4jc@virginia.edu format Load { 36712120Sar4jc@virginia.edu 0x2: flw({{ 36812120Sar4jc@virginia.edu Fd_bits = (uint64_t)Mem_uw; 36912120Sar4jc@virginia.edu }}); 37012120Sar4jc@virginia.edu 0x3: fld({{ 37112120Sar4jc@virginia.edu Fd_bits = Mem; 37212120Sar4jc@virginia.edu }}); 37311726Sar4jc@virginia.edu } 37411726Sar4jc@virginia.edu } 37512120Sar4jc@virginia.edu 37612120Sar4jc@virginia.edu 0x03: decode FUNCT3 { 37712120Sar4jc@virginia.edu format IOp { 37812120Sar4jc@virginia.edu 0x0: fence({{ 37912120Sar4jc@virginia.edu }}, IsNonSpeculative, IsMemBarrier, No_OpClass); 38012120Sar4jc@virginia.edu 0x1: fence_i({{ 38112120Sar4jc@virginia.edu }}, IsNonSpeculative, IsSerializeAfter, No_OpClass); 38211726Sar4jc@virginia.edu } 38311726Sar4jc@virginia.edu } 38412120Sar4jc@virginia.edu 38512120Sar4jc@virginia.edu 0x04: decode FUNCT3 { 38612120Sar4jc@virginia.edu format IOp { 38712120Sar4jc@virginia.edu 0x0: addi({{ 38812120Sar4jc@virginia.edu Rd_sd = Rs1_sd + imm; 38911723Sar4jc@virginia.edu }}); 39012120Sar4jc@virginia.edu 0x1: slli({{ 39112120Sar4jc@virginia.edu Rd = Rs1 << SHAMT6; 39212120Sar4jc@virginia.edu }}); 39312120Sar4jc@virginia.edu 0x2: slti({{ 39412120Sar4jc@virginia.edu Rd = (Rs1_sd < imm) ? 1 : 0; 39512120Sar4jc@virginia.edu }}); 39612120Sar4jc@virginia.edu 0x3: sltiu({{ 39712120Sar4jc@virginia.edu Rd = (Rs1 < (uint64_t)imm) ? 1 : 0; 39812120Sar4jc@virginia.edu }}); 39912120Sar4jc@virginia.edu 0x4: xori({{ 40012120Sar4jc@virginia.edu Rd = Rs1 ^ (uint64_t)imm; 40112120Sar4jc@virginia.edu }}); 40212120Sar4jc@virginia.edu 0x5: decode SRTYPE { 40312120Sar4jc@virginia.edu 0x0: srli({{ 40412120Sar4jc@virginia.edu Rd = Rs1 >> SHAMT6; 40512120Sar4jc@virginia.edu }}); 40612120Sar4jc@virginia.edu 0x1: srai({{ 40712120Sar4jc@virginia.edu Rd_sd = Rs1_sd >> SHAMT6; 40812120Sar4jc@virginia.edu }}); 40912120Sar4jc@virginia.edu } 41012120Sar4jc@virginia.edu 0x6: ori({{ 41112120Sar4jc@virginia.edu Rd = Rs1 | (uint64_t)imm; 41212120Sar4jc@virginia.edu }}); 41312120Sar4jc@virginia.edu 0x7: andi({{ 41412120Sar4jc@virginia.edu Rd = Rs1 & (uint64_t)imm; 41511723Sar4jc@virginia.edu }}); 41611723Sar4jc@virginia.edu } 41712120Sar4jc@virginia.edu } 41812120Sar4jc@virginia.edu 41912120Sar4jc@virginia.edu 0x05: UOp::auipc({{ 42012120Sar4jc@virginia.edu Rd = PC + imm; 42112120Sar4jc@virginia.edu }}); 42212120Sar4jc@virginia.edu 42312120Sar4jc@virginia.edu 0x06: decode FUNCT3 { 42412120Sar4jc@virginia.edu format IOp { 42512120Sar4jc@virginia.edu 0x0: addiw({{ 42612120Sar4jc@virginia.edu Rd_sd = (int32_t)Rs1 + (int32_t)imm; 42711723Sar4jc@virginia.edu }}); 42812120Sar4jc@virginia.edu 0x1: slliw({{ 42912120Sar4jc@virginia.edu Rd_sd = Rs1_sw << SHAMT5; 43012120Sar4jc@virginia.edu }}); 43112120Sar4jc@virginia.edu 0x5: decode SRTYPE { 43212120Sar4jc@virginia.edu 0x0: srliw({{ 43312120Sar4jc@virginia.edu Rd = Rs1_uw >> SHAMT5; 43412120Sar4jc@virginia.edu }}); 43512120Sar4jc@virginia.edu 0x1: sraiw({{ 43612120Sar4jc@virginia.edu Rd_sd = Rs1_sw >> SHAMT5; 43712120Sar4jc@virginia.edu }}); 43812120Sar4jc@virginia.edu } 43912120Sar4jc@virginia.edu } 44012120Sar4jc@virginia.edu } 44111724Sar4jc@virginia.edu 44212120Sar4jc@virginia.edu 0x08: decode FUNCT3 { 44312120Sar4jc@virginia.edu format Store { 44412120Sar4jc@virginia.edu 0x0: sb({{ 44512120Sar4jc@virginia.edu Mem_ub = Rs2_ub; 44612120Sar4jc@virginia.edu }}); 44712120Sar4jc@virginia.edu 0x1: sh({{ 44812120Sar4jc@virginia.edu Mem_uh = Rs2_uh; 44912120Sar4jc@virginia.edu }}); 45012120Sar4jc@virginia.edu 0x2: sw({{ 45112120Sar4jc@virginia.edu Mem_uw = Rs2_uw; 45212120Sar4jc@virginia.edu }}); 45312120Sar4jc@virginia.edu 0x3: sd({{ 45412120Sar4jc@virginia.edu Mem_ud = Rs2_ud; 45512120Sar4jc@virginia.edu }}); 45612120Sar4jc@virginia.edu } 45712120Sar4jc@virginia.edu } 45811724Sar4jc@virginia.edu 45912120Sar4jc@virginia.edu 0x09: decode FUNCT3 { 46012120Sar4jc@virginia.edu format Store { 46112120Sar4jc@virginia.edu 0x2: fsw({{ 46212120Sar4jc@virginia.edu Mem_uw = (uint32_t)Fs2_bits; 46312120Sar4jc@virginia.edu }}); 46412120Sar4jc@virginia.edu 0x3: fsd({{ 46512120Sar4jc@virginia.edu Mem_ud = Fs2_bits; 46612120Sar4jc@virginia.edu }}); 46712120Sar4jc@virginia.edu } 46812120Sar4jc@virginia.edu } 46911724Sar4jc@virginia.edu 47012120Sar4jc@virginia.edu 0x0b: decode FUNCT3 { 47112120Sar4jc@virginia.edu 0x2: decode AMOFUNCT { 47212120Sar4jc@virginia.edu 0x2: LoadReserved::lr_w({{ 47312120Sar4jc@virginia.edu Rd_sd = Mem_sw; 47412120Sar4jc@virginia.edu }}, mem_flags=LLSC); 47512120Sar4jc@virginia.edu 0x3: StoreCond::sc_w({{ 47612120Sar4jc@virginia.edu Mem_uw = Rs2_uw; 47712120Sar4jc@virginia.edu }}, {{ 47812120Sar4jc@virginia.edu Rd = result; 47912120Sar4jc@virginia.edu }}, inst_flags=IsStoreConditional, mem_flags=LLSC); 48012120Sar4jc@virginia.edu format AtomicMemOp { 48112120Sar4jc@virginia.edu 0x0: amoadd_w({{Rt_sd = Mem_sw;}}, {{ 48212120Sar4jc@virginia.edu Mem_sw = Rs2_sw + Rt_sd; 48312120Sar4jc@virginia.edu Rd_sd = Rt_sd; 48412120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 48512120Sar4jc@virginia.edu 0x1: amoswap_w({{Rt_sd = Mem_sw;}}, {{ 48612120Sar4jc@virginia.edu Mem_sw = Rs2_uw; 48712120Sar4jc@virginia.edu Rd_sd = Rt_sd; 48812120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 48912120Sar4jc@virginia.edu 0x4: amoxor_w({{Rt_sd = Mem_sw;}}, {{ 49012120Sar4jc@virginia.edu Mem_sw = Rs2_uw^Rt_sd; 49112120Sar4jc@virginia.edu Rd_sd = Rt_sd; 49212120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 49312120Sar4jc@virginia.edu 0x8: amoor_w({{Rt_sd = Mem_sw;}}, {{ 49412120Sar4jc@virginia.edu Mem_sw = Rs2_uw | Rt_sd; 49512120Sar4jc@virginia.edu Rd_sd = Rt_sd; 49612120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 49712120Sar4jc@virginia.edu 0xc: amoand_w({{Rt_sd = Mem_sw;}}, {{ 49812120Sar4jc@virginia.edu Mem_sw = Rs2_uw&Rt_sd; 49912120Sar4jc@virginia.edu Rd_sd = Rt_sd; 50012120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 50112120Sar4jc@virginia.edu 0x10: amomin_w({{Rt_sd = Mem_sw;}}, {{ 50212120Sar4jc@virginia.edu Mem_sw = min<int32_t>(Rs2_sw, Rt_sd); 50312120Sar4jc@virginia.edu Rd_sd = Rt_sd; 50412120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 50512120Sar4jc@virginia.edu 0x14: amomax_w({{Rt_sd = Mem_sw;}}, {{ 50612120Sar4jc@virginia.edu Mem_sw = max<int32_t>(Rs2_sw, Rt_sd); 50712120Sar4jc@virginia.edu Rd_sd = Rt_sd; 50812120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 50912120Sar4jc@virginia.edu 0x18: amominu_w({{Rt_sd = Mem_sw;}}, {{ 51012120Sar4jc@virginia.edu Mem_sw = min<uint32_t>(Rs2_uw, Rt_sd); 51112120Sar4jc@virginia.edu Rd_sd = Rt_sd; 51212120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 51312120Sar4jc@virginia.edu 0x1c: amomaxu_w({{Rt_sd = Mem_sw;}}, {{ 51412120Sar4jc@virginia.edu Mem_sw = max<uint32_t>(Rs2_uw, Rt_sd); 51512120Sar4jc@virginia.edu Rd_sd = Rt_sd; 51612120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 51712120Sar4jc@virginia.edu } 51811723Sar4jc@virginia.edu } 51912120Sar4jc@virginia.edu 0x3: decode AMOFUNCT { 52012120Sar4jc@virginia.edu 0x2: LoadReserved::lr_d({{ 52112120Sar4jc@virginia.edu Rd_sd = Mem_sd; 52212120Sar4jc@virginia.edu }}, mem_flags=LLSC); 52312120Sar4jc@virginia.edu 0x3: StoreCond::sc_d({{ 52412120Sar4jc@virginia.edu Mem = Rs2; 52512120Sar4jc@virginia.edu }}, {{ 52612120Sar4jc@virginia.edu Rd = result; 52712120Sar4jc@virginia.edu }}, mem_flags=LLSC, inst_flags=IsStoreConditional); 52812120Sar4jc@virginia.edu format AtomicMemOp { 52912120Sar4jc@virginia.edu 0x0: amoadd_d({{Rt_sd = Mem_sd;}}, {{ 53012120Sar4jc@virginia.edu Mem_sd = Rs2_sd + Rt_sd; 53112120Sar4jc@virginia.edu Rd_sd = Rt_sd; 53212120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 53312120Sar4jc@virginia.edu 0x1: amoswap_d({{Rt = Mem;}}, {{ 53412120Sar4jc@virginia.edu Mem = Rs2; 53512120Sar4jc@virginia.edu Rd = Rt; 53612120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 53712120Sar4jc@virginia.edu 0x4: amoxor_d({{Rt = Mem;}}, {{ 53812120Sar4jc@virginia.edu Mem = Rs2^Rt; 53912120Sar4jc@virginia.edu Rd = Rt; 54012120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 54112120Sar4jc@virginia.edu 0x8: amoor_d({{Rt = Mem;}}, {{ 54212120Sar4jc@virginia.edu Mem = Rs2 | Rt; 54312120Sar4jc@virginia.edu Rd = Rt; 54412120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 54512120Sar4jc@virginia.edu 0xc: amoand_d({{Rt = Mem;}}, {{ 54612120Sar4jc@virginia.edu Mem = Rs2&Rt; 54712120Sar4jc@virginia.edu Rd = Rt; 54812120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 54912120Sar4jc@virginia.edu 0x10: amomin_d({{Rt_sd = Mem_sd;}}, {{ 55012120Sar4jc@virginia.edu Mem_sd = min(Rs2_sd, Rt_sd); 55112120Sar4jc@virginia.edu Rd_sd = Rt_sd; 55212120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 55312120Sar4jc@virginia.edu 0x14: amomax_d({{Rt_sd = Mem_sd;}}, {{ 55412120Sar4jc@virginia.edu Mem_sd = max(Rs2_sd, Rt_sd); 55512120Sar4jc@virginia.edu Rd_sd = Rt_sd; 55612120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 55712120Sar4jc@virginia.edu 0x18: amominu_d({{Rt = Mem;}}, {{ 55812120Sar4jc@virginia.edu Mem = min(Rs2, Rt); 55912120Sar4jc@virginia.edu Rd = Rt; 56012120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 56112120Sar4jc@virginia.edu 0x1c: amomaxu_d({{Rt = Mem;}}, {{ 56212120Sar4jc@virginia.edu Mem = max(Rs2, Rt); 56312120Sar4jc@virginia.edu Rd = Rt; 56412120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 56512120Sar4jc@virginia.edu } 56612120Sar4jc@virginia.edu } 56712120Sar4jc@virginia.edu } 56812120Sar4jc@virginia.edu 0x0c: decode FUNCT3 { 56912120Sar4jc@virginia.edu format ROp { 57012120Sar4jc@virginia.edu 0x0: decode FUNCT7 { 57112120Sar4jc@virginia.edu 0x0: add({{ 57212120Sar4jc@virginia.edu Rd = Rs1_sd + Rs2_sd; 57312120Sar4jc@virginia.edu }}); 57412120Sar4jc@virginia.edu 0x1: mul({{ 57512120Sar4jc@virginia.edu Rd = Rs1_sd*Rs2_sd; 57612120Sar4jc@virginia.edu }}, IntMultOp); 57712120Sar4jc@virginia.edu 0x20: sub({{ 57812120Sar4jc@virginia.edu Rd = Rs1_sd - Rs2_sd; 57912120Sar4jc@virginia.edu }}); 58012120Sar4jc@virginia.edu } 58112120Sar4jc@virginia.edu 0x1: decode FUNCT7 { 58212120Sar4jc@virginia.edu 0x0: sll({{ 58312120Sar4jc@virginia.edu Rd = Rs1 << Rs2<5:0>; 58412120Sar4jc@virginia.edu }}); 58512120Sar4jc@virginia.edu 0x1: mulh({{ 58612120Sar4jc@virginia.edu bool negate = (Rs1_sd < 0) != (Rs2_sd < 0); 58712120Sar4jc@virginia.edu 58812120Sar4jc@virginia.edu uint64_t Rs1_lo = (uint32_t)abs(Rs1_sd); 58912120Sar4jc@virginia.edu uint64_t Rs1_hi = (uint64_t)abs(Rs1_sd) >> 32; 59012120Sar4jc@virginia.edu uint64_t Rs2_lo = (uint32_t)abs(Rs2_sd); 59112120Sar4jc@virginia.edu uint64_t Rs2_hi = (uint64_t)abs(Rs2_sd) >> 32; 59212120Sar4jc@virginia.edu 59312120Sar4jc@virginia.edu uint64_t hi = Rs1_hi*Rs2_hi; 59412120Sar4jc@virginia.edu uint64_t mid1 = Rs1_hi*Rs2_lo; 59512120Sar4jc@virginia.edu uint64_t mid2 = Rs1_lo*Rs2_hi; 59612120Sar4jc@virginia.edu uint64_t lo = Rs2_lo*Rs1_lo; 59712120Sar4jc@virginia.edu uint64_t carry = ((uint64_t)(uint32_t)mid1 59812120Sar4jc@virginia.edu + (uint64_t)(uint32_t)mid2 + (lo >> 32)) >> 32; 59912120Sar4jc@virginia.edu 60012120Sar4jc@virginia.edu uint64_t res = hi + 60112120Sar4jc@virginia.edu (mid1 >> 32) + 60212120Sar4jc@virginia.edu (mid2 >> 32) + 60312120Sar4jc@virginia.edu carry; 60412120Sar4jc@virginia.edu Rd = negate ? ~res + (Rs1_sd*Rs2_sd == 0 ? 1 : 0) 60512120Sar4jc@virginia.edu : res; 60612120Sar4jc@virginia.edu }}, IntMultOp); 60712120Sar4jc@virginia.edu } 60812120Sar4jc@virginia.edu 0x2: decode FUNCT7 { 60912120Sar4jc@virginia.edu 0x0: slt({{ 61012120Sar4jc@virginia.edu Rd = (Rs1_sd < Rs2_sd) ? 1 : 0; 61112120Sar4jc@virginia.edu }}); 61212120Sar4jc@virginia.edu 0x1: mulhsu({{ 61312120Sar4jc@virginia.edu bool negate = Rs1_sd < 0; 61412120Sar4jc@virginia.edu uint64_t Rs1_lo = (uint32_t)abs(Rs1_sd); 61512120Sar4jc@virginia.edu uint64_t Rs1_hi = (uint64_t)abs(Rs1_sd) >> 32; 61612120Sar4jc@virginia.edu uint64_t Rs2_lo = (uint32_t)Rs2; 61712120Sar4jc@virginia.edu uint64_t Rs2_hi = Rs2 >> 32; 61812120Sar4jc@virginia.edu 61912120Sar4jc@virginia.edu uint64_t hi = Rs1_hi*Rs2_hi; 62012120Sar4jc@virginia.edu uint64_t mid1 = Rs1_hi*Rs2_lo; 62112120Sar4jc@virginia.edu uint64_t mid2 = Rs1_lo*Rs2_hi; 62212120Sar4jc@virginia.edu uint64_t lo = Rs1_lo*Rs2_lo; 62312120Sar4jc@virginia.edu uint64_t carry = ((uint64_t)(uint32_t)mid1 62412120Sar4jc@virginia.edu + (uint64_t)(uint32_t)mid2 + (lo >> 32)) >> 32; 62512120Sar4jc@virginia.edu 62612120Sar4jc@virginia.edu uint64_t res = hi + 62712120Sar4jc@virginia.edu (mid1 >> 32) + 62812120Sar4jc@virginia.edu (mid2 >> 32) + 62912120Sar4jc@virginia.edu carry; 63012120Sar4jc@virginia.edu Rd = negate ? ~res + (Rs1_sd*Rs2 == 0 ? 1 : 0) : res; 63112120Sar4jc@virginia.edu }}, IntMultOp); 63212120Sar4jc@virginia.edu } 63312120Sar4jc@virginia.edu 0x3: decode FUNCT7 { 63412120Sar4jc@virginia.edu 0x0: sltu({{ 63512120Sar4jc@virginia.edu Rd = (Rs1 < Rs2) ? 1 : 0; 63612120Sar4jc@virginia.edu }}); 63712120Sar4jc@virginia.edu 0x1: mulhu({{ 63812120Sar4jc@virginia.edu uint64_t Rs1_lo = (uint32_t)Rs1; 63912120Sar4jc@virginia.edu uint64_t Rs1_hi = Rs1 >> 32; 64012120Sar4jc@virginia.edu uint64_t Rs2_lo = (uint32_t)Rs2; 64112120Sar4jc@virginia.edu uint64_t Rs2_hi = Rs2 >> 32; 64212120Sar4jc@virginia.edu 64312120Sar4jc@virginia.edu uint64_t hi = Rs1_hi*Rs2_hi; 64412120Sar4jc@virginia.edu uint64_t mid1 = Rs1_hi*Rs2_lo; 64512120Sar4jc@virginia.edu uint64_t mid2 = Rs1_lo*Rs2_hi; 64612120Sar4jc@virginia.edu uint64_t lo = Rs1_lo*Rs2_lo; 64712120Sar4jc@virginia.edu uint64_t carry = ((uint64_t)(uint32_t)mid1 64812120Sar4jc@virginia.edu + (uint64_t)(uint32_t)mid2 + (lo >> 32)) >> 32; 64912120Sar4jc@virginia.edu 65012120Sar4jc@virginia.edu Rd = hi + (mid1 >> 32) + (mid2 >> 32) + carry; 65112120Sar4jc@virginia.edu }}, IntMultOp); 65212120Sar4jc@virginia.edu } 65312120Sar4jc@virginia.edu 0x4: decode FUNCT7 { 65412120Sar4jc@virginia.edu 0x0: xor({{ 65512120Sar4jc@virginia.edu Rd = Rs1 ^ Rs2; 65612120Sar4jc@virginia.edu }}); 65712120Sar4jc@virginia.edu 0x1: div({{ 65812120Sar4jc@virginia.edu if (Rs2_sd == 0) { 65912120Sar4jc@virginia.edu Rd_sd = -1; 66012120Sar4jc@virginia.edu } else if (Rs1_sd == numeric_limits<int64_t>::min() 66112120Sar4jc@virginia.edu && Rs2_sd == -1) { 66212120Sar4jc@virginia.edu Rd_sd = numeric_limits<int64_t>::min(); 66312120Sar4jc@virginia.edu } else { 66412120Sar4jc@virginia.edu Rd_sd = Rs1_sd/Rs2_sd; 66512120Sar4jc@virginia.edu } 66612120Sar4jc@virginia.edu }}, IntDivOp); 66712120Sar4jc@virginia.edu } 66812120Sar4jc@virginia.edu 0x5: decode FUNCT7 { 66912120Sar4jc@virginia.edu 0x0: srl({{ 67012120Sar4jc@virginia.edu Rd = Rs1 >> Rs2<5:0>; 67112120Sar4jc@virginia.edu }}); 67212120Sar4jc@virginia.edu 0x1: divu({{ 67312120Sar4jc@virginia.edu if (Rs2 == 0) { 67412120Sar4jc@virginia.edu Rd = numeric_limits<uint64_t>::max(); 67512120Sar4jc@virginia.edu } else { 67612120Sar4jc@virginia.edu Rd = Rs1/Rs2; 67712120Sar4jc@virginia.edu } 67812120Sar4jc@virginia.edu }}, IntDivOp); 67912120Sar4jc@virginia.edu 0x20: sra({{ 68012120Sar4jc@virginia.edu Rd_sd = Rs1_sd >> Rs2<5:0>; 68112120Sar4jc@virginia.edu }}); 68212120Sar4jc@virginia.edu } 68312120Sar4jc@virginia.edu 0x6: decode FUNCT7 { 68412120Sar4jc@virginia.edu 0x0: or({{ 68512120Sar4jc@virginia.edu Rd = Rs1 | Rs2; 68612120Sar4jc@virginia.edu }}); 68712120Sar4jc@virginia.edu 0x1: rem({{ 68812120Sar4jc@virginia.edu if (Rs2_sd == 0) { 68912120Sar4jc@virginia.edu Rd = Rs1_sd; 69012120Sar4jc@virginia.edu } else if (Rs1_sd == numeric_limits<int64_t>::min() 69112120Sar4jc@virginia.edu && Rs2_sd == -1) { 69212120Sar4jc@virginia.edu Rd = 0; 69312120Sar4jc@virginia.edu } else { 69412120Sar4jc@virginia.edu Rd = Rs1_sd%Rs2_sd; 69512120Sar4jc@virginia.edu } 69612120Sar4jc@virginia.edu }}, IntDivOp); 69712120Sar4jc@virginia.edu } 69812120Sar4jc@virginia.edu 0x7: decode FUNCT7 { 69912120Sar4jc@virginia.edu 0x0: and({{ 70012120Sar4jc@virginia.edu Rd = Rs1 & Rs2; 70112120Sar4jc@virginia.edu }}); 70212120Sar4jc@virginia.edu 0x1: remu({{ 70312120Sar4jc@virginia.edu if (Rs2 == 0) { 70412120Sar4jc@virginia.edu Rd = Rs1; 70512120Sar4jc@virginia.edu } else { 70612120Sar4jc@virginia.edu Rd = Rs1%Rs2; 70712120Sar4jc@virginia.edu } 70812120Sar4jc@virginia.edu }}, IntDivOp); 70912120Sar4jc@virginia.edu } 71012120Sar4jc@virginia.edu } 71112120Sar4jc@virginia.edu } 71212120Sar4jc@virginia.edu 71312120Sar4jc@virginia.edu 0x0d: UOp::lui({{ 71412120Sar4jc@virginia.edu Rd = (uint64_t)imm; 71512120Sar4jc@virginia.edu }}); 71612120Sar4jc@virginia.edu 71712120Sar4jc@virginia.edu 0x0e: decode FUNCT3 { 71812120Sar4jc@virginia.edu format ROp { 71912120Sar4jc@virginia.edu 0x0: decode FUNCT7 { 72012120Sar4jc@virginia.edu 0x0: addw({{ 72112120Sar4jc@virginia.edu Rd_sd = Rs1_sw + Rs2_sw; 72212120Sar4jc@virginia.edu }}); 72312120Sar4jc@virginia.edu 0x1: mulw({{ 72412120Sar4jc@virginia.edu Rd_sd = (int32_t)(Rs1_sw*Rs2_sw); 72512120Sar4jc@virginia.edu }}, IntMultOp); 72612120Sar4jc@virginia.edu 0x20: subw({{ 72712120Sar4jc@virginia.edu Rd_sd = Rs1_sw - Rs2_sw; 72812120Sar4jc@virginia.edu }}); 72912120Sar4jc@virginia.edu } 73012120Sar4jc@virginia.edu 0x1: sllw({{ 73112120Sar4jc@virginia.edu Rd_sd = Rs1_sw << Rs2<4:0>; 73211723Sar4jc@virginia.edu }}); 73312120Sar4jc@virginia.edu 0x4: divw({{ 73412120Sar4jc@virginia.edu if (Rs2_sw == 0) { 73511724Sar4jc@virginia.edu Rd_sd = -1; 73612120Sar4jc@virginia.edu } else if (Rs1_sw == numeric_limits<int32_t>::min() 73712120Sar4jc@virginia.edu && Rs2_sw == -1) { 73812120Sar4jc@virginia.edu Rd_sd = numeric_limits<int32_t>::min(); 73911724Sar4jc@virginia.edu } else { 74012120Sar4jc@virginia.edu Rd_sd = Rs1_sw/Rs2_sw; 74111724Sar4jc@virginia.edu } 74211724Sar4jc@virginia.edu }}, IntDivOp); 74312120Sar4jc@virginia.edu 0x5: decode FUNCT7 { 74412120Sar4jc@virginia.edu 0x0: srlw({{ 74512120Sar4jc@virginia.edu Rd_uw = Rs1_uw >> Rs2<4:0>; 74612120Sar4jc@virginia.edu }}); 74712120Sar4jc@virginia.edu 0x1: divuw({{ 74812120Sar4jc@virginia.edu if (Rs2_uw == 0) { 74912120Sar4jc@virginia.edu Rd_sd = numeric_limits<IntReg>::max(); 75012120Sar4jc@virginia.edu } else { 75112120Sar4jc@virginia.edu Rd_sd = (int32_t)(Rs1_uw/Rs2_uw); 75212120Sar4jc@virginia.edu } 75312120Sar4jc@virginia.edu }}, IntDivOp); 75412120Sar4jc@virginia.edu 0x20: sraw({{ 75512120Sar4jc@virginia.edu Rd_sd = Rs1_sw >> Rs2<4:0>; 75612120Sar4jc@virginia.edu }}); 75712120Sar4jc@virginia.edu } 75812120Sar4jc@virginia.edu 0x6: remw({{ 75912120Sar4jc@virginia.edu if (Rs2_sw == 0) { 76012120Sar4jc@virginia.edu Rd_sd = Rs1_sw; 76112120Sar4jc@virginia.edu } else if (Rs1_sw == numeric_limits<int32_t>::min() 76212120Sar4jc@virginia.edu && Rs2_sw == -1) { 76312120Sar4jc@virginia.edu Rd_sd = 0; 76411724Sar4jc@virginia.edu } else { 76512120Sar4jc@virginia.edu Rd_sd = Rs1_sw%Rs2_sw; 76611724Sar4jc@virginia.edu } 76711724Sar4jc@virginia.edu }}, IntDivOp); 76812120Sar4jc@virginia.edu 0x7: remuw({{ 76912120Sar4jc@virginia.edu if (Rs2_uw == 0) { 77012120Sar4jc@virginia.edu Rd_sd = (int32_t)Rs1_uw; 77111724Sar4jc@virginia.edu } else { 77212120Sar4jc@virginia.edu Rd_sd = (int32_t)(Rs1_uw%Rs2_uw); 77311724Sar4jc@virginia.edu } 77411724Sar4jc@virginia.edu }}, IntDivOp); 77511723Sar4jc@virginia.edu } 77611723Sar4jc@virginia.edu } 77711723Sar4jc@virginia.edu 77812120Sar4jc@virginia.edu format FPROp { 77912120Sar4jc@virginia.edu 0x10: decode FUNCT2 { 78012120Sar4jc@virginia.edu 0x0: fmadd_s({{ 78112120Sar4jc@virginia.edu uint32_t temp; 78212120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 78312120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 78412120Sar4jc@virginia.edu float fs3 = reinterpret_cast<float&>(temp = Fs3_bits); 78512120Sar4jc@virginia.edu float fd; 78611723Sar4jc@virginia.edu 78712120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2) || isnan(fs3)) { 78812120Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2) 78912120Sar4jc@virginia.edu || issignalingnan(fs3)) { 79012120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 79112120Sar4jc@virginia.edu } 79212120Sar4jc@virginia.edu fd = numeric_limits<float>::quiet_NaN(); 79312120Sar4jc@virginia.edu } else if (isinf(fs1) || isinf(fs2) || 79412120Sar4jc@virginia.edu isinf(fs3)) { 79512120Sar4jc@virginia.edu if (signbit(fs1) == signbit(fs2) 79612120Sar4jc@virginia.edu && !isinf(fs3)) { 79712120Sar4jc@virginia.edu fd = numeric_limits<float>::infinity(); 79812120Sar4jc@virginia.edu } else if (signbit(fs1) != signbit(fs2) 79912120Sar4jc@virginia.edu && !isinf(fs3)) { 80012120Sar4jc@virginia.edu fd = -numeric_limits<float>::infinity(); 80112120Sar4jc@virginia.edu } else { // Fs3_sf is infinity 80212120Sar4jc@virginia.edu fd = fs3; 80312120Sar4jc@virginia.edu } 80412120Sar4jc@virginia.edu } else { 80512120Sar4jc@virginia.edu fd = fs1*fs2 + fs3; 80612120Sar4jc@virginia.edu } 80712120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 80812120Sar4jc@virginia.edu }}, FloatMultOp); 80912120Sar4jc@virginia.edu 0x1: fmadd_d({{ 81012120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2) || isnan(Fs3)) { 81112120Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2) 81212120Sar4jc@virginia.edu || issignalingnan(Fs3)) { 81312120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 81412120Sar4jc@virginia.edu } 81512120Sar4jc@virginia.edu Fd = numeric_limits<double>::quiet_NaN(); 81612120Sar4jc@virginia.edu } else if (isinf(Fs1) || isinf(Fs2) || 81712120Sar4jc@virginia.edu isinf(Fs3)) { 81812120Sar4jc@virginia.edu if (signbit(Fs1) == signbit(Fs2) 81912120Sar4jc@virginia.edu && !isinf(Fs3)) { 82012120Sar4jc@virginia.edu Fd = numeric_limits<double>::infinity(); 82112120Sar4jc@virginia.edu } else if (signbit(Fs1) != signbit(Fs2) 82212120Sar4jc@virginia.edu && !isinf(Fs3)) { 82312120Sar4jc@virginia.edu Fd = -numeric_limits<double>::infinity(); 82412120Sar4jc@virginia.edu } else { 82512120Sar4jc@virginia.edu Fd = Fs3; 82612120Sar4jc@virginia.edu } 82712120Sar4jc@virginia.edu } else { 82812120Sar4jc@virginia.edu Fd = Fs1*Fs2 + Fs3; 82912120Sar4jc@virginia.edu } 83012120Sar4jc@virginia.edu }}, FloatMultOp); 83111723Sar4jc@virginia.edu } 83212120Sar4jc@virginia.edu 0x11: decode FUNCT2 { 83312120Sar4jc@virginia.edu 0x0: fmsub_s({{ 83412120Sar4jc@virginia.edu uint32_t temp; 83512120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 83612120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 83712120Sar4jc@virginia.edu float fs3 = reinterpret_cast<float&>(temp = Fs3_bits); 83812120Sar4jc@virginia.edu float fd; 83912120Sar4jc@virginia.edu 84012120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2) || isnan(fs3)) { 84112120Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2) 84212120Sar4jc@virginia.edu || issignalingnan(fs3)) { 84312120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 84412120Sar4jc@virginia.edu } 84512120Sar4jc@virginia.edu fd = numeric_limits<float>::quiet_NaN(); 84612120Sar4jc@virginia.edu } else if (isinf(fs1) || isinf(fs2) || 84712120Sar4jc@virginia.edu isinf(fs3)) { 84812120Sar4jc@virginia.edu if (signbit(fs1) == signbit(fs2) 84912120Sar4jc@virginia.edu && !isinf(fs3)) { 85012120Sar4jc@virginia.edu fd = numeric_limits<float>::infinity(); 85112120Sar4jc@virginia.edu } else if (signbit(fs1) != signbit(fs2) 85212120Sar4jc@virginia.edu && !isinf(fs3)) { 85312120Sar4jc@virginia.edu fd = -numeric_limits<float>::infinity(); 85412120Sar4jc@virginia.edu } else { // Fs3_sf is infinity 85512120Sar4jc@virginia.edu fd = -fs3; 85612120Sar4jc@virginia.edu } 85711724Sar4jc@virginia.edu } else { 85812120Sar4jc@virginia.edu fd = fs1*fs2 - fs3; 85911724Sar4jc@virginia.edu } 86012120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 86112120Sar4jc@virginia.edu }}, FloatMultOp); 86212120Sar4jc@virginia.edu 0x1: fmsub_d({{ 86312120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2) || isnan(Fs3)) { 86412120Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2) 86512120Sar4jc@virginia.edu || issignalingnan(Fs3)) { 86612120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 86712120Sar4jc@virginia.edu } 86812120Sar4jc@virginia.edu Fd = numeric_limits<double>::quiet_NaN(); 86912120Sar4jc@virginia.edu } else if (isinf(Fs1) || isinf(Fs2) || 87012120Sar4jc@virginia.edu isinf(Fs3)) { 87112120Sar4jc@virginia.edu if (signbit(Fs1) == signbit(Fs2) 87212120Sar4jc@virginia.edu && !isinf(Fs3)) { 87312120Sar4jc@virginia.edu Fd = numeric_limits<double>::infinity(); 87412120Sar4jc@virginia.edu } else if (signbit(Fs1) != signbit(Fs2) 87512120Sar4jc@virginia.edu && !isinf(Fs3)) { 87612120Sar4jc@virginia.edu Fd = -numeric_limits<double>::infinity(); 87712120Sar4jc@virginia.edu } else { 87812120Sar4jc@virginia.edu Fd = -Fs3; 87912120Sar4jc@virginia.edu } 88012120Sar4jc@virginia.edu } else { 88112120Sar4jc@virginia.edu Fd = Fs1*Fs2 - Fs3; 88212120Sar4jc@virginia.edu } 88312120Sar4jc@virginia.edu }}, FloatMultOp); 88411723Sar4jc@virginia.edu } 88512120Sar4jc@virginia.edu 0x12: decode FUNCT2 { 88612120Sar4jc@virginia.edu 0x0: fnmsub_s({{ 88712120Sar4jc@virginia.edu uint32_t temp; 88812120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 88912120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 89012120Sar4jc@virginia.edu float fs3 = reinterpret_cast<float&>(temp = Fs3_bits); 89112120Sar4jc@virginia.edu float fd; 89211723Sar4jc@virginia.edu 89312120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2) || isnan(fs3)) { 89412120Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2) 89512120Sar4jc@virginia.edu || issignalingnan(fs3)) { 89612120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 89712120Sar4jc@virginia.edu } 89812120Sar4jc@virginia.edu fd = numeric_limits<float>::quiet_NaN(); 89912120Sar4jc@virginia.edu } else if (isinf(fs1) || isinf(fs2) || 90012120Sar4jc@virginia.edu isinf(fs3)) { 90112120Sar4jc@virginia.edu if (signbit(fs1) == signbit(fs2) 90212120Sar4jc@virginia.edu && !isinf(fs3)) { 90312120Sar4jc@virginia.edu fd = -numeric_limits<float>::infinity(); 90412120Sar4jc@virginia.edu } else if (signbit(fs1) != signbit(fs2) 90512120Sar4jc@virginia.edu && !isinf(fs3)) { 90612120Sar4jc@virginia.edu fd = numeric_limits<float>::infinity(); 90712120Sar4jc@virginia.edu } else { // Fs3_sf is infinity 90812120Sar4jc@virginia.edu fd = fs3; 90912120Sar4jc@virginia.edu } 91012120Sar4jc@virginia.edu } else { 91112120Sar4jc@virginia.edu fd = -(fs1*fs2 - fs3); 91212120Sar4jc@virginia.edu } 91312120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 91412120Sar4jc@virginia.edu }}, FloatMultOp); 91512120Sar4jc@virginia.edu 0x1: fnmsub_d({{ 91612120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2) || isnan(Fs3)) { 91712120Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2) 91812120Sar4jc@virginia.edu || issignalingnan(Fs3)) { 91912120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 92012120Sar4jc@virginia.edu } 92112120Sar4jc@virginia.edu Fd = numeric_limits<double>::quiet_NaN(); 92212120Sar4jc@virginia.edu } else if (isinf(Fs1) || isinf(Fs2) 92312120Sar4jc@virginia.edu || isinf(Fs3)) { 92412120Sar4jc@virginia.edu if (signbit(Fs1) == signbit(Fs2) 92512120Sar4jc@virginia.edu && !isinf(Fs3)) { 92612120Sar4jc@virginia.edu Fd = -numeric_limits<double>::infinity(); 92712120Sar4jc@virginia.edu } else if (signbit(Fs1) != signbit(Fs2) 92812120Sar4jc@virginia.edu && !isinf(Fs3)) { 92912120Sar4jc@virginia.edu Fd = numeric_limits<double>::infinity(); 93012120Sar4jc@virginia.edu } else { 93112120Sar4jc@virginia.edu Fd = Fs3; 93212120Sar4jc@virginia.edu } 93312120Sar4jc@virginia.edu } else { 93412120Sar4jc@virginia.edu Fd = -(Fs1*Fs2 - Fs3); 93512120Sar4jc@virginia.edu } 93612120Sar4jc@virginia.edu }}, FloatMultOp); 93712120Sar4jc@virginia.edu } 93812120Sar4jc@virginia.edu 0x13: decode FUNCT2 { 93912120Sar4jc@virginia.edu 0x0: fnmadd_s({{ 94012120Sar4jc@virginia.edu uint32_t temp; 94112120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 94212120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 94312120Sar4jc@virginia.edu float fs3 = reinterpret_cast<float&>(temp = Fs3_bits); 94412120Sar4jc@virginia.edu float fd; 94511725Sar4jc@virginia.edu 94612120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2) || isnan(fs3)) { 94712120Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2) 94812120Sar4jc@virginia.edu || issignalingnan(fs3)) { 94912120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 95012120Sar4jc@virginia.edu } 95112120Sar4jc@virginia.edu fd = numeric_limits<float>::quiet_NaN(); 95212120Sar4jc@virginia.edu } else if (isinf(fs1) || isinf(fs2) || 95312120Sar4jc@virginia.edu isinf(fs3)) { 95412120Sar4jc@virginia.edu if (signbit(fs1) == signbit(fs2) 95512120Sar4jc@virginia.edu && !isinf(fs3)) { 95612120Sar4jc@virginia.edu fd = -numeric_limits<float>::infinity(); 95712120Sar4jc@virginia.edu } else if (signbit(fs1) != signbit(fs2) 95812120Sar4jc@virginia.edu && !isinf(fs3)) { 95912120Sar4jc@virginia.edu fd = numeric_limits<float>::infinity(); 96012120Sar4jc@virginia.edu } else { // Fs3_sf is infinity 96112120Sar4jc@virginia.edu fd = -fs3; 96212120Sar4jc@virginia.edu } 96312120Sar4jc@virginia.edu } else { 96412120Sar4jc@virginia.edu fd = -(fs1*fs2 + fs3); 96511725Sar4jc@virginia.edu } 96612120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 96712120Sar4jc@virginia.edu }}, FloatMultOp); 96812120Sar4jc@virginia.edu 0x1: fnmadd_d({{ 96912120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2) || isnan(Fs3)) { 97012120Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2) 97112120Sar4jc@virginia.edu || issignalingnan(Fs3)) { 97212120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 97312120Sar4jc@virginia.edu } 97412120Sar4jc@virginia.edu Fd = numeric_limits<double>::quiet_NaN(); 97512120Sar4jc@virginia.edu } else if (isinf(Fs1) || isinf(Fs2) || 97612120Sar4jc@virginia.edu isinf(Fs3)) { 97712120Sar4jc@virginia.edu if (signbit(Fs1) == signbit(Fs2) 97812120Sar4jc@virginia.edu && !isinf(Fs3)) { 97912120Sar4jc@virginia.edu Fd = -numeric_limits<double>::infinity(); 98012120Sar4jc@virginia.edu } else if (signbit(Fs1) != signbit(Fs2) 98112120Sar4jc@virginia.edu && !isinf(Fs3)) { 98212120Sar4jc@virginia.edu Fd = numeric_limits<double>::infinity(); 98312120Sar4jc@virginia.edu } else { 98412120Sar4jc@virginia.edu Fd = -Fs3; 98512120Sar4jc@virginia.edu } 98612120Sar4jc@virginia.edu } else { 98712120Sar4jc@virginia.edu Fd = -(Fs1*Fs2 + Fs3); 98811725Sar4jc@virginia.edu } 98912120Sar4jc@virginia.edu }}, FloatMultOp); 99012120Sar4jc@virginia.edu } 99112120Sar4jc@virginia.edu 0x14: decode FUNCT7 { 99212120Sar4jc@virginia.edu 0x0: fadd_s({{ 99311725Sar4jc@virginia.edu uint32_t temp; 99411725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 99511725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 99611725Sar4jc@virginia.edu float fd; 99711725Sar4jc@virginia.edu 99812120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2)) { 99912120Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2)) { 100012120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 100112120Sar4jc@virginia.edu } 100212120Sar4jc@virginia.edu fd = numeric_limits<float>::quiet_NaN(); 100311725Sar4jc@virginia.edu } else { 100412120Sar4jc@virginia.edu fd = fs1 + fs2; 100511725Sar4jc@virginia.edu } 100611725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 100712120Sar4jc@virginia.edu }}, FloatAddOp); 100812120Sar4jc@virginia.edu 0x1: fadd_d({{ 100912120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2)) { 101012120Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2)) { 101112120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 101212120Sar4jc@virginia.edu } 101312120Sar4jc@virginia.edu Fd = numeric_limits<double>::quiet_NaN(); 101412120Sar4jc@virginia.edu } else { 101512120Sar4jc@virginia.edu Fd = Fs1 + Fs2; 101612120Sar4jc@virginia.edu } 101712120Sar4jc@virginia.edu }}, FloatAddOp); 101812120Sar4jc@virginia.edu 0x4: fsub_s({{ 101911725Sar4jc@virginia.edu uint32_t temp; 102011725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 102111725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 102211725Sar4jc@virginia.edu float fd; 102311725Sar4jc@virginia.edu 102412120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2)) { 102512120Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2)) { 102612120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 102712120Sar4jc@virginia.edu } 102812120Sar4jc@virginia.edu fd = numeric_limits<float>::quiet_NaN(); 102911725Sar4jc@virginia.edu } else { 103012120Sar4jc@virginia.edu fd = fs1 - fs2; 103111725Sar4jc@virginia.edu } 103211725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 103312120Sar4jc@virginia.edu }}, FloatAddOp); 103412120Sar4jc@virginia.edu 0x5: fsub_d({{ 103512120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2)) { 103612120Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2)) { 103712120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 103812120Sar4jc@virginia.edu } 103912120Sar4jc@virginia.edu Fd = numeric_limits<double>::quiet_NaN(); 104012120Sar4jc@virginia.edu } else { 104112120Sar4jc@virginia.edu Fd = Fs1 - Fs2; 104212120Sar4jc@virginia.edu } 104312120Sar4jc@virginia.edu }}, FloatAddOp); 104412120Sar4jc@virginia.edu 0x8: fmul_s({{ 104511725Sar4jc@virginia.edu uint32_t temp; 104611725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 104711725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 104811725Sar4jc@virginia.edu float fd; 104911725Sar4jc@virginia.edu 105012120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2)) { 105112120Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2)) { 105212120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 105312120Sar4jc@virginia.edu } 105412120Sar4jc@virginia.edu fd = numeric_limits<float>::quiet_NaN(); 105511725Sar4jc@virginia.edu } else { 105612120Sar4jc@virginia.edu fd = fs1*fs2; 105711725Sar4jc@virginia.edu } 105811725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 105912120Sar4jc@virginia.edu }}, FloatMultOp); 106012120Sar4jc@virginia.edu 0x9: fmul_d({{ 106112120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2)) { 106212120Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2)) { 106312120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 106412120Sar4jc@virginia.edu } 106512120Sar4jc@virginia.edu Fd = numeric_limits<double>::quiet_NaN(); 106611725Sar4jc@virginia.edu } else { 106712120Sar4jc@virginia.edu Fd = Fs1*Fs2; 106811725Sar4jc@virginia.edu } 106912120Sar4jc@virginia.edu }}, FloatMultOp); 107012120Sar4jc@virginia.edu 0xc: fdiv_s({{ 107111725Sar4jc@virginia.edu uint32_t temp; 107211725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 107311725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 107411725Sar4jc@virginia.edu float fd; 107511725Sar4jc@virginia.edu 107612120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2)) { 107712120Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2)) { 107812120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 107912120Sar4jc@virginia.edu } 108012120Sar4jc@virginia.edu fd = numeric_limits<float>::quiet_NaN(); 108112120Sar4jc@virginia.edu } else { 108212120Sar4jc@virginia.edu fd = fs1/fs2; 108312120Sar4jc@virginia.edu } 108412120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 108512120Sar4jc@virginia.edu }}, FloatDivOp); 108612120Sar4jc@virginia.edu 0xd: fdiv_d({{ 108712120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2)) { 108812120Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2)) { 108912120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 109012120Sar4jc@virginia.edu } 109112120Sar4jc@virginia.edu Fd = numeric_limits<double>::quiet_NaN(); 109212120Sar4jc@virginia.edu } else { 109312120Sar4jc@virginia.edu Fd = Fs1/Fs2; 109412120Sar4jc@virginia.edu } 109512120Sar4jc@virginia.edu }}, FloatDivOp); 109612120Sar4jc@virginia.edu 0x10: decode ROUND_MODE { 109712120Sar4jc@virginia.edu 0x0: fsgnj_s({{ 109812120Sar4jc@virginia.edu uint32_t temp; 109912120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 110012120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 110112120Sar4jc@virginia.edu float fd; 110212120Sar4jc@virginia.edu 110312120Sar4jc@virginia.edu if (issignalingnan(fs1)) { 110412120Sar4jc@virginia.edu fd = numeric_limits<float>::signaling_NaN(); 110512120Sar4jc@virginia.edu feclearexcept(FE_INVALID); 110612120Sar4jc@virginia.edu } else { 110712120Sar4jc@virginia.edu fd = copysign(fs1, fs2); 110812120Sar4jc@virginia.edu } 110912120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 111012120Sar4jc@virginia.edu }}); 111112120Sar4jc@virginia.edu 0x1: fsgnjn_s({{ 111212120Sar4jc@virginia.edu uint32_t temp; 111312120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 111412120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 111512120Sar4jc@virginia.edu float fd; 111612120Sar4jc@virginia.edu 111712120Sar4jc@virginia.edu if (issignalingnan(fs1)) { 111812120Sar4jc@virginia.edu fd = numeric_limits<float>::signaling_NaN(); 111912120Sar4jc@virginia.edu feclearexcept(FE_INVALID); 112012120Sar4jc@virginia.edu } else { 112112120Sar4jc@virginia.edu fd = copysign(fs1, -fs2); 112212120Sar4jc@virginia.edu } 112312120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 112412120Sar4jc@virginia.edu }}); 112512120Sar4jc@virginia.edu 0x2: fsgnjx_s({{ 112612120Sar4jc@virginia.edu uint32_t temp; 112712120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 112812120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 112912120Sar4jc@virginia.edu float fd; 113012120Sar4jc@virginia.edu 113112120Sar4jc@virginia.edu if (issignalingnan(fs1)) { 113212120Sar4jc@virginia.edu fd = numeric_limits<float>::signaling_NaN(); 113312120Sar4jc@virginia.edu feclearexcept(FE_INVALID); 113412120Sar4jc@virginia.edu } else { 113512120Sar4jc@virginia.edu fd = fs1*(signbit(fs2) ? -1.0 : 1.0); 113612120Sar4jc@virginia.edu } 113712120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 113812120Sar4jc@virginia.edu }}); 113912120Sar4jc@virginia.edu } 114012120Sar4jc@virginia.edu 0x11: decode ROUND_MODE { 114112120Sar4jc@virginia.edu 0x0: fsgnj_d({{ 114212120Sar4jc@virginia.edu if (issignalingnan(Fs1)) { 114312120Sar4jc@virginia.edu Fd = numeric_limits<double>::signaling_NaN(); 114412120Sar4jc@virginia.edu feclearexcept(FE_INVALID); 114512120Sar4jc@virginia.edu } else { 114612120Sar4jc@virginia.edu Fd = copysign(Fs1, Fs2); 114712120Sar4jc@virginia.edu } 114812120Sar4jc@virginia.edu }}); 114912120Sar4jc@virginia.edu 0x1: fsgnjn_d({{ 115012120Sar4jc@virginia.edu if (issignalingnan(Fs1)) { 115112120Sar4jc@virginia.edu Fd = numeric_limits<double>::signaling_NaN(); 115212120Sar4jc@virginia.edu feclearexcept(FE_INVALID); 115312120Sar4jc@virginia.edu } else { 115412120Sar4jc@virginia.edu Fd = copysign(Fs1, -Fs2); 115512120Sar4jc@virginia.edu } 115612120Sar4jc@virginia.edu }}); 115712120Sar4jc@virginia.edu 0x2: fsgnjx_d({{ 115812120Sar4jc@virginia.edu if (issignalingnan(Fs1)) { 115912120Sar4jc@virginia.edu Fd = numeric_limits<double>::signaling_NaN(); 116012120Sar4jc@virginia.edu feclearexcept(FE_INVALID); 116112120Sar4jc@virginia.edu } else { 116212120Sar4jc@virginia.edu Fd = Fs1*(signbit(Fs2) ? -1.0 : 1.0); 116312120Sar4jc@virginia.edu } 116412120Sar4jc@virginia.edu }}); 116512120Sar4jc@virginia.edu } 116612120Sar4jc@virginia.edu 0x14: decode ROUND_MODE { 116712120Sar4jc@virginia.edu 0x0: fmin_s({{ 116812120Sar4jc@virginia.edu uint32_t temp; 116912120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 117012120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 117112120Sar4jc@virginia.edu float fd; 117212120Sar4jc@virginia.edu 117312120Sar4jc@virginia.edu if (issignalingnan(fs2)) { 117412120Sar4jc@virginia.edu fd = fs1; 117512120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 117612120Sar4jc@virginia.edu } else if (issignalingnan(fs1)) { 117712120Sar4jc@virginia.edu fd = fs2; 117812120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 117912120Sar4jc@virginia.edu } else { 118012120Sar4jc@virginia.edu fd = fmin(fs1, fs2); 118112120Sar4jc@virginia.edu } 118212120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 118312120Sar4jc@virginia.edu }}, FloatCmpOp); 118412120Sar4jc@virginia.edu 0x1: fmax_s({{ 118512120Sar4jc@virginia.edu uint32_t temp; 118612120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 118712120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 118812120Sar4jc@virginia.edu float fd; 118912120Sar4jc@virginia.edu 119012120Sar4jc@virginia.edu if (issignalingnan(fs2)) { 119112120Sar4jc@virginia.edu fd = fs1; 119212120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 119312120Sar4jc@virginia.edu } else if (issignalingnan(fs1)) { 119412120Sar4jc@virginia.edu fd = fs2; 119512120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 119612120Sar4jc@virginia.edu } else { 119712120Sar4jc@virginia.edu fd = fmax(fs1, fs2); 119812120Sar4jc@virginia.edu } 119912120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 120012120Sar4jc@virginia.edu }}, FloatCmpOp); 120112120Sar4jc@virginia.edu } 120212120Sar4jc@virginia.edu 0x15: decode ROUND_MODE { 120312120Sar4jc@virginia.edu 0x0: fmin_d({{ 120412120Sar4jc@virginia.edu if (issignalingnan(Fs2)) { 120512120Sar4jc@virginia.edu Fd = Fs1; 120612120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 120712120Sar4jc@virginia.edu } else if (issignalingnan(Fs1)) { 120812120Sar4jc@virginia.edu Fd = Fs2; 120912120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 121012120Sar4jc@virginia.edu } else { 121112120Sar4jc@virginia.edu Fd = fmin(Fs1, Fs2); 121212120Sar4jc@virginia.edu } 121312120Sar4jc@virginia.edu }}, FloatCmpOp); 121412120Sar4jc@virginia.edu 0x1: fmax_d({{ 121512120Sar4jc@virginia.edu if (issignalingnan(Fs2)) { 121612120Sar4jc@virginia.edu Fd = Fs1; 121712120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 121812120Sar4jc@virginia.edu } else if (issignalingnan(Fs1)) { 121912120Sar4jc@virginia.edu Fd = Fs2; 122012120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 122112120Sar4jc@virginia.edu } else { 122212120Sar4jc@virginia.edu Fd = fmax(Fs1, Fs2); 122312120Sar4jc@virginia.edu } 122412120Sar4jc@virginia.edu }}, FloatCmpOp); 122512120Sar4jc@virginia.edu } 122612120Sar4jc@virginia.edu 0x20: fcvt_s_d({{ 122712120Sar4jc@virginia.edu assert(CONV_SGN == 1); 122812120Sar4jc@virginia.edu float fd; 122912120Sar4jc@virginia.edu if (issignalingnan(Fs1)) { 123012120Sar4jc@virginia.edu fd = numeric_limits<float>::quiet_NaN(); 123111725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 123211725Sar4jc@virginia.edu } else { 123312120Sar4jc@virginia.edu fd = (float)Fs1; 123411725Sar4jc@virginia.edu } 123511725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 123612120Sar4jc@virginia.edu }}, FloatCvtOp); 123712120Sar4jc@virginia.edu 0x21: fcvt_d_s({{ 123812120Sar4jc@virginia.edu assert(CONV_SGN == 0); 123911725Sar4jc@virginia.edu uint32_t temp; 124011725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 124111725Sar4jc@virginia.edu 124212120Sar4jc@virginia.edu if (issignalingnan(fs1)) { 124312120Sar4jc@virginia.edu Fd = numeric_limits<double>::quiet_NaN(); 124411725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 124511725Sar4jc@virginia.edu } else { 124612120Sar4jc@virginia.edu Fd = (double)fs1; 124711725Sar4jc@virginia.edu } 124811725Sar4jc@virginia.edu }}, FloatCvtOp); 124912120Sar4jc@virginia.edu 0x2c: fsqrt_s({{ 125012120Sar4jc@virginia.edu assert(RS2 == 0); 125111725Sar4jc@virginia.edu uint32_t temp; 125211725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 125312120Sar4jc@virginia.edu float fd; 125411725Sar4jc@virginia.edu 125512120Sar4jc@virginia.edu if (issignalingnan(Fs1_sf)) { 125611725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 125712120Sar4jc@virginia.edu } 125812120Sar4jc@virginia.edu fd = sqrt(fs1); 125912120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 126012120Sar4jc@virginia.edu }}, FloatSqrtOp); 126112120Sar4jc@virginia.edu 0x2d: fsqrt_d({{ 126212120Sar4jc@virginia.edu assert(RS2 == 0); 126312120Sar4jc@virginia.edu Fd = sqrt(Fs1); 126412120Sar4jc@virginia.edu }}, FloatSqrtOp); 126512120Sar4jc@virginia.edu 0x50: decode ROUND_MODE { 126612120Sar4jc@virginia.edu 0x0: fle_s({{ 126712120Sar4jc@virginia.edu uint32_t temp; 126812120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 126912120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 127012120Sar4jc@virginia.edu 127112120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2)) { 127212120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 127312120Sar4jc@virginia.edu Rd = 0; 127412120Sar4jc@virginia.edu } else { 127512120Sar4jc@virginia.edu Rd = fs1 <= fs2 ? 1 : 0; 127611725Sar4jc@virginia.edu } 127712120Sar4jc@virginia.edu }}, FloatCmpOp); 127812120Sar4jc@virginia.edu 0x1: flt_s({{ 127912120Sar4jc@virginia.edu uint32_t temp; 128012120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 128112120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 128212120Sar4jc@virginia.edu 128312120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2)) { 128412120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 128512120Sar4jc@virginia.edu Rd = 0; 128612120Sar4jc@virginia.edu } else { 128712120Sar4jc@virginia.edu Rd = fs1 < fs2 ? 1 : 0; 128812120Sar4jc@virginia.edu } 128912120Sar4jc@virginia.edu }}, FloatCmpOp); 129012120Sar4jc@virginia.edu 0x2: feq_s({{ 129112120Sar4jc@virginia.edu uint32_t temp; 129212120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 129312120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 129412120Sar4jc@virginia.edu 129512120Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2)) { 129612120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 129712120Sar4jc@virginia.edu } 129812120Sar4jc@virginia.edu Rd = fs1 == fs2 ? 1 : 0; 129912120Sar4jc@virginia.edu }}, FloatCmpOp); 130012120Sar4jc@virginia.edu } 130112120Sar4jc@virginia.edu 0x51: decode ROUND_MODE { 130212120Sar4jc@virginia.edu 0x0: fle_d({{ 130312120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2)) { 130412120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 130512120Sar4jc@virginia.edu Rd = 0; 130612120Sar4jc@virginia.edu } else { 130712120Sar4jc@virginia.edu Rd = Fs1 <= Fs2 ? 1 : 0; 130812120Sar4jc@virginia.edu } 130912120Sar4jc@virginia.edu }}, FloatCmpOp); 131012120Sar4jc@virginia.edu 0x1: flt_d({{ 131112120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2)) { 131212120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 131312120Sar4jc@virginia.edu Rd = 0; 131412120Sar4jc@virginia.edu } else { 131512120Sar4jc@virginia.edu Rd = Fs1 < Fs2 ? 1 : 0; 131612120Sar4jc@virginia.edu } 131712120Sar4jc@virginia.edu }}, FloatCmpOp); 131812120Sar4jc@virginia.edu 0x2: feq_d({{ 131912120Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2)) { 132012120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 132112120Sar4jc@virginia.edu } 132212120Sar4jc@virginia.edu Rd = Fs1 == Fs2 ? 1 : 0; 132312120Sar4jc@virginia.edu }}, FloatCmpOp); 132412120Sar4jc@virginia.edu } 132512120Sar4jc@virginia.edu 0x60: decode CONV_SGN { 132612120Sar4jc@virginia.edu 0x0: fcvt_w_s({{ 132712120Sar4jc@virginia.edu uint32_t temp; 132812120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 132912120Sar4jc@virginia.edu 133012120Sar4jc@virginia.edu if (isnan(fs1)) { 133112120Sar4jc@virginia.edu Rd_sd = numeric_limits<int32_t>::max(); 133212120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 133312120Sar4jc@virginia.edu } else { 133412120Sar4jc@virginia.edu Rd_sd = (int32_t)fs1; 133512120Sar4jc@virginia.edu if (fetestexcept(FE_INVALID)) { 133612120Sar4jc@virginia.edu if (signbit(fs1)) { 133712120Sar4jc@virginia.edu Rd_sd = numeric_limits<int32_t>::min(); 133812120Sar4jc@virginia.edu } else { 133912120Sar4jc@virginia.edu Rd_sd = numeric_limits<int32_t>::max(); 134012120Sar4jc@virginia.edu } 134112120Sar4jc@virginia.edu feclearexcept(FE_INEXACT); 134212120Sar4jc@virginia.edu } 134312120Sar4jc@virginia.edu } 134412120Sar4jc@virginia.edu }}, FloatCvtOp); 134512120Sar4jc@virginia.edu 0x1: fcvt_wu_s({{ 134612120Sar4jc@virginia.edu uint32_t temp; 134712120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 134812120Sar4jc@virginia.edu 134912120Sar4jc@virginia.edu if (fs1 < 0.0) { 135012120Sar4jc@virginia.edu Rd = 0; 135112120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 135212120Sar4jc@virginia.edu } else { 135312120Sar4jc@virginia.edu Rd = (uint32_t)fs1; 135412120Sar4jc@virginia.edu if (fetestexcept(FE_INVALID)) { 135512120Sar4jc@virginia.edu Rd = numeric_limits<uint64_t>::max(); 135612120Sar4jc@virginia.edu feclearexcept(FE_INEXACT); 135712120Sar4jc@virginia.edu } 135812120Sar4jc@virginia.edu } 135912120Sar4jc@virginia.edu }}, FloatCvtOp); 136012120Sar4jc@virginia.edu 0x2: fcvt_l_s({{ 136112120Sar4jc@virginia.edu uint32_t temp; 136212120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 136312120Sar4jc@virginia.edu 136412120Sar4jc@virginia.edu if (isnan(fs1)) { 136512120Sar4jc@virginia.edu Rd_sd = numeric_limits<int64_t>::max(); 136612120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 136712120Sar4jc@virginia.edu } else { 136812120Sar4jc@virginia.edu Rd_sd = (int64_t)fs1; 136912120Sar4jc@virginia.edu if (fetestexcept(FE_INVALID)) { 137012120Sar4jc@virginia.edu if (signbit(fs1)) { 137112120Sar4jc@virginia.edu Rd_sd = numeric_limits<int64_t>::min(); 137212120Sar4jc@virginia.edu } else { 137312120Sar4jc@virginia.edu Rd_sd = numeric_limits<int64_t>::max(); 137412120Sar4jc@virginia.edu } 137512120Sar4jc@virginia.edu feclearexcept(FE_INEXACT); 137612120Sar4jc@virginia.edu } 137712120Sar4jc@virginia.edu } 137812120Sar4jc@virginia.edu }}, FloatCvtOp); 137912120Sar4jc@virginia.edu 0x3: fcvt_lu_s({{ 138012120Sar4jc@virginia.edu uint32_t temp; 138112120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 138212120Sar4jc@virginia.edu 138312120Sar4jc@virginia.edu if (fs1 < 0.0) { 138412120Sar4jc@virginia.edu Rd = 0; 138512120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 138612120Sar4jc@virginia.edu } else { 138712120Sar4jc@virginia.edu Rd = (uint64_t)fs1; 138812120Sar4jc@virginia.edu if (fetestexcept(FE_INVALID)) { 138912120Sar4jc@virginia.edu Rd = numeric_limits<uint64_t>::max(); 139012120Sar4jc@virginia.edu feclearexcept(FE_INEXACT); 139112120Sar4jc@virginia.edu } 139212120Sar4jc@virginia.edu } 139312120Sar4jc@virginia.edu }}, FloatCvtOp); 139412120Sar4jc@virginia.edu } 139512120Sar4jc@virginia.edu 0x61: decode CONV_SGN { 139612120Sar4jc@virginia.edu 0x0: fcvt_w_d({{ 139712120Sar4jc@virginia.edu Rd_sd = (int32_t)Fs1; 139812120Sar4jc@virginia.edu if (fetestexcept(FE_INVALID)) { 139912120Sar4jc@virginia.edu if (Fs1 < 0.0) { 140012120Sar4jc@virginia.edu Rd_sd = numeric_limits<int32_t>::min(); 140112120Sar4jc@virginia.edu } else { 140212120Sar4jc@virginia.edu Rd_sd = numeric_limits<int32_t>::max(); 140312120Sar4jc@virginia.edu } 140412120Sar4jc@virginia.edu feclearexcept(FE_INEXACT); 140512120Sar4jc@virginia.edu } 140612120Sar4jc@virginia.edu }}, FloatCvtOp); 140712120Sar4jc@virginia.edu 0x1: fcvt_wu_d({{ 140812120Sar4jc@virginia.edu if (Fs1 < 0.0) { 140912120Sar4jc@virginia.edu Rd = 0; 141012120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 141112120Sar4jc@virginia.edu } else { 141212120Sar4jc@virginia.edu Rd = (uint32_t)Fs1; 141312120Sar4jc@virginia.edu if (fetestexcept(FE_INVALID)) { 141412120Sar4jc@virginia.edu Rd = numeric_limits<uint64_t>::max(); 141512120Sar4jc@virginia.edu feclearexcept(FE_INEXACT); 141612120Sar4jc@virginia.edu } 141712120Sar4jc@virginia.edu } 141812120Sar4jc@virginia.edu }}, FloatCvtOp); 141912120Sar4jc@virginia.edu 0x2: fcvt_l_d({{ 142012120Sar4jc@virginia.edu Rd_sd = Fs1; 142112120Sar4jc@virginia.edu if (fetestexcept(FE_INVALID)) { 142212120Sar4jc@virginia.edu if (Fs1 < 0.0) { 142312120Sar4jc@virginia.edu Rd_sd = numeric_limits<int64_t>::min(); 142412120Sar4jc@virginia.edu } else { 142512120Sar4jc@virginia.edu Rd_sd = numeric_limits<int64_t>::max(); 142612120Sar4jc@virginia.edu } 142712120Sar4jc@virginia.edu feclearexcept(FE_INEXACT); 142812120Sar4jc@virginia.edu } 142912120Sar4jc@virginia.edu }}, FloatCvtOp); 143012120Sar4jc@virginia.edu 0x3: fcvt_lu_d({{ 143112120Sar4jc@virginia.edu if (Fs1 < 0.0) { 143212120Sar4jc@virginia.edu Rd = 0; 143312120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 143412120Sar4jc@virginia.edu } else { 143512120Sar4jc@virginia.edu Rd = (uint64_t)Fs1; 143612120Sar4jc@virginia.edu if (fetestexcept(FE_INVALID)) { 143712120Sar4jc@virginia.edu Rd = numeric_limits<uint64_t>::max(); 143812120Sar4jc@virginia.edu feclearexcept(FE_INEXACT); 143912120Sar4jc@virginia.edu } 144012120Sar4jc@virginia.edu } 144112120Sar4jc@virginia.edu }}, FloatCvtOp); 144212120Sar4jc@virginia.edu } 144312120Sar4jc@virginia.edu 0x68: decode CONV_SGN { 144412120Sar4jc@virginia.edu 0x0: fcvt_s_w({{ 144512120Sar4jc@virginia.edu float temp = (float)Rs1_sw; 144612120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp); 144712120Sar4jc@virginia.edu }}, FloatCvtOp); 144812120Sar4jc@virginia.edu 0x1: fcvt_s_wu({{ 144912120Sar4jc@virginia.edu float temp = (float)Rs1_uw; 145012120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp); 145112120Sar4jc@virginia.edu }}, FloatCvtOp); 145212120Sar4jc@virginia.edu 0x2: fcvt_s_l({{ 145312120Sar4jc@virginia.edu float temp = (float)Rs1_sd; 145412120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp); 145512120Sar4jc@virginia.edu }}, FloatCvtOp); 145612120Sar4jc@virginia.edu 0x3: fcvt_s_lu({{ 145712120Sar4jc@virginia.edu float temp = (float)Rs1; 145812120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp); 145912120Sar4jc@virginia.edu }}, FloatCvtOp); 146012120Sar4jc@virginia.edu } 146112120Sar4jc@virginia.edu 0x69: decode CONV_SGN { 146212120Sar4jc@virginia.edu 0x0: fcvt_d_w({{ 146312120Sar4jc@virginia.edu Fd = (double)Rs1_sw; 146412120Sar4jc@virginia.edu }}, FloatCvtOp); 146512120Sar4jc@virginia.edu 0x1: fcvt_d_wu({{ 146612120Sar4jc@virginia.edu Fd = (double)Rs1_uw; 146712120Sar4jc@virginia.edu }}, FloatCvtOp); 146812120Sar4jc@virginia.edu 0x2: fcvt_d_l({{ 146912120Sar4jc@virginia.edu Fd = (double)Rs1_sd; 147012120Sar4jc@virginia.edu }}, FloatCvtOp); 147112120Sar4jc@virginia.edu 0x3: fcvt_d_lu({{ 147212120Sar4jc@virginia.edu Fd = (double)Rs1; 147312120Sar4jc@virginia.edu }}, FloatCvtOp); 147412120Sar4jc@virginia.edu } 147512120Sar4jc@virginia.edu 0x70: decode ROUND_MODE { 147612120Sar4jc@virginia.edu 0x0: fmv_x_s({{ 147712120Sar4jc@virginia.edu Rd = (uint32_t)Fs1_bits; 147812120Sar4jc@virginia.edu if ((Rd&0x80000000) != 0) { 147912120Sar4jc@virginia.edu Rd |= (0xFFFFFFFFULL << 32); 148012120Sar4jc@virginia.edu } 148112120Sar4jc@virginia.edu }}, FloatCvtOp); 148212120Sar4jc@virginia.edu 0x1: fclass_s({{ 148312120Sar4jc@virginia.edu uint32_t temp; 148412120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 148512120Sar4jc@virginia.edu switch (fpclassify(fs1)) { 148612120Sar4jc@virginia.edu case FP_INFINITE: 148712120Sar4jc@virginia.edu if (signbit(fs1)) { 148812120Sar4jc@virginia.edu Rd = 1 << 0; 148912120Sar4jc@virginia.edu } else { 149012120Sar4jc@virginia.edu Rd = 1 << 7; 149112120Sar4jc@virginia.edu } 149212120Sar4jc@virginia.edu break; 149312120Sar4jc@virginia.edu case FP_NAN: 149412120Sar4jc@virginia.edu if (issignalingnan(fs1)) { 149512120Sar4jc@virginia.edu Rd = 1 << 8; 149612120Sar4jc@virginia.edu } else { 149712120Sar4jc@virginia.edu Rd = 1 << 9; 149812120Sar4jc@virginia.edu } 149912120Sar4jc@virginia.edu break; 150012120Sar4jc@virginia.edu case FP_ZERO: 150112120Sar4jc@virginia.edu if (signbit(fs1)) { 150212120Sar4jc@virginia.edu Rd = 1 << 3; 150312120Sar4jc@virginia.edu } else { 150412120Sar4jc@virginia.edu Rd = 1 << 4; 150512120Sar4jc@virginia.edu } 150612120Sar4jc@virginia.edu break; 150712120Sar4jc@virginia.edu case FP_SUBNORMAL: 150812120Sar4jc@virginia.edu if (signbit(fs1)) { 150912120Sar4jc@virginia.edu Rd = 1 << 2; 151012120Sar4jc@virginia.edu } else { 151112120Sar4jc@virginia.edu Rd = 1 << 5; 151212120Sar4jc@virginia.edu } 151312120Sar4jc@virginia.edu break; 151412120Sar4jc@virginia.edu case FP_NORMAL: 151512120Sar4jc@virginia.edu if (signbit(fs1)) { 151612120Sar4jc@virginia.edu Rd = 1 << 1; 151712120Sar4jc@virginia.edu } else { 151812120Sar4jc@virginia.edu Rd = 1 << 6; 151912120Sar4jc@virginia.edu } 152012120Sar4jc@virginia.edu break; 152112120Sar4jc@virginia.edu default: 152212120Sar4jc@virginia.edu panic("Unknown classification for operand."); 152312120Sar4jc@virginia.edu break; 152412120Sar4jc@virginia.edu } 152512120Sar4jc@virginia.edu }}); 152612120Sar4jc@virginia.edu } 152712120Sar4jc@virginia.edu 0x71: decode ROUND_MODE { 152812120Sar4jc@virginia.edu 0x0: fmv_x_d({{ 152912120Sar4jc@virginia.edu Rd = Fs1_bits; 153012120Sar4jc@virginia.edu }}, FloatCvtOp); 153112120Sar4jc@virginia.edu 0x1: fclass_d({{ 153212120Sar4jc@virginia.edu switch (fpclassify(Fs1)) { 153312120Sar4jc@virginia.edu case FP_INFINITE: 153412120Sar4jc@virginia.edu if (signbit(Fs1)) { 153512120Sar4jc@virginia.edu Rd = 1 << 0; 153612120Sar4jc@virginia.edu } else { 153712120Sar4jc@virginia.edu Rd = 1 << 7; 153812120Sar4jc@virginia.edu } 153912120Sar4jc@virginia.edu break; 154012120Sar4jc@virginia.edu case FP_NAN: 154112120Sar4jc@virginia.edu if (issignalingnan(Fs1)) { 154212120Sar4jc@virginia.edu Rd = 1 << 8; 154312120Sar4jc@virginia.edu } else { 154412120Sar4jc@virginia.edu Rd = 1 << 9; 154512120Sar4jc@virginia.edu } 154612120Sar4jc@virginia.edu break; 154712120Sar4jc@virginia.edu case FP_ZERO: 154812120Sar4jc@virginia.edu if (signbit(Fs1)) { 154912120Sar4jc@virginia.edu Rd = 1 << 3; 155012120Sar4jc@virginia.edu } else { 155112120Sar4jc@virginia.edu Rd = 1 << 4; 155212120Sar4jc@virginia.edu } 155312120Sar4jc@virginia.edu break; 155412120Sar4jc@virginia.edu case FP_SUBNORMAL: 155512120Sar4jc@virginia.edu if (signbit(Fs1)) { 155612120Sar4jc@virginia.edu Rd = 1 << 2; 155712120Sar4jc@virginia.edu } else { 155812120Sar4jc@virginia.edu Rd = 1 << 5; 155912120Sar4jc@virginia.edu } 156012120Sar4jc@virginia.edu break; 156112120Sar4jc@virginia.edu case FP_NORMAL: 156212120Sar4jc@virginia.edu if (signbit(Fs1)) { 156312120Sar4jc@virginia.edu Rd = 1 << 1; 156412120Sar4jc@virginia.edu } else { 156512120Sar4jc@virginia.edu Rd = 1 << 6; 156612120Sar4jc@virginia.edu } 156712120Sar4jc@virginia.edu break; 156812120Sar4jc@virginia.edu default: 156912120Sar4jc@virginia.edu panic("Unknown classification for operand."); 157012120Sar4jc@virginia.edu break; 157112120Sar4jc@virginia.edu } 157212120Sar4jc@virginia.edu }}); 157312120Sar4jc@virginia.edu } 157412120Sar4jc@virginia.edu 0x78: fmv_s_x({{ 157512120Sar4jc@virginia.edu Fd_bits = (uint64_t)Rs1_uw; 157611725Sar4jc@virginia.edu }}, FloatCvtOp); 157712120Sar4jc@virginia.edu 0x79: fmv_d_x({{ 157812120Sar4jc@virginia.edu Fd_bits = Rs1; 157911725Sar4jc@virginia.edu }}, FloatCvtOp); 158011725Sar4jc@virginia.edu } 158112120Sar4jc@virginia.edu } 158212120Sar4jc@virginia.edu 158312120Sar4jc@virginia.edu 0x18: decode FUNCT3 { 158412120Sar4jc@virginia.edu format BOp { 158512120Sar4jc@virginia.edu 0x0: beq({{ 158612120Sar4jc@virginia.edu if (Rs1 == Rs2) { 158712120Sar4jc@virginia.edu NPC = PC + imm; 158812120Sar4jc@virginia.edu } else { 158912120Sar4jc@virginia.edu NPC = NPC; 159011725Sar4jc@virginia.edu } 159112120Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 159212120Sar4jc@virginia.edu 0x1: bne({{ 159312120Sar4jc@virginia.edu if (Rs1 != Rs2) { 159412120Sar4jc@virginia.edu NPC = PC + imm; 159511725Sar4jc@virginia.edu } else { 159612120Sar4jc@virginia.edu NPC = NPC; 159711725Sar4jc@virginia.edu } 159812120Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 159912120Sar4jc@virginia.edu 0x4: blt({{ 160012120Sar4jc@virginia.edu if (Rs1_sd < Rs2_sd) { 160112120Sar4jc@virginia.edu NPC = PC + imm; 160212120Sar4jc@virginia.edu } else { 160312120Sar4jc@virginia.edu NPC = NPC; 160411725Sar4jc@virginia.edu } 160512120Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 160612120Sar4jc@virginia.edu 0x5: bge({{ 160712120Sar4jc@virginia.edu if (Rs1_sd >= Rs2_sd) { 160812120Sar4jc@virginia.edu NPC = PC + imm; 160911725Sar4jc@virginia.edu } else { 161012120Sar4jc@virginia.edu NPC = NPC; 161111725Sar4jc@virginia.edu } 161212120Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 161312120Sar4jc@virginia.edu 0x6: bltu({{ 161412120Sar4jc@virginia.edu if (Rs1 < Rs2) { 161512120Sar4jc@virginia.edu NPC = PC + imm; 161612120Sar4jc@virginia.edu } else { 161712120Sar4jc@virginia.edu NPC = NPC; 161812120Sar4jc@virginia.edu } 161912120Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 162012120Sar4jc@virginia.edu 0x7: bgeu({{ 162112120Sar4jc@virginia.edu if (Rs1 >= Rs2) { 162212120Sar4jc@virginia.edu NPC = PC + imm; 162312120Sar4jc@virginia.edu } else { 162412120Sar4jc@virginia.edu NPC = NPC; 162512120Sar4jc@virginia.edu } 162612120Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 162711725Sar4jc@virginia.edu } 162812120Sar4jc@virginia.edu } 162912120Sar4jc@virginia.edu 163012120Sar4jc@virginia.edu 0x19: decode FUNCT3 { 163112120Sar4jc@virginia.edu 0x0: Jump::jalr({{ 163212120Sar4jc@virginia.edu Rd = NPC; 163312120Sar4jc@virginia.edu NPC = (imm + Rs1) & (~0x1); 163412120Sar4jc@virginia.edu }}, IsIndirectControl, IsUncondControl, IsCall); 163512120Sar4jc@virginia.edu } 163612120Sar4jc@virginia.edu 163712120Sar4jc@virginia.edu 0x1b: JOp::jal({{ 163812120Sar4jc@virginia.edu Rd = NPC; 163912120Sar4jc@virginia.edu NPC = PC + imm; 164012120Sar4jc@virginia.edu }}, IsDirectControl, IsUncondControl, IsCall); 164112120Sar4jc@virginia.edu 164212120Sar4jc@virginia.edu 0x1c: decode FUNCT3 { 164312120Sar4jc@virginia.edu format SystemOp { 164412120Sar4jc@virginia.edu 0x0: decode FUNCT12 { 164512120Sar4jc@virginia.edu 0x0: ecall({{ 164612120Sar4jc@virginia.edu fault = make_shared<SyscallFault>(); 164712120Sar4jc@virginia.edu }}, IsSerializeAfter, IsNonSpeculative, IsSyscall, 164812120Sar4jc@virginia.edu No_OpClass); 164912120Sar4jc@virginia.edu 0x1: ebreak({{ 165012120Sar4jc@virginia.edu fault = make_shared<BreakpointFault>(); 165112120Sar4jc@virginia.edu }}, IsSerializeAfter, IsNonSpeculative, No_OpClass); 165212120Sar4jc@virginia.edu 0x100: eret({{ 165312120Sar4jc@virginia.edu fault = make_shared<UnimplementedFault>("eret"); 165412120Sar4jc@virginia.edu }}, No_OpClass); 165512120Sar4jc@virginia.edu } 165611725Sar4jc@virginia.edu } 165712120Sar4jc@virginia.edu format CSROp { 165812120Sar4jc@virginia.edu 0x1: csrrw({{ 165912120Sar4jc@virginia.edu Rd = xc->readMiscReg(csr); 166012120Sar4jc@virginia.edu xc->setMiscReg(csr, Rs1); 166112120Sar4jc@virginia.edu }}, IsNonSpeculative, No_OpClass); 166212120Sar4jc@virginia.edu 0x2: csrrs({{ 166312120Sar4jc@virginia.edu Rd = xc->readMiscReg(csr); 166412120Sar4jc@virginia.edu if (Rs1 != 0) { 166512120Sar4jc@virginia.edu xc->setMiscReg(csr, Rd | Rs1); 166612120Sar4jc@virginia.edu } 166712120Sar4jc@virginia.edu }}, IsNonSpeculative, No_OpClass); 166812120Sar4jc@virginia.edu 0x3: csrrc({{ 166912120Sar4jc@virginia.edu Rd = xc->readMiscReg(csr); 167012120Sar4jc@virginia.edu if (Rs1 != 0) { 167112120Sar4jc@virginia.edu xc->setMiscReg(csr, Rd & ~Rs1); 167212120Sar4jc@virginia.edu } 167312120Sar4jc@virginia.edu }}, IsNonSpeculative, No_OpClass); 167412120Sar4jc@virginia.edu 0x5: csrrwi({{ 167512120Sar4jc@virginia.edu Rd = xc->readMiscReg(csr); 167612120Sar4jc@virginia.edu xc->setMiscReg(csr, uimm); 167712120Sar4jc@virginia.edu }}, IsNonSpeculative, No_OpClass); 167812120Sar4jc@virginia.edu 0x6: csrrsi({{ 167912120Sar4jc@virginia.edu Rd = xc->readMiscReg(csr); 168012120Sar4jc@virginia.edu if (uimm != 0) { 168112120Sar4jc@virginia.edu xc->setMiscReg(csr, Rd | uimm); 168212120Sar4jc@virginia.edu } 168312120Sar4jc@virginia.edu }}, IsNonSpeculative, No_OpClass); 168412120Sar4jc@virginia.edu 0x7: csrrci({{ 168512120Sar4jc@virginia.edu Rd = xc->readMiscReg(csr); 168612120Sar4jc@virginia.edu if (uimm != 0) { 168712120Sar4jc@virginia.edu xc->setMiscReg(csr, Rd & ~uimm); 168812120Sar4jc@virginia.edu } 168912120Sar4jc@virginia.edu }}, IsNonSpeculative, No_OpClass); 169011725Sar4jc@virginia.edu } 169111725Sar4jc@virginia.edu } 169211725Sar4jc@virginia.edu } 169312120Sar4jc@virginia.edu}