decoder.isa revision 12120
111723Sar4jc@virginia.edu// -*- mode:c++ -*- 211723Sar4jc@virginia.edu 311723Sar4jc@virginia.edu// Copyright (c) 2015 RISC-V Foundation 412120Sar4jc@virginia.edu// Copyright (c) 2017 The University of Virginia 511723Sar4jc@virginia.edu// All rights reserved. 611723Sar4jc@virginia.edu// 711723Sar4jc@virginia.edu// Redistribution and use in source and binary forms, with or without 811723Sar4jc@virginia.edu// modification, are permitted provided that the following conditions are 911723Sar4jc@virginia.edu// met: redistributions of source code must retain the above copyright 1011723Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer; 1111723Sar4jc@virginia.edu// redistributions in binary form must reproduce the above copyright 1211723Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer in the 1311723Sar4jc@virginia.edu// documentation and/or other materials provided with the distribution; 1411723Sar4jc@virginia.edu// neither the name of the copyright holders nor the names of its 1511723Sar4jc@virginia.edu// contributors may be used to endorse or promote products derived from 1611723Sar4jc@virginia.edu// this software without specific prior written permission. 1711723Sar4jc@virginia.edu// 1811723Sar4jc@virginia.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1911723Sar4jc@virginia.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2011723Sar4jc@virginia.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2111723Sar4jc@virginia.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2211723Sar4jc@virginia.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2311723Sar4jc@virginia.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2411723Sar4jc@virginia.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2511723Sar4jc@virginia.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2611723Sar4jc@virginia.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2711723Sar4jc@virginia.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2811723Sar4jc@virginia.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2911723Sar4jc@virginia.edu// 3011723Sar4jc@virginia.edu// Authors: Alec Roelke 3111723Sar4jc@virginia.edu 3211723Sar4jc@virginia.edu//////////////////////////////////////////////////////////////////// 3311723Sar4jc@virginia.edu// 3411723Sar4jc@virginia.edu// The RISC-V ISA decoder 3511723Sar4jc@virginia.edu// 3611723Sar4jc@virginia.edu 3712120Sar4jc@virginia.edudecode QUADRANT default Unknown::unknown() { 3812120Sar4jc@virginia.edu 0x0: decode COPCODE { 3912120Sar4jc@virginia.edu 0x0: CUIOp::c_addi4spn({{ 4012120Sar4jc@virginia.edu imm = CIMM8<1:1> << 2 | 4112120Sar4jc@virginia.edu CIMM8<0:0> << 3 | 4212120Sar4jc@virginia.edu CIMM8<7:6> << 4 | 4312120Sar4jc@virginia.edu CIMM8<5:2> << 6; 4412120Sar4jc@virginia.edu }}, {{ 4512120Sar4jc@virginia.edu assert(imm != 0); 4612120Sar4jc@virginia.edu Rp2 = sp + imm; 4712120Sar4jc@virginia.edu }}); 4812120Sar4jc@virginia.edu format CompressedLoad { 4912120Sar4jc@virginia.edu 0x1: c_fld({{ 5012120Sar4jc@virginia.edu ldisp = CIMM3 << 3 | CIMM2 << 6; 5112120Sar4jc@virginia.edu }}, {{ 5212120Sar4jc@virginia.edu Fp2_bits = Mem; 5312120Sar4jc@virginia.edu }}, {{ 5412120Sar4jc@virginia.edu EA = Rp1 + ldisp; 5511723Sar4jc@virginia.edu }}); 5612120Sar4jc@virginia.edu 0x2: c_lw({{ 5712120Sar4jc@virginia.edu ldisp = CIMM2<1:1> << 2 | 5812120Sar4jc@virginia.edu CIMM3 << 3 | 5912120Sar4jc@virginia.edu CIMM2<0:0> << 6; 6012120Sar4jc@virginia.edu }}, {{ 6112120Sar4jc@virginia.edu Rp2_sd = Mem_sw; 6212120Sar4jc@virginia.edu }}, {{ 6312120Sar4jc@virginia.edu EA = Rp1 + ldisp; 6411723Sar4jc@virginia.edu }}); 6512120Sar4jc@virginia.edu 0x3: c_ld({{ 6612120Sar4jc@virginia.edu ldisp = CIMM3 << 3 | CIMM2 << 6; 6712120Sar4jc@virginia.edu }}, {{ 6812120Sar4jc@virginia.edu Rp2_sd = Mem_sd; 6912120Sar4jc@virginia.edu }}, {{ 7012120Sar4jc@virginia.edu EA = Rp1 + ldisp; 7111723Sar4jc@virginia.edu }}); 7212120Sar4jc@virginia.edu } 7312120Sar4jc@virginia.edu format CompressedStore { 7412120Sar4jc@virginia.edu 0x5: c_fsd({{ 7512120Sar4jc@virginia.edu sdisp = CIMM3 << 3 | CIMM2 << 6; 7612120Sar4jc@virginia.edu }}, {{ 7712120Sar4jc@virginia.edu Mem = Fp2_bits; 7812120Sar4jc@virginia.edu }}, {{ 7912120Sar4jc@virginia.edu EA = Rp1 + sdisp; 8011723Sar4jc@virginia.edu }}); 8112120Sar4jc@virginia.edu 0x6: c_sw({{ 8212120Sar4jc@virginia.edu sdisp = CIMM2<1:1> << 2 | 8312120Sar4jc@virginia.edu CIMM3 << 3 | 8412120Sar4jc@virginia.edu CIMM2<0:0> << 6; 8512120Sar4jc@virginia.edu }}, {{ 8612120Sar4jc@virginia.edu Mem_uw = Rp2_uw; 8712120Sar4jc@virginia.edu }}, ea_code={{ 8812120Sar4jc@virginia.edu EA = Rp1 + sdisp; 8911723Sar4jc@virginia.edu }}); 9012120Sar4jc@virginia.edu 0x7: c_sd({{ 9112120Sar4jc@virginia.edu sdisp = CIMM3 << 3 | CIMM2 << 6; 9212120Sar4jc@virginia.edu }}, {{ 9312120Sar4jc@virginia.edu Mem_ud = Rp2_ud; 9412120Sar4jc@virginia.edu }}, {{ 9512120Sar4jc@virginia.edu EA = Rp1 + sdisp; 9611723Sar4jc@virginia.edu }}); 9711723Sar4jc@virginia.edu } 9811723Sar4jc@virginia.edu } 9912120Sar4jc@virginia.edu 0x1: decode COPCODE { 10012120Sar4jc@virginia.edu format CIOp { 10112120Sar4jc@virginia.edu 0x0: c_addi({{ 10212120Sar4jc@virginia.edu imm = CIMM5; 10312120Sar4jc@virginia.edu if (CIMM1 > 0) 10412120Sar4jc@virginia.edu imm |= ~((uint64_t)0x1F); 10512120Sar4jc@virginia.edu }}, {{ 10612120Sar4jc@virginia.edu assert((RC1 == 0) == (imm == 0)); 10712120Sar4jc@virginia.edu Rc1_sd = Rc1_sd + imm; 10812120Sar4jc@virginia.edu }}); 10912120Sar4jc@virginia.edu 0x1: c_addiw({{ 11012120Sar4jc@virginia.edu imm = CIMM5; 11112120Sar4jc@virginia.edu if (CIMM1 > 0) 11212120Sar4jc@virginia.edu imm |= ~((uint64_t)0x1F); 11312120Sar4jc@virginia.edu }}, {{ 11412120Sar4jc@virginia.edu assert(RC1 != 0); 11512120Sar4jc@virginia.edu Rc1_sd = (int32_t)Rc1_sd + imm; 11612120Sar4jc@virginia.edu }}); 11712120Sar4jc@virginia.edu 0x2: c_li({{ 11812120Sar4jc@virginia.edu imm = CIMM5; 11912120Sar4jc@virginia.edu if (CIMM1 > 0) 12012120Sar4jc@virginia.edu imm |= ~((uint64_t)0x1F); 12112120Sar4jc@virginia.edu }}, {{ 12212120Sar4jc@virginia.edu assert(RC1 != 0); 12312120Sar4jc@virginia.edu Rc1_sd = imm; 12412120Sar4jc@virginia.edu }}); 12512120Sar4jc@virginia.edu 0x3: decode RC1 { 12612120Sar4jc@virginia.edu 0x2: c_addi16sp({{ 12712120Sar4jc@virginia.edu imm = CIMM5<4:4> << 4 | 12812120Sar4jc@virginia.edu CIMM5<0:0> << 5 | 12912120Sar4jc@virginia.edu CIMM5<3:3> << 6 | 13012120Sar4jc@virginia.edu CIMM5<2:1> << 7; 13112120Sar4jc@virginia.edu if (CIMM1 > 0) 13212120Sar4jc@virginia.edu imm |= ~((int64_t)0x1FF); 13312120Sar4jc@virginia.edu }}, {{ 13412120Sar4jc@virginia.edu assert(imm != 0); 13512120Sar4jc@virginia.edu sp_sd = sp_sd + imm; 13612120Sar4jc@virginia.edu }}); 13712120Sar4jc@virginia.edu default: c_lui({{ 13812120Sar4jc@virginia.edu imm = CIMM5 << 12; 13912120Sar4jc@virginia.edu if (CIMM1 > 0) 14012120Sar4jc@virginia.edu imm |= ~((uint64_t)0x1FFFF); 14112120Sar4jc@virginia.edu }}, {{ 14212120Sar4jc@virginia.edu assert(RC1 != 0 && RC1 != 2); 14312120Sar4jc@virginia.edu assert(imm != 0); 14412120Sar4jc@virginia.edu Rc1_sd = imm; 14512120Sar4jc@virginia.edu }}); 14612120Sar4jc@virginia.edu } 14712120Sar4jc@virginia.edu } 14812120Sar4jc@virginia.edu 0x4: decode CFUNCT2HIGH { 14912120Sar4jc@virginia.edu format CUIOp { 15012120Sar4jc@virginia.edu 0x0: c_srli({{ 15112120Sar4jc@virginia.edu imm = CIMM5 | (CIMM1 << 5); 15212120Sar4jc@virginia.edu assert(imm != 0); 15312120Sar4jc@virginia.edu }}, {{ 15412120Sar4jc@virginia.edu Rp1 = Rp1 >> imm; 15512120Sar4jc@virginia.edu }}); 15612120Sar4jc@virginia.edu 0x1: c_srai({{ 15712120Sar4jc@virginia.edu imm = CIMM5 | (CIMM1 << 5); 15812120Sar4jc@virginia.edu assert(imm != 0); 15912120Sar4jc@virginia.edu }}, {{ 16012120Sar4jc@virginia.edu Rp1_sd = Rp1_sd >> imm; 16112120Sar4jc@virginia.edu }}); 16212120Sar4jc@virginia.edu 0x2: c_andi({{ 16312120Sar4jc@virginia.edu imm = CIMM5; 16412120Sar4jc@virginia.edu if (CIMM1 > 0) 16512120Sar4jc@virginia.edu imm |= ~((uint64_t)0x1F); 16612120Sar4jc@virginia.edu }}, {{ 16712120Sar4jc@virginia.edu Rp1 = Rp1 & imm; 16812120Sar4jc@virginia.edu }}); 16912120Sar4jc@virginia.edu } 17012120Sar4jc@virginia.edu format ROp { 17112120Sar4jc@virginia.edu 0x3: decode CFUNCT1 { 17212120Sar4jc@virginia.edu 0x0: decode CFUNCT2LOW { 17312120Sar4jc@virginia.edu 0x0: c_sub({{ 17412120Sar4jc@virginia.edu Rp1 = Rp1 - Rp2; 17512120Sar4jc@virginia.edu }}); 17612120Sar4jc@virginia.edu 0x1: c_xor({{ 17712120Sar4jc@virginia.edu Rp1 = Rp1 ^ Rp2; 17812120Sar4jc@virginia.edu }}); 17912120Sar4jc@virginia.edu 0x2: c_or({{ 18012120Sar4jc@virginia.edu Rp1 = Rp1 | Rp2; 18112120Sar4jc@virginia.edu }}); 18212120Sar4jc@virginia.edu 0x3: c_and({{ 18312120Sar4jc@virginia.edu Rp1 = Rp1 & Rp2; 18412120Sar4jc@virginia.edu }}); 18512120Sar4jc@virginia.edu } 18612120Sar4jc@virginia.edu 0x1: decode CFUNCT2LOW { 18712120Sar4jc@virginia.edu 0x0: c_subw({{ 18812120Sar4jc@virginia.edu Rp1_sd = (int32_t)Rp1_sd - Rp2_sw; 18912120Sar4jc@virginia.edu }}); 19012120Sar4jc@virginia.edu 0x1: c_addw({{ 19112120Sar4jc@virginia.edu Rp1_sd = (int32_t)Rp1_sd + Rp2_sw; 19212120Sar4jc@virginia.edu }}); 19312120Sar4jc@virginia.edu } 19412120Sar4jc@virginia.edu } 19512120Sar4jc@virginia.edu } 19612120Sar4jc@virginia.edu } 19712120Sar4jc@virginia.edu 0x5: JOp::c_j({{ 19812120Sar4jc@virginia.edu int64_t offset = CJUMPIMM<3:1> << 1 | 19912120Sar4jc@virginia.edu CJUMPIMM<9:9> << 4 | 20012120Sar4jc@virginia.edu CJUMPIMM<0:0> << 5 | 20112120Sar4jc@virginia.edu CJUMPIMM<5:5> << 6 | 20212120Sar4jc@virginia.edu CJUMPIMM<4:4> << 7 | 20312120Sar4jc@virginia.edu CJUMPIMM<8:7> << 8 | 20412120Sar4jc@virginia.edu CJUMPIMM<6:6> << 10; 20512120Sar4jc@virginia.edu if (CJUMPIMM<10:10> > 0) 20612120Sar4jc@virginia.edu offset |= ~((int64_t)0x7FF); 20712120Sar4jc@virginia.edu NPC = PC + offset; 20812120Sar4jc@virginia.edu }}, IsIndirectControl, IsUncondControl, IsCall); 20912120Sar4jc@virginia.edu format BOp { 21012120Sar4jc@virginia.edu 0x6: c_beqz({{ 21112120Sar4jc@virginia.edu int64_t offset = CIMM5<2:1> << 1 | 21212120Sar4jc@virginia.edu CIMM3<1:0> << 3 | 21312120Sar4jc@virginia.edu CIMM5<0:0> << 5 | 21412120Sar4jc@virginia.edu CIMM5<4:3> << 6; 21512120Sar4jc@virginia.edu if (CIMM3<2:2> > 0) 21612120Sar4jc@virginia.edu offset |= ~((int64_t)0xFF); 21711723Sar4jc@virginia.edu 21812120Sar4jc@virginia.edu if (Rp1 == 0) 21912120Sar4jc@virginia.edu NPC = PC + offset; 22012120Sar4jc@virginia.edu else 22112120Sar4jc@virginia.edu NPC = NPC; 22212120Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 22312120Sar4jc@virginia.edu 0x7: c_bnez({{ 22412120Sar4jc@virginia.edu int64_t offset = CIMM5<2:1> << 1 | 22512120Sar4jc@virginia.edu CIMM3<1:0> << 3 | 22612120Sar4jc@virginia.edu CIMM5<0:0> << 5 | 22712120Sar4jc@virginia.edu CIMM5<4:3> << 6; 22812120Sar4jc@virginia.edu if (CIMM3<2:2> > 0) 22912120Sar4jc@virginia.edu offset |= ~((int64_t)0xFF); 23012120Sar4jc@virginia.edu 23112120Sar4jc@virginia.edu if (Rp1 != 0) 23212120Sar4jc@virginia.edu NPC = PC + offset; 23312120Sar4jc@virginia.edu else 23412120Sar4jc@virginia.edu NPC = NPC; 23512120Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 23612120Sar4jc@virginia.edu } 23712120Sar4jc@virginia.edu } 23812120Sar4jc@virginia.edu 0x2: decode COPCODE { 23912120Sar4jc@virginia.edu 0x0: CUIOp::c_slli({{ 24012120Sar4jc@virginia.edu imm = CIMM5 | (CIMM1 << 5); 24112120Sar4jc@virginia.edu assert(imm != 0); 24212120Sar4jc@virginia.edu }}, {{ 24312120Sar4jc@virginia.edu assert(RC1 != 0); 24412120Sar4jc@virginia.edu Rc1 = Rc1 << imm; 24512120Sar4jc@virginia.edu }}); 24612120Sar4jc@virginia.edu format CompressedLoad { 24712120Sar4jc@virginia.edu 0x1: c_fldsp({{ 24812120Sar4jc@virginia.edu ldisp = CIMM5<4:3> << 3 | 24912120Sar4jc@virginia.edu CIMM1 << 5 | 25012120Sar4jc@virginia.edu CIMM5<2:0> << 6; 25112120Sar4jc@virginia.edu }}, {{ 25212120Sar4jc@virginia.edu Fc1_bits = Mem; 25312120Sar4jc@virginia.edu }}, {{ 25412120Sar4jc@virginia.edu EA = sp + ldisp; 25511725Sar4jc@virginia.edu }}); 25612120Sar4jc@virginia.edu 0x2: c_lwsp({{ 25712120Sar4jc@virginia.edu ldisp = CIMM5<4:2> << 2 | 25812120Sar4jc@virginia.edu CIMM1 << 5 | 25912120Sar4jc@virginia.edu CIMM5<1:0> << 6; 26012120Sar4jc@virginia.edu }}, {{ 26112120Sar4jc@virginia.edu assert(RC1 != 0); 26212120Sar4jc@virginia.edu Rc1_sd = Mem_sw; 26312120Sar4jc@virginia.edu }}, {{ 26412120Sar4jc@virginia.edu EA = sp + ldisp; 26512120Sar4jc@virginia.edu }}); 26612120Sar4jc@virginia.edu 0x3: c_ldsp({{ 26712120Sar4jc@virginia.edu ldisp = CIMM5<4:3> << 3 | 26812120Sar4jc@virginia.edu CIMM1 << 5 | 26912120Sar4jc@virginia.edu CIMM5<2:0> << 6; 27012120Sar4jc@virginia.edu }}, {{ 27112120Sar4jc@virginia.edu assert(RC1 != 0); 27212120Sar4jc@virginia.edu Rc1_sd = Mem_sd; 27312120Sar4jc@virginia.edu }}, {{ 27412120Sar4jc@virginia.edu EA = sp + ldisp; 27512120Sar4jc@virginia.edu }}); 27612120Sar4jc@virginia.edu } 27712120Sar4jc@virginia.edu 0x4: decode CFUNCT1 { 27812120Sar4jc@virginia.edu 0x0: decode RC2 { 27912120Sar4jc@virginia.edu 0x0: Jump::c_jr({{ 28012120Sar4jc@virginia.edu assert(RC1 != 0); 28112120Sar4jc@virginia.edu NPC = Rc1; 28212120Sar4jc@virginia.edu }}, IsIndirectControl, IsUncondControl, IsCall); 28312120Sar4jc@virginia.edu default: CROp::c_mv({{ 28412120Sar4jc@virginia.edu assert(RC1 != 0); 28512120Sar4jc@virginia.edu Rc1 = Rc2; 28612120Sar4jc@virginia.edu }}); 28712120Sar4jc@virginia.edu } 28812120Sar4jc@virginia.edu 0x1: decode RC1 { 28912120Sar4jc@virginia.edu 0x0: SystemOp::c_ebreak({{ 29012120Sar4jc@virginia.edu assert(RC2 == 0); 29112120Sar4jc@virginia.edu fault = make_shared<BreakpointFault>(); 29212120Sar4jc@virginia.edu }}, IsSerializeAfter, IsNonSpeculative, No_OpClass); 29312120Sar4jc@virginia.edu default: decode RC2 { 29412120Sar4jc@virginia.edu 0x0: Jump::c_jalr({{ 29512120Sar4jc@virginia.edu assert(RC1 != 0); 29612120Sar4jc@virginia.edu ra = NPC; 29712120Sar4jc@virginia.edu NPC = Rc1; 29812120Sar4jc@virginia.edu }}, IsIndirectControl, IsUncondControl, IsCall); 29912120Sar4jc@virginia.edu default: ROp::c_add({{ 30012120Sar4jc@virginia.edu Rc1_sd = Rc1_sd + Rc2_sd; 30112120Sar4jc@virginia.edu }}); 30212120Sar4jc@virginia.edu } 30312120Sar4jc@virginia.edu } 30412120Sar4jc@virginia.edu } 30512120Sar4jc@virginia.edu format CompressedStore { 30612120Sar4jc@virginia.edu 0x5: c_fsdsp({{ 30712120Sar4jc@virginia.edu sdisp = CIMM6<5:3> << 3 | 30812120Sar4jc@virginia.edu CIMM6<2:0> << 6; 30912120Sar4jc@virginia.edu }}, {{ 31012120Sar4jc@virginia.edu Mem_ud = Fc2_bits; 31112120Sar4jc@virginia.edu }}, {{ 31212120Sar4jc@virginia.edu EA = sp + sdisp; 31312120Sar4jc@virginia.edu }}); 31412120Sar4jc@virginia.edu 0x6: c_swsp({{ 31512120Sar4jc@virginia.edu sdisp = CIMM6<5:2> << 2 | 31612120Sar4jc@virginia.edu CIMM6<1:0> << 6; 31712120Sar4jc@virginia.edu }}, {{ 31812120Sar4jc@virginia.edu Mem_uw = Rc2_uw; 31912120Sar4jc@virginia.edu }}, {{ 32012120Sar4jc@virginia.edu EA = sp + sdisp; 32112120Sar4jc@virginia.edu }}); 32212120Sar4jc@virginia.edu 0x7: c_sdsp({{ 32312120Sar4jc@virginia.edu sdisp = CIMM6<5:3> << 3 | 32412120Sar4jc@virginia.edu CIMM6<2:0> << 6; 32512120Sar4jc@virginia.edu }}, {{ 32612120Sar4jc@virginia.edu Mem = Rc2; 32712120Sar4jc@virginia.edu }}, {{ 32812120Sar4jc@virginia.edu EA = sp + sdisp; 32911725Sar4jc@virginia.edu }}); 33011725Sar4jc@virginia.edu } 33111725Sar4jc@virginia.edu } 33212120Sar4jc@virginia.edu 0x3: decode OPCODE { 33312120Sar4jc@virginia.edu 0x00: decode FUNCT3 { 33412120Sar4jc@virginia.edu format Load { 33512120Sar4jc@virginia.edu 0x0: lb({{ 33612120Sar4jc@virginia.edu Rd_sd = Mem_sb; 33711723Sar4jc@virginia.edu }}); 33812120Sar4jc@virginia.edu 0x1: lh({{ 33912120Sar4jc@virginia.edu Rd_sd = Mem_sh; 34011723Sar4jc@virginia.edu }}); 34112120Sar4jc@virginia.edu 0x2: lw({{ 34212120Sar4jc@virginia.edu Rd_sd = Mem_sw; 34311723Sar4jc@virginia.edu }}); 34412120Sar4jc@virginia.edu 0x3: ld({{ 34512120Sar4jc@virginia.edu Rd_sd = Mem_sd; 34612120Sar4jc@virginia.edu }}); 34712120Sar4jc@virginia.edu 0x4: lbu({{ 34812120Sar4jc@virginia.edu Rd = Mem_ub; 34912120Sar4jc@virginia.edu }}); 35012120Sar4jc@virginia.edu 0x5: lhu({{ 35112120Sar4jc@virginia.edu Rd = Mem_uh; 35212120Sar4jc@virginia.edu }}); 35312120Sar4jc@virginia.edu 0x6: lwu({{ 35412120Sar4jc@virginia.edu Rd = Mem_uw; 35511723Sar4jc@virginia.edu }}); 35611723Sar4jc@virginia.edu } 35711723Sar4jc@virginia.edu } 35811723Sar4jc@virginia.edu 35912120Sar4jc@virginia.edu 0x01: decode FUNCT3 { 36012120Sar4jc@virginia.edu format Load { 36112120Sar4jc@virginia.edu 0x2: flw({{ 36212120Sar4jc@virginia.edu Fd_bits = (uint64_t)Mem_uw; 36312120Sar4jc@virginia.edu }}); 36412120Sar4jc@virginia.edu 0x3: fld({{ 36512120Sar4jc@virginia.edu Fd_bits = Mem; 36612120Sar4jc@virginia.edu }}); 36711726Sar4jc@virginia.edu } 36811726Sar4jc@virginia.edu } 36912120Sar4jc@virginia.edu 37012120Sar4jc@virginia.edu 0x03: decode FUNCT3 { 37112120Sar4jc@virginia.edu format IOp { 37212120Sar4jc@virginia.edu 0x0: fence({{ 37312120Sar4jc@virginia.edu }}, IsNonSpeculative, IsMemBarrier, No_OpClass); 37412120Sar4jc@virginia.edu 0x1: fence_i({{ 37512120Sar4jc@virginia.edu }}, IsNonSpeculative, IsSerializeAfter, No_OpClass); 37611726Sar4jc@virginia.edu } 37711726Sar4jc@virginia.edu } 37812120Sar4jc@virginia.edu 37912120Sar4jc@virginia.edu 0x04: decode FUNCT3 { 38012120Sar4jc@virginia.edu format IOp { 38112120Sar4jc@virginia.edu 0x0: addi({{ 38212120Sar4jc@virginia.edu Rd_sd = Rs1_sd + imm; 38311723Sar4jc@virginia.edu }}); 38412120Sar4jc@virginia.edu 0x1: slli({{ 38512120Sar4jc@virginia.edu Rd = Rs1 << SHAMT6; 38612120Sar4jc@virginia.edu }}); 38712120Sar4jc@virginia.edu 0x2: slti({{ 38812120Sar4jc@virginia.edu Rd = (Rs1_sd < imm) ? 1 : 0; 38912120Sar4jc@virginia.edu }}); 39012120Sar4jc@virginia.edu 0x3: sltiu({{ 39112120Sar4jc@virginia.edu Rd = (Rs1 < (uint64_t)imm) ? 1 : 0; 39212120Sar4jc@virginia.edu }}); 39312120Sar4jc@virginia.edu 0x4: xori({{ 39412120Sar4jc@virginia.edu Rd = Rs1 ^ (uint64_t)imm; 39512120Sar4jc@virginia.edu }}); 39612120Sar4jc@virginia.edu 0x5: decode SRTYPE { 39712120Sar4jc@virginia.edu 0x0: srli({{ 39812120Sar4jc@virginia.edu Rd = Rs1 >> SHAMT6; 39912120Sar4jc@virginia.edu }}); 40012120Sar4jc@virginia.edu 0x1: srai({{ 40112120Sar4jc@virginia.edu Rd_sd = Rs1_sd >> SHAMT6; 40212120Sar4jc@virginia.edu }}); 40312120Sar4jc@virginia.edu } 40412120Sar4jc@virginia.edu 0x6: ori({{ 40512120Sar4jc@virginia.edu Rd = Rs1 | (uint64_t)imm; 40612120Sar4jc@virginia.edu }}); 40712120Sar4jc@virginia.edu 0x7: andi({{ 40812120Sar4jc@virginia.edu Rd = Rs1 & (uint64_t)imm; 40911723Sar4jc@virginia.edu }}); 41011723Sar4jc@virginia.edu } 41112120Sar4jc@virginia.edu } 41212120Sar4jc@virginia.edu 41312120Sar4jc@virginia.edu 0x05: UOp::auipc({{ 41412120Sar4jc@virginia.edu Rd = PC + imm; 41512120Sar4jc@virginia.edu }}); 41612120Sar4jc@virginia.edu 41712120Sar4jc@virginia.edu 0x06: decode FUNCT3 { 41812120Sar4jc@virginia.edu format IOp { 41912120Sar4jc@virginia.edu 0x0: addiw({{ 42012120Sar4jc@virginia.edu Rd_sd = (int32_t)Rs1 + (int32_t)imm; 42111723Sar4jc@virginia.edu }}); 42212120Sar4jc@virginia.edu 0x1: slliw({{ 42312120Sar4jc@virginia.edu Rd_sd = Rs1_sw << SHAMT5; 42412120Sar4jc@virginia.edu }}); 42512120Sar4jc@virginia.edu 0x5: decode SRTYPE { 42612120Sar4jc@virginia.edu 0x0: srliw({{ 42712120Sar4jc@virginia.edu Rd = Rs1_uw >> SHAMT5; 42812120Sar4jc@virginia.edu }}); 42912120Sar4jc@virginia.edu 0x1: sraiw({{ 43012120Sar4jc@virginia.edu Rd_sd = Rs1_sw >> SHAMT5; 43112120Sar4jc@virginia.edu }}); 43212120Sar4jc@virginia.edu } 43312120Sar4jc@virginia.edu } 43412120Sar4jc@virginia.edu } 43511724Sar4jc@virginia.edu 43612120Sar4jc@virginia.edu 0x08: decode FUNCT3 { 43712120Sar4jc@virginia.edu format Store { 43812120Sar4jc@virginia.edu 0x0: sb({{ 43912120Sar4jc@virginia.edu Mem_ub = Rs2_ub; 44012120Sar4jc@virginia.edu }}); 44112120Sar4jc@virginia.edu 0x1: sh({{ 44212120Sar4jc@virginia.edu Mem_uh = Rs2_uh; 44312120Sar4jc@virginia.edu }}); 44412120Sar4jc@virginia.edu 0x2: sw({{ 44512120Sar4jc@virginia.edu Mem_uw = Rs2_uw; 44612120Sar4jc@virginia.edu }}); 44712120Sar4jc@virginia.edu 0x3: sd({{ 44812120Sar4jc@virginia.edu Mem_ud = Rs2_ud; 44912120Sar4jc@virginia.edu }}); 45012120Sar4jc@virginia.edu } 45112120Sar4jc@virginia.edu } 45211724Sar4jc@virginia.edu 45312120Sar4jc@virginia.edu 0x09: decode FUNCT3 { 45412120Sar4jc@virginia.edu format Store { 45512120Sar4jc@virginia.edu 0x2: fsw({{ 45612120Sar4jc@virginia.edu Mem_uw = (uint32_t)Fs2_bits; 45712120Sar4jc@virginia.edu }}); 45812120Sar4jc@virginia.edu 0x3: fsd({{ 45912120Sar4jc@virginia.edu Mem_ud = Fs2_bits; 46012120Sar4jc@virginia.edu }}); 46112120Sar4jc@virginia.edu } 46212120Sar4jc@virginia.edu } 46311724Sar4jc@virginia.edu 46412120Sar4jc@virginia.edu 0x0b: decode FUNCT3 { 46512120Sar4jc@virginia.edu 0x2: decode AMOFUNCT { 46612120Sar4jc@virginia.edu 0x2: LoadReserved::lr_w({{ 46712120Sar4jc@virginia.edu Rd_sd = Mem_sw; 46812120Sar4jc@virginia.edu }}, mem_flags=LLSC); 46912120Sar4jc@virginia.edu 0x3: StoreCond::sc_w({{ 47012120Sar4jc@virginia.edu Mem_uw = Rs2_uw; 47112120Sar4jc@virginia.edu }}, {{ 47212120Sar4jc@virginia.edu Rd = result; 47312120Sar4jc@virginia.edu }}, inst_flags=IsStoreConditional, mem_flags=LLSC); 47412120Sar4jc@virginia.edu format AtomicMemOp { 47512120Sar4jc@virginia.edu 0x0: amoadd_w({{Rt_sd = Mem_sw;}}, {{ 47612120Sar4jc@virginia.edu Mem_sw = Rs2_sw + Rt_sd; 47712120Sar4jc@virginia.edu Rd_sd = Rt_sd; 47812120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 47912120Sar4jc@virginia.edu 0x1: amoswap_w({{Rt_sd = Mem_sw;}}, {{ 48012120Sar4jc@virginia.edu Mem_sw = Rs2_uw; 48112120Sar4jc@virginia.edu Rd_sd = Rt_sd; 48212120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 48312120Sar4jc@virginia.edu 0x4: amoxor_w({{Rt_sd = Mem_sw;}}, {{ 48412120Sar4jc@virginia.edu Mem_sw = Rs2_uw^Rt_sd; 48512120Sar4jc@virginia.edu Rd_sd = Rt_sd; 48612120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 48712120Sar4jc@virginia.edu 0x8: amoor_w({{Rt_sd = Mem_sw;}}, {{ 48812120Sar4jc@virginia.edu Mem_sw = Rs2_uw | Rt_sd; 48912120Sar4jc@virginia.edu Rd_sd = Rt_sd; 49012120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 49112120Sar4jc@virginia.edu 0xc: amoand_w({{Rt_sd = Mem_sw;}}, {{ 49212120Sar4jc@virginia.edu Mem_sw = Rs2_uw&Rt_sd; 49312120Sar4jc@virginia.edu Rd_sd = Rt_sd; 49412120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 49512120Sar4jc@virginia.edu 0x10: amomin_w({{Rt_sd = Mem_sw;}}, {{ 49612120Sar4jc@virginia.edu Mem_sw = min<int32_t>(Rs2_sw, Rt_sd); 49712120Sar4jc@virginia.edu Rd_sd = Rt_sd; 49812120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 49912120Sar4jc@virginia.edu 0x14: amomax_w({{Rt_sd = Mem_sw;}}, {{ 50012120Sar4jc@virginia.edu Mem_sw = max<int32_t>(Rs2_sw, Rt_sd); 50112120Sar4jc@virginia.edu Rd_sd = Rt_sd; 50212120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 50312120Sar4jc@virginia.edu 0x18: amominu_w({{Rt_sd = Mem_sw;}}, {{ 50412120Sar4jc@virginia.edu Mem_sw = min<uint32_t>(Rs2_uw, Rt_sd); 50512120Sar4jc@virginia.edu Rd_sd = Rt_sd; 50612120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 50712120Sar4jc@virginia.edu 0x1c: amomaxu_w({{Rt_sd = Mem_sw;}}, {{ 50812120Sar4jc@virginia.edu Mem_sw = max<uint32_t>(Rs2_uw, Rt_sd); 50912120Sar4jc@virginia.edu Rd_sd = Rt_sd; 51012120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 51112120Sar4jc@virginia.edu } 51211723Sar4jc@virginia.edu } 51312120Sar4jc@virginia.edu 0x3: decode AMOFUNCT { 51412120Sar4jc@virginia.edu 0x2: LoadReserved::lr_d({{ 51512120Sar4jc@virginia.edu Rd_sd = Mem_sd; 51612120Sar4jc@virginia.edu }}, mem_flags=LLSC); 51712120Sar4jc@virginia.edu 0x3: StoreCond::sc_d({{ 51812120Sar4jc@virginia.edu Mem = Rs2; 51912120Sar4jc@virginia.edu }}, {{ 52012120Sar4jc@virginia.edu Rd = result; 52112120Sar4jc@virginia.edu }}, mem_flags=LLSC, inst_flags=IsStoreConditional); 52212120Sar4jc@virginia.edu format AtomicMemOp { 52312120Sar4jc@virginia.edu 0x0: amoadd_d({{Rt_sd = Mem_sd;}}, {{ 52412120Sar4jc@virginia.edu Mem_sd = Rs2_sd + Rt_sd; 52512120Sar4jc@virginia.edu Rd_sd = Rt_sd; 52612120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 52712120Sar4jc@virginia.edu 0x1: amoswap_d({{Rt = Mem;}}, {{ 52812120Sar4jc@virginia.edu Mem = Rs2; 52912120Sar4jc@virginia.edu Rd = Rt; 53012120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 53112120Sar4jc@virginia.edu 0x4: amoxor_d({{Rt = Mem;}}, {{ 53212120Sar4jc@virginia.edu Mem = Rs2^Rt; 53312120Sar4jc@virginia.edu Rd = Rt; 53412120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 53512120Sar4jc@virginia.edu 0x8: amoor_d({{Rt = Mem;}}, {{ 53612120Sar4jc@virginia.edu Mem = Rs2 | Rt; 53712120Sar4jc@virginia.edu Rd = Rt; 53812120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 53912120Sar4jc@virginia.edu 0xc: amoand_d({{Rt = Mem;}}, {{ 54012120Sar4jc@virginia.edu Mem = Rs2&Rt; 54112120Sar4jc@virginia.edu Rd = Rt; 54212120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 54312120Sar4jc@virginia.edu 0x10: amomin_d({{Rt_sd = Mem_sd;}}, {{ 54412120Sar4jc@virginia.edu Mem_sd = min(Rs2_sd, Rt_sd); 54512120Sar4jc@virginia.edu Rd_sd = Rt_sd; 54612120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 54712120Sar4jc@virginia.edu 0x14: amomax_d({{Rt_sd = Mem_sd;}}, {{ 54812120Sar4jc@virginia.edu Mem_sd = max(Rs2_sd, Rt_sd); 54912120Sar4jc@virginia.edu Rd_sd = Rt_sd; 55012120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 55112120Sar4jc@virginia.edu 0x18: amominu_d({{Rt = Mem;}}, {{ 55212120Sar4jc@virginia.edu Mem = min(Rs2, Rt); 55312120Sar4jc@virginia.edu Rd = Rt; 55412120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 55512120Sar4jc@virginia.edu 0x1c: amomaxu_d({{Rt = Mem;}}, {{ 55612120Sar4jc@virginia.edu Mem = max(Rs2, Rt); 55712120Sar4jc@virginia.edu Rd = Rt; 55812120Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 55912120Sar4jc@virginia.edu } 56012120Sar4jc@virginia.edu } 56112120Sar4jc@virginia.edu } 56212120Sar4jc@virginia.edu 0x0c: decode FUNCT3 { 56312120Sar4jc@virginia.edu format ROp { 56412120Sar4jc@virginia.edu 0x0: decode FUNCT7 { 56512120Sar4jc@virginia.edu 0x0: add({{ 56612120Sar4jc@virginia.edu Rd = Rs1_sd + Rs2_sd; 56712120Sar4jc@virginia.edu }}); 56812120Sar4jc@virginia.edu 0x1: mul({{ 56912120Sar4jc@virginia.edu Rd = Rs1_sd*Rs2_sd; 57012120Sar4jc@virginia.edu }}, IntMultOp); 57112120Sar4jc@virginia.edu 0x20: sub({{ 57212120Sar4jc@virginia.edu Rd = Rs1_sd - Rs2_sd; 57312120Sar4jc@virginia.edu }}); 57412120Sar4jc@virginia.edu } 57512120Sar4jc@virginia.edu 0x1: decode FUNCT7 { 57612120Sar4jc@virginia.edu 0x0: sll({{ 57712120Sar4jc@virginia.edu Rd = Rs1 << Rs2<5:0>; 57812120Sar4jc@virginia.edu }}); 57912120Sar4jc@virginia.edu 0x1: mulh({{ 58012120Sar4jc@virginia.edu bool negate = (Rs1_sd < 0) != (Rs2_sd < 0); 58112120Sar4jc@virginia.edu 58212120Sar4jc@virginia.edu uint64_t Rs1_lo = (uint32_t)abs(Rs1_sd); 58312120Sar4jc@virginia.edu uint64_t Rs1_hi = (uint64_t)abs(Rs1_sd) >> 32; 58412120Sar4jc@virginia.edu uint64_t Rs2_lo = (uint32_t)abs(Rs2_sd); 58512120Sar4jc@virginia.edu uint64_t Rs2_hi = (uint64_t)abs(Rs2_sd) >> 32; 58612120Sar4jc@virginia.edu 58712120Sar4jc@virginia.edu uint64_t hi = Rs1_hi*Rs2_hi; 58812120Sar4jc@virginia.edu uint64_t mid1 = Rs1_hi*Rs2_lo; 58912120Sar4jc@virginia.edu uint64_t mid2 = Rs1_lo*Rs2_hi; 59012120Sar4jc@virginia.edu uint64_t lo = Rs2_lo*Rs1_lo; 59112120Sar4jc@virginia.edu uint64_t carry = ((uint64_t)(uint32_t)mid1 59212120Sar4jc@virginia.edu + (uint64_t)(uint32_t)mid2 + (lo >> 32)) >> 32; 59312120Sar4jc@virginia.edu 59412120Sar4jc@virginia.edu uint64_t res = hi + 59512120Sar4jc@virginia.edu (mid1 >> 32) + 59612120Sar4jc@virginia.edu (mid2 >> 32) + 59712120Sar4jc@virginia.edu carry; 59812120Sar4jc@virginia.edu Rd = negate ? ~res + (Rs1_sd*Rs2_sd == 0 ? 1 : 0) 59912120Sar4jc@virginia.edu : res; 60012120Sar4jc@virginia.edu }}, IntMultOp); 60112120Sar4jc@virginia.edu } 60212120Sar4jc@virginia.edu 0x2: decode FUNCT7 { 60312120Sar4jc@virginia.edu 0x0: slt({{ 60412120Sar4jc@virginia.edu Rd = (Rs1_sd < Rs2_sd) ? 1 : 0; 60512120Sar4jc@virginia.edu }}); 60612120Sar4jc@virginia.edu 0x1: mulhsu({{ 60712120Sar4jc@virginia.edu bool negate = Rs1_sd < 0; 60812120Sar4jc@virginia.edu uint64_t Rs1_lo = (uint32_t)abs(Rs1_sd); 60912120Sar4jc@virginia.edu uint64_t Rs1_hi = (uint64_t)abs(Rs1_sd) >> 32; 61012120Sar4jc@virginia.edu uint64_t Rs2_lo = (uint32_t)Rs2; 61112120Sar4jc@virginia.edu uint64_t Rs2_hi = Rs2 >> 32; 61212120Sar4jc@virginia.edu 61312120Sar4jc@virginia.edu uint64_t hi = Rs1_hi*Rs2_hi; 61412120Sar4jc@virginia.edu uint64_t mid1 = Rs1_hi*Rs2_lo; 61512120Sar4jc@virginia.edu uint64_t mid2 = Rs1_lo*Rs2_hi; 61612120Sar4jc@virginia.edu uint64_t lo = Rs1_lo*Rs2_lo; 61712120Sar4jc@virginia.edu uint64_t carry = ((uint64_t)(uint32_t)mid1 61812120Sar4jc@virginia.edu + (uint64_t)(uint32_t)mid2 + (lo >> 32)) >> 32; 61912120Sar4jc@virginia.edu 62012120Sar4jc@virginia.edu uint64_t res = hi + 62112120Sar4jc@virginia.edu (mid1 >> 32) + 62212120Sar4jc@virginia.edu (mid2 >> 32) + 62312120Sar4jc@virginia.edu carry; 62412120Sar4jc@virginia.edu Rd = negate ? ~res + (Rs1_sd*Rs2 == 0 ? 1 : 0) : res; 62512120Sar4jc@virginia.edu }}, IntMultOp); 62612120Sar4jc@virginia.edu } 62712120Sar4jc@virginia.edu 0x3: decode FUNCT7 { 62812120Sar4jc@virginia.edu 0x0: sltu({{ 62912120Sar4jc@virginia.edu Rd = (Rs1 < Rs2) ? 1 : 0; 63012120Sar4jc@virginia.edu }}); 63112120Sar4jc@virginia.edu 0x1: mulhu({{ 63212120Sar4jc@virginia.edu uint64_t Rs1_lo = (uint32_t)Rs1; 63312120Sar4jc@virginia.edu uint64_t Rs1_hi = Rs1 >> 32; 63412120Sar4jc@virginia.edu uint64_t Rs2_lo = (uint32_t)Rs2; 63512120Sar4jc@virginia.edu uint64_t Rs2_hi = Rs2 >> 32; 63612120Sar4jc@virginia.edu 63712120Sar4jc@virginia.edu uint64_t hi = Rs1_hi*Rs2_hi; 63812120Sar4jc@virginia.edu uint64_t mid1 = Rs1_hi*Rs2_lo; 63912120Sar4jc@virginia.edu uint64_t mid2 = Rs1_lo*Rs2_hi; 64012120Sar4jc@virginia.edu uint64_t lo = Rs1_lo*Rs2_lo; 64112120Sar4jc@virginia.edu uint64_t carry = ((uint64_t)(uint32_t)mid1 64212120Sar4jc@virginia.edu + (uint64_t)(uint32_t)mid2 + (lo >> 32)) >> 32; 64312120Sar4jc@virginia.edu 64412120Sar4jc@virginia.edu Rd = hi + (mid1 >> 32) + (mid2 >> 32) + carry; 64512120Sar4jc@virginia.edu }}, IntMultOp); 64612120Sar4jc@virginia.edu } 64712120Sar4jc@virginia.edu 0x4: decode FUNCT7 { 64812120Sar4jc@virginia.edu 0x0: xor({{ 64912120Sar4jc@virginia.edu Rd = Rs1 ^ Rs2; 65012120Sar4jc@virginia.edu }}); 65112120Sar4jc@virginia.edu 0x1: div({{ 65212120Sar4jc@virginia.edu if (Rs2_sd == 0) { 65312120Sar4jc@virginia.edu Rd_sd = -1; 65412120Sar4jc@virginia.edu } else if (Rs1_sd == numeric_limits<int64_t>::min() 65512120Sar4jc@virginia.edu && Rs2_sd == -1) { 65612120Sar4jc@virginia.edu Rd_sd = numeric_limits<int64_t>::min(); 65712120Sar4jc@virginia.edu } else { 65812120Sar4jc@virginia.edu Rd_sd = Rs1_sd/Rs2_sd; 65912120Sar4jc@virginia.edu } 66012120Sar4jc@virginia.edu }}, IntDivOp); 66112120Sar4jc@virginia.edu } 66212120Sar4jc@virginia.edu 0x5: decode FUNCT7 { 66312120Sar4jc@virginia.edu 0x0: srl({{ 66412120Sar4jc@virginia.edu Rd = Rs1 >> Rs2<5:0>; 66512120Sar4jc@virginia.edu }}); 66612120Sar4jc@virginia.edu 0x1: divu({{ 66712120Sar4jc@virginia.edu if (Rs2 == 0) { 66812120Sar4jc@virginia.edu Rd = numeric_limits<uint64_t>::max(); 66912120Sar4jc@virginia.edu } else { 67012120Sar4jc@virginia.edu Rd = Rs1/Rs2; 67112120Sar4jc@virginia.edu } 67212120Sar4jc@virginia.edu }}, IntDivOp); 67312120Sar4jc@virginia.edu 0x20: sra({{ 67412120Sar4jc@virginia.edu Rd_sd = Rs1_sd >> Rs2<5:0>; 67512120Sar4jc@virginia.edu }}); 67612120Sar4jc@virginia.edu } 67712120Sar4jc@virginia.edu 0x6: decode FUNCT7 { 67812120Sar4jc@virginia.edu 0x0: or({{ 67912120Sar4jc@virginia.edu Rd = Rs1 | Rs2; 68012120Sar4jc@virginia.edu }}); 68112120Sar4jc@virginia.edu 0x1: rem({{ 68212120Sar4jc@virginia.edu if (Rs2_sd == 0) { 68312120Sar4jc@virginia.edu Rd = Rs1_sd; 68412120Sar4jc@virginia.edu } else if (Rs1_sd == numeric_limits<int64_t>::min() 68512120Sar4jc@virginia.edu && Rs2_sd == -1) { 68612120Sar4jc@virginia.edu Rd = 0; 68712120Sar4jc@virginia.edu } else { 68812120Sar4jc@virginia.edu Rd = Rs1_sd%Rs2_sd; 68912120Sar4jc@virginia.edu } 69012120Sar4jc@virginia.edu }}, IntDivOp); 69112120Sar4jc@virginia.edu } 69212120Sar4jc@virginia.edu 0x7: decode FUNCT7 { 69312120Sar4jc@virginia.edu 0x0: and({{ 69412120Sar4jc@virginia.edu Rd = Rs1 & Rs2; 69512120Sar4jc@virginia.edu }}); 69612120Sar4jc@virginia.edu 0x1: remu({{ 69712120Sar4jc@virginia.edu if (Rs2 == 0) { 69812120Sar4jc@virginia.edu Rd = Rs1; 69912120Sar4jc@virginia.edu } else { 70012120Sar4jc@virginia.edu Rd = Rs1%Rs2; 70112120Sar4jc@virginia.edu } 70212120Sar4jc@virginia.edu }}, IntDivOp); 70312120Sar4jc@virginia.edu } 70412120Sar4jc@virginia.edu } 70512120Sar4jc@virginia.edu } 70612120Sar4jc@virginia.edu 70712120Sar4jc@virginia.edu 0x0d: UOp::lui({{ 70812120Sar4jc@virginia.edu Rd = (uint64_t)imm; 70912120Sar4jc@virginia.edu }}); 71012120Sar4jc@virginia.edu 71112120Sar4jc@virginia.edu 0x0e: decode FUNCT3 { 71212120Sar4jc@virginia.edu format ROp { 71312120Sar4jc@virginia.edu 0x0: decode FUNCT7 { 71412120Sar4jc@virginia.edu 0x0: addw({{ 71512120Sar4jc@virginia.edu Rd_sd = Rs1_sw + Rs2_sw; 71612120Sar4jc@virginia.edu }}); 71712120Sar4jc@virginia.edu 0x1: mulw({{ 71812120Sar4jc@virginia.edu Rd_sd = (int32_t)(Rs1_sw*Rs2_sw); 71912120Sar4jc@virginia.edu }}, IntMultOp); 72012120Sar4jc@virginia.edu 0x20: subw({{ 72112120Sar4jc@virginia.edu Rd_sd = Rs1_sw - Rs2_sw; 72212120Sar4jc@virginia.edu }}); 72312120Sar4jc@virginia.edu } 72412120Sar4jc@virginia.edu 0x1: sllw({{ 72512120Sar4jc@virginia.edu Rd_sd = Rs1_sw << Rs2<4:0>; 72611723Sar4jc@virginia.edu }}); 72712120Sar4jc@virginia.edu 0x4: divw({{ 72812120Sar4jc@virginia.edu if (Rs2_sw == 0) { 72911724Sar4jc@virginia.edu Rd_sd = -1; 73012120Sar4jc@virginia.edu } else if (Rs1_sw == numeric_limits<int32_t>::min() 73112120Sar4jc@virginia.edu && Rs2_sw == -1) { 73212120Sar4jc@virginia.edu Rd_sd = numeric_limits<int32_t>::min(); 73311724Sar4jc@virginia.edu } else { 73412120Sar4jc@virginia.edu Rd_sd = Rs1_sw/Rs2_sw; 73511724Sar4jc@virginia.edu } 73611724Sar4jc@virginia.edu }}, IntDivOp); 73712120Sar4jc@virginia.edu 0x5: decode FUNCT7 { 73812120Sar4jc@virginia.edu 0x0: srlw({{ 73912120Sar4jc@virginia.edu Rd_uw = Rs1_uw >> Rs2<4:0>; 74012120Sar4jc@virginia.edu }}); 74112120Sar4jc@virginia.edu 0x1: divuw({{ 74212120Sar4jc@virginia.edu if (Rs2_uw == 0) { 74312120Sar4jc@virginia.edu Rd_sd = numeric_limits<IntReg>::max(); 74412120Sar4jc@virginia.edu } else { 74512120Sar4jc@virginia.edu Rd_sd = (int32_t)(Rs1_uw/Rs2_uw); 74612120Sar4jc@virginia.edu } 74712120Sar4jc@virginia.edu }}, IntDivOp); 74812120Sar4jc@virginia.edu 0x20: sraw({{ 74912120Sar4jc@virginia.edu Rd_sd = Rs1_sw >> Rs2<4:0>; 75012120Sar4jc@virginia.edu }}); 75112120Sar4jc@virginia.edu } 75212120Sar4jc@virginia.edu 0x6: remw({{ 75312120Sar4jc@virginia.edu if (Rs2_sw == 0) { 75412120Sar4jc@virginia.edu Rd_sd = Rs1_sw; 75512120Sar4jc@virginia.edu } else if (Rs1_sw == numeric_limits<int32_t>::min() 75612120Sar4jc@virginia.edu && Rs2_sw == -1) { 75712120Sar4jc@virginia.edu Rd_sd = 0; 75811724Sar4jc@virginia.edu } else { 75912120Sar4jc@virginia.edu Rd_sd = Rs1_sw%Rs2_sw; 76011724Sar4jc@virginia.edu } 76111724Sar4jc@virginia.edu }}, IntDivOp); 76212120Sar4jc@virginia.edu 0x7: remuw({{ 76312120Sar4jc@virginia.edu if (Rs2_uw == 0) { 76412120Sar4jc@virginia.edu Rd_sd = (int32_t)Rs1_uw; 76511724Sar4jc@virginia.edu } else { 76612120Sar4jc@virginia.edu Rd_sd = (int32_t)(Rs1_uw%Rs2_uw); 76711724Sar4jc@virginia.edu } 76811724Sar4jc@virginia.edu }}, IntDivOp); 76911723Sar4jc@virginia.edu } 77011723Sar4jc@virginia.edu } 77111723Sar4jc@virginia.edu 77212120Sar4jc@virginia.edu format FPROp { 77312120Sar4jc@virginia.edu 0x10: decode FUNCT2 { 77412120Sar4jc@virginia.edu 0x0: fmadd_s({{ 77512120Sar4jc@virginia.edu uint32_t temp; 77612120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 77712120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 77812120Sar4jc@virginia.edu float fs3 = reinterpret_cast<float&>(temp = Fs3_bits); 77912120Sar4jc@virginia.edu float fd; 78011723Sar4jc@virginia.edu 78112120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2) || isnan(fs3)) { 78212120Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2) 78312120Sar4jc@virginia.edu || issignalingnan(fs3)) { 78412120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 78512120Sar4jc@virginia.edu } 78612120Sar4jc@virginia.edu fd = numeric_limits<float>::quiet_NaN(); 78712120Sar4jc@virginia.edu } else if (isinf(fs1) || isinf(fs2) || 78812120Sar4jc@virginia.edu isinf(fs3)) { 78912120Sar4jc@virginia.edu if (signbit(fs1) == signbit(fs2) 79012120Sar4jc@virginia.edu && !isinf(fs3)) { 79112120Sar4jc@virginia.edu fd = numeric_limits<float>::infinity(); 79212120Sar4jc@virginia.edu } else if (signbit(fs1) != signbit(fs2) 79312120Sar4jc@virginia.edu && !isinf(fs3)) { 79412120Sar4jc@virginia.edu fd = -numeric_limits<float>::infinity(); 79512120Sar4jc@virginia.edu } else { // Fs3_sf is infinity 79612120Sar4jc@virginia.edu fd = fs3; 79712120Sar4jc@virginia.edu } 79812120Sar4jc@virginia.edu } else { 79912120Sar4jc@virginia.edu fd = fs1*fs2 + fs3; 80012120Sar4jc@virginia.edu } 80112120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 80212120Sar4jc@virginia.edu }}, FloatMultOp); 80312120Sar4jc@virginia.edu 0x1: fmadd_d({{ 80412120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2) || isnan(Fs3)) { 80512120Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2) 80612120Sar4jc@virginia.edu || issignalingnan(Fs3)) { 80712120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 80812120Sar4jc@virginia.edu } 80912120Sar4jc@virginia.edu Fd = numeric_limits<double>::quiet_NaN(); 81012120Sar4jc@virginia.edu } else if (isinf(Fs1) || isinf(Fs2) || 81112120Sar4jc@virginia.edu isinf(Fs3)) { 81212120Sar4jc@virginia.edu if (signbit(Fs1) == signbit(Fs2) 81312120Sar4jc@virginia.edu && !isinf(Fs3)) { 81412120Sar4jc@virginia.edu Fd = numeric_limits<double>::infinity(); 81512120Sar4jc@virginia.edu } else if (signbit(Fs1) != signbit(Fs2) 81612120Sar4jc@virginia.edu && !isinf(Fs3)) { 81712120Sar4jc@virginia.edu Fd = -numeric_limits<double>::infinity(); 81812120Sar4jc@virginia.edu } else { 81912120Sar4jc@virginia.edu Fd = Fs3; 82012120Sar4jc@virginia.edu } 82112120Sar4jc@virginia.edu } else { 82212120Sar4jc@virginia.edu Fd = Fs1*Fs2 + Fs3; 82312120Sar4jc@virginia.edu } 82412120Sar4jc@virginia.edu }}, FloatMultOp); 82511723Sar4jc@virginia.edu } 82612120Sar4jc@virginia.edu 0x11: decode FUNCT2 { 82712120Sar4jc@virginia.edu 0x0: fmsub_s({{ 82812120Sar4jc@virginia.edu uint32_t temp; 82912120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 83012120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 83112120Sar4jc@virginia.edu float fs3 = reinterpret_cast<float&>(temp = Fs3_bits); 83212120Sar4jc@virginia.edu float fd; 83312120Sar4jc@virginia.edu 83412120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2) || isnan(fs3)) { 83512120Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2) 83612120Sar4jc@virginia.edu || issignalingnan(fs3)) { 83712120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 83812120Sar4jc@virginia.edu } 83912120Sar4jc@virginia.edu fd = numeric_limits<float>::quiet_NaN(); 84012120Sar4jc@virginia.edu } else if (isinf(fs1) || isinf(fs2) || 84112120Sar4jc@virginia.edu isinf(fs3)) { 84212120Sar4jc@virginia.edu if (signbit(fs1) == signbit(fs2) 84312120Sar4jc@virginia.edu && !isinf(fs3)) { 84412120Sar4jc@virginia.edu fd = numeric_limits<float>::infinity(); 84512120Sar4jc@virginia.edu } else if (signbit(fs1) != signbit(fs2) 84612120Sar4jc@virginia.edu && !isinf(fs3)) { 84712120Sar4jc@virginia.edu fd = -numeric_limits<float>::infinity(); 84812120Sar4jc@virginia.edu } else { // Fs3_sf is infinity 84912120Sar4jc@virginia.edu fd = -fs3; 85012120Sar4jc@virginia.edu } 85111724Sar4jc@virginia.edu } else { 85212120Sar4jc@virginia.edu fd = fs1*fs2 - fs3; 85311724Sar4jc@virginia.edu } 85412120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 85512120Sar4jc@virginia.edu }}, FloatMultOp); 85612120Sar4jc@virginia.edu 0x1: fmsub_d({{ 85712120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2) || isnan(Fs3)) { 85812120Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2) 85912120Sar4jc@virginia.edu || issignalingnan(Fs3)) { 86012120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 86112120Sar4jc@virginia.edu } 86212120Sar4jc@virginia.edu Fd = numeric_limits<double>::quiet_NaN(); 86312120Sar4jc@virginia.edu } else if (isinf(Fs1) || isinf(Fs2) || 86412120Sar4jc@virginia.edu isinf(Fs3)) { 86512120Sar4jc@virginia.edu if (signbit(Fs1) == signbit(Fs2) 86612120Sar4jc@virginia.edu && !isinf(Fs3)) { 86712120Sar4jc@virginia.edu Fd = numeric_limits<double>::infinity(); 86812120Sar4jc@virginia.edu } else if (signbit(Fs1) != signbit(Fs2) 86912120Sar4jc@virginia.edu && !isinf(Fs3)) { 87012120Sar4jc@virginia.edu Fd = -numeric_limits<double>::infinity(); 87112120Sar4jc@virginia.edu } else { 87212120Sar4jc@virginia.edu Fd = -Fs3; 87312120Sar4jc@virginia.edu } 87412120Sar4jc@virginia.edu } else { 87512120Sar4jc@virginia.edu Fd = Fs1*Fs2 - Fs3; 87612120Sar4jc@virginia.edu } 87712120Sar4jc@virginia.edu }}, FloatMultOp); 87811723Sar4jc@virginia.edu } 87912120Sar4jc@virginia.edu 0x12: decode FUNCT2 { 88012120Sar4jc@virginia.edu 0x0: fnmsub_s({{ 88112120Sar4jc@virginia.edu uint32_t temp; 88212120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 88312120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 88412120Sar4jc@virginia.edu float fs3 = reinterpret_cast<float&>(temp = Fs3_bits); 88512120Sar4jc@virginia.edu float fd; 88611723Sar4jc@virginia.edu 88712120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2) || isnan(fs3)) { 88812120Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2) 88912120Sar4jc@virginia.edu || issignalingnan(fs3)) { 89012120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 89112120Sar4jc@virginia.edu } 89212120Sar4jc@virginia.edu fd = numeric_limits<float>::quiet_NaN(); 89312120Sar4jc@virginia.edu } else if (isinf(fs1) || isinf(fs2) || 89412120Sar4jc@virginia.edu isinf(fs3)) { 89512120Sar4jc@virginia.edu if (signbit(fs1) == signbit(fs2) 89612120Sar4jc@virginia.edu && !isinf(fs3)) { 89712120Sar4jc@virginia.edu fd = -numeric_limits<float>::infinity(); 89812120Sar4jc@virginia.edu } else if (signbit(fs1) != signbit(fs2) 89912120Sar4jc@virginia.edu && !isinf(fs3)) { 90012120Sar4jc@virginia.edu fd = numeric_limits<float>::infinity(); 90112120Sar4jc@virginia.edu } else { // Fs3_sf is infinity 90212120Sar4jc@virginia.edu fd = fs3; 90312120Sar4jc@virginia.edu } 90412120Sar4jc@virginia.edu } else { 90512120Sar4jc@virginia.edu fd = -(fs1*fs2 - fs3); 90612120Sar4jc@virginia.edu } 90712120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 90812120Sar4jc@virginia.edu }}, FloatMultOp); 90912120Sar4jc@virginia.edu 0x1: fnmsub_d({{ 91012120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2) || isnan(Fs3)) { 91112120Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2) 91212120Sar4jc@virginia.edu || issignalingnan(Fs3)) { 91312120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 91412120Sar4jc@virginia.edu } 91512120Sar4jc@virginia.edu Fd = numeric_limits<double>::quiet_NaN(); 91612120Sar4jc@virginia.edu } else if (isinf(Fs1) || isinf(Fs2) 91712120Sar4jc@virginia.edu || isinf(Fs3)) { 91812120Sar4jc@virginia.edu if (signbit(Fs1) == signbit(Fs2) 91912120Sar4jc@virginia.edu && !isinf(Fs3)) { 92012120Sar4jc@virginia.edu Fd = -numeric_limits<double>::infinity(); 92112120Sar4jc@virginia.edu } else if (signbit(Fs1) != signbit(Fs2) 92212120Sar4jc@virginia.edu && !isinf(Fs3)) { 92312120Sar4jc@virginia.edu Fd = numeric_limits<double>::infinity(); 92412120Sar4jc@virginia.edu } else { 92512120Sar4jc@virginia.edu Fd = Fs3; 92612120Sar4jc@virginia.edu } 92712120Sar4jc@virginia.edu } else { 92812120Sar4jc@virginia.edu Fd = -(Fs1*Fs2 - Fs3); 92912120Sar4jc@virginia.edu } 93012120Sar4jc@virginia.edu }}, FloatMultOp); 93112120Sar4jc@virginia.edu } 93212120Sar4jc@virginia.edu 0x13: decode FUNCT2 { 93312120Sar4jc@virginia.edu 0x0: fnmadd_s({{ 93412120Sar4jc@virginia.edu uint32_t temp; 93512120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 93612120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 93712120Sar4jc@virginia.edu float fs3 = reinterpret_cast<float&>(temp = Fs3_bits); 93812120Sar4jc@virginia.edu float fd; 93911725Sar4jc@virginia.edu 94012120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2) || isnan(fs3)) { 94112120Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2) 94212120Sar4jc@virginia.edu || issignalingnan(fs3)) { 94312120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 94412120Sar4jc@virginia.edu } 94512120Sar4jc@virginia.edu fd = numeric_limits<float>::quiet_NaN(); 94612120Sar4jc@virginia.edu } else if (isinf(fs1) || isinf(fs2) || 94712120Sar4jc@virginia.edu isinf(fs3)) { 94812120Sar4jc@virginia.edu if (signbit(fs1) == signbit(fs2) 94912120Sar4jc@virginia.edu && !isinf(fs3)) { 95012120Sar4jc@virginia.edu fd = -numeric_limits<float>::infinity(); 95112120Sar4jc@virginia.edu } else if (signbit(fs1) != signbit(fs2) 95212120Sar4jc@virginia.edu && !isinf(fs3)) { 95312120Sar4jc@virginia.edu fd = numeric_limits<float>::infinity(); 95412120Sar4jc@virginia.edu } else { // Fs3_sf is infinity 95512120Sar4jc@virginia.edu fd = -fs3; 95612120Sar4jc@virginia.edu } 95712120Sar4jc@virginia.edu } else { 95812120Sar4jc@virginia.edu fd = -(fs1*fs2 + fs3); 95911725Sar4jc@virginia.edu } 96012120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 96112120Sar4jc@virginia.edu }}, FloatMultOp); 96212120Sar4jc@virginia.edu 0x1: fnmadd_d({{ 96312120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2) || isnan(Fs3)) { 96412120Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2) 96512120Sar4jc@virginia.edu || issignalingnan(Fs3)) { 96612120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 96712120Sar4jc@virginia.edu } 96812120Sar4jc@virginia.edu Fd = numeric_limits<double>::quiet_NaN(); 96912120Sar4jc@virginia.edu } else if (isinf(Fs1) || isinf(Fs2) || 97012120Sar4jc@virginia.edu isinf(Fs3)) { 97112120Sar4jc@virginia.edu if (signbit(Fs1) == signbit(Fs2) 97212120Sar4jc@virginia.edu && !isinf(Fs3)) { 97312120Sar4jc@virginia.edu Fd = -numeric_limits<double>::infinity(); 97412120Sar4jc@virginia.edu } else if (signbit(Fs1) != signbit(Fs2) 97512120Sar4jc@virginia.edu && !isinf(Fs3)) { 97612120Sar4jc@virginia.edu Fd = numeric_limits<double>::infinity(); 97712120Sar4jc@virginia.edu } else { 97812120Sar4jc@virginia.edu Fd = -Fs3; 97912120Sar4jc@virginia.edu } 98012120Sar4jc@virginia.edu } else { 98112120Sar4jc@virginia.edu Fd = -(Fs1*Fs2 + Fs3); 98211725Sar4jc@virginia.edu } 98312120Sar4jc@virginia.edu }}, FloatMultOp); 98412120Sar4jc@virginia.edu } 98512120Sar4jc@virginia.edu 0x14: decode FUNCT7 { 98612120Sar4jc@virginia.edu 0x0: fadd_s({{ 98711725Sar4jc@virginia.edu uint32_t temp; 98811725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 98911725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 99011725Sar4jc@virginia.edu float fd; 99111725Sar4jc@virginia.edu 99212120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2)) { 99312120Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2)) { 99412120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 99512120Sar4jc@virginia.edu } 99612120Sar4jc@virginia.edu fd = numeric_limits<float>::quiet_NaN(); 99711725Sar4jc@virginia.edu } else { 99812120Sar4jc@virginia.edu fd = fs1 + fs2; 99911725Sar4jc@virginia.edu } 100011725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 100112120Sar4jc@virginia.edu }}, FloatAddOp); 100212120Sar4jc@virginia.edu 0x1: fadd_d({{ 100312120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2)) { 100412120Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2)) { 100512120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 100612120Sar4jc@virginia.edu } 100712120Sar4jc@virginia.edu Fd = numeric_limits<double>::quiet_NaN(); 100812120Sar4jc@virginia.edu } else { 100912120Sar4jc@virginia.edu Fd = Fs1 + Fs2; 101012120Sar4jc@virginia.edu } 101112120Sar4jc@virginia.edu }}, FloatAddOp); 101212120Sar4jc@virginia.edu 0x4: fsub_s({{ 101311725Sar4jc@virginia.edu uint32_t temp; 101411725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 101511725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 101611725Sar4jc@virginia.edu float fd; 101711725Sar4jc@virginia.edu 101812120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2)) { 101912120Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2)) { 102012120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 102112120Sar4jc@virginia.edu } 102212120Sar4jc@virginia.edu fd = numeric_limits<float>::quiet_NaN(); 102311725Sar4jc@virginia.edu } else { 102412120Sar4jc@virginia.edu fd = fs1 - fs2; 102511725Sar4jc@virginia.edu } 102611725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 102712120Sar4jc@virginia.edu }}, FloatAddOp); 102812120Sar4jc@virginia.edu 0x5: fsub_d({{ 102912120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2)) { 103012120Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2)) { 103112120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 103212120Sar4jc@virginia.edu } 103312120Sar4jc@virginia.edu Fd = numeric_limits<double>::quiet_NaN(); 103412120Sar4jc@virginia.edu } else { 103512120Sar4jc@virginia.edu Fd = Fs1 - Fs2; 103612120Sar4jc@virginia.edu } 103712120Sar4jc@virginia.edu }}, FloatAddOp); 103812120Sar4jc@virginia.edu 0x8: fmul_s({{ 103911725Sar4jc@virginia.edu uint32_t temp; 104011725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 104111725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 104211725Sar4jc@virginia.edu float fd; 104311725Sar4jc@virginia.edu 104412120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2)) { 104512120Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2)) { 104612120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 104712120Sar4jc@virginia.edu } 104812120Sar4jc@virginia.edu fd = numeric_limits<float>::quiet_NaN(); 104911725Sar4jc@virginia.edu } else { 105012120Sar4jc@virginia.edu fd = fs1*fs2; 105111725Sar4jc@virginia.edu } 105211725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 105312120Sar4jc@virginia.edu }}, FloatMultOp); 105412120Sar4jc@virginia.edu 0x9: fmul_d({{ 105512120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2)) { 105612120Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2)) { 105712120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 105812120Sar4jc@virginia.edu } 105912120Sar4jc@virginia.edu Fd = numeric_limits<double>::quiet_NaN(); 106011725Sar4jc@virginia.edu } else { 106112120Sar4jc@virginia.edu Fd = Fs1*Fs2; 106211725Sar4jc@virginia.edu } 106312120Sar4jc@virginia.edu }}, FloatMultOp); 106412120Sar4jc@virginia.edu 0xc: fdiv_s({{ 106511725Sar4jc@virginia.edu uint32_t temp; 106611725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 106711725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 106811725Sar4jc@virginia.edu float fd; 106911725Sar4jc@virginia.edu 107012120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2)) { 107112120Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2)) { 107212120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 107312120Sar4jc@virginia.edu } 107412120Sar4jc@virginia.edu fd = numeric_limits<float>::quiet_NaN(); 107512120Sar4jc@virginia.edu } else { 107612120Sar4jc@virginia.edu fd = fs1/fs2; 107712120Sar4jc@virginia.edu } 107812120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 107912120Sar4jc@virginia.edu }}, FloatDivOp); 108012120Sar4jc@virginia.edu 0xd: fdiv_d({{ 108112120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2)) { 108212120Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2)) { 108312120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 108412120Sar4jc@virginia.edu } 108512120Sar4jc@virginia.edu Fd = numeric_limits<double>::quiet_NaN(); 108612120Sar4jc@virginia.edu } else { 108712120Sar4jc@virginia.edu Fd = Fs1/Fs2; 108812120Sar4jc@virginia.edu } 108912120Sar4jc@virginia.edu }}, FloatDivOp); 109012120Sar4jc@virginia.edu 0x10: decode ROUND_MODE { 109112120Sar4jc@virginia.edu 0x0: fsgnj_s({{ 109212120Sar4jc@virginia.edu uint32_t temp; 109312120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 109412120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 109512120Sar4jc@virginia.edu float fd; 109612120Sar4jc@virginia.edu 109712120Sar4jc@virginia.edu if (issignalingnan(fs1)) { 109812120Sar4jc@virginia.edu fd = numeric_limits<float>::signaling_NaN(); 109912120Sar4jc@virginia.edu feclearexcept(FE_INVALID); 110012120Sar4jc@virginia.edu } else { 110112120Sar4jc@virginia.edu fd = copysign(fs1, fs2); 110212120Sar4jc@virginia.edu } 110312120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 110412120Sar4jc@virginia.edu }}); 110512120Sar4jc@virginia.edu 0x1: fsgnjn_s({{ 110612120Sar4jc@virginia.edu uint32_t temp; 110712120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 110812120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 110912120Sar4jc@virginia.edu float fd; 111012120Sar4jc@virginia.edu 111112120Sar4jc@virginia.edu if (issignalingnan(fs1)) { 111212120Sar4jc@virginia.edu fd = numeric_limits<float>::signaling_NaN(); 111312120Sar4jc@virginia.edu feclearexcept(FE_INVALID); 111412120Sar4jc@virginia.edu } else { 111512120Sar4jc@virginia.edu fd = copysign(fs1, -fs2); 111612120Sar4jc@virginia.edu } 111712120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 111812120Sar4jc@virginia.edu }}); 111912120Sar4jc@virginia.edu 0x2: fsgnjx_s({{ 112012120Sar4jc@virginia.edu uint32_t temp; 112112120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 112212120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 112312120Sar4jc@virginia.edu float fd; 112412120Sar4jc@virginia.edu 112512120Sar4jc@virginia.edu if (issignalingnan(fs1)) { 112612120Sar4jc@virginia.edu fd = numeric_limits<float>::signaling_NaN(); 112712120Sar4jc@virginia.edu feclearexcept(FE_INVALID); 112812120Sar4jc@virginia.edu } else { 112912120Sar4jc@virginia.edu fd = fs1*(signbit(fs2) ? -1.0 : 1.0); 113012120Sar4jc@virginia.edu } 113112120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 113212120Sar4jc@virginia.edu }}); 113312120Sar4jc@virginia.edu } 113412120Sar4jc@virginia.edu 0x11: decode ROUND_MODE { 113512120Sar4jc@virginia.edu 0x0: fsgnj_d({{ 113612120Sar4jc@virginia.edu if (issignalingnan(Fs1)) { 113712120Sar4jc@virginia.edu Fd = numeric_limits<double>::signaling_NaN(); 113812120Sar4jc@virginia.edu feclearexcept(FE_INVALID); 113912120Sar4jc@virginia.edu } else { 114012120Sar4jc@virginia.edu Fd = copysign(Fs1, Fs2); 114112120Sar4jc@virginia.edu } 114212120Sar4jc@virginia.edu }}); 114312120Sar4jc@virginia.edu 0x1: fsgnjn_d({{ 114412120Sar4jc@virginia.edu if (issignalingnan(Fs1)) { 114512120Sar4jc@virginia.edu Fd = numeric_limits<double>::signaling_NaN(); 114612120Sar4jc@virginia.edu feclearexcept(FE_INVALID); 114712120Sar4jc@virginia.edu } else { 114812120Sar4jc@virginia.edu Fd = copysign(Fs1, -Fs2); 114912120Sar4jc@virginia.edu } 115012120Sar4jc@virginia.edu }}); 115112120Sar4jc@virginia.edu 0x2: fsgnjx_d({{ 115212120Sar4jc@virginia.edu if (issignalingnan(Fs1)) { 115312120Sar4jc@virginia.edu Fd = numeric_limits<double>::signaling_NaN(); 115412120Sar4jc@virginia.edu feclearexcept(FE_INVALID); 115512120Sar4jc@virginia.edu } else { 115612120Sar4jc@virginia.edu Fd = Fs1*(signbit(Fs2) ? -1.0 : 1.0); 115712120Sar4jc@virginia.edu } 115812120Sar4jc@virginia.edu }}); 115912120Sar4jc@virginia.edu } 116012120Sar4jc@virginia.edu 0x14: decode ROUND_MODE { 116112120Sar4jc@virginia.edu 0x0: fmin_s({{ 116212120Sar4jc@virginia.edu uint32_t temp; 116312120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 116412120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 116512120Sar4jc@virginia.edu float fd; 116612120Sar4jc@virginia.edu 116712120Sar4jc@virginia.edu if (issignalingnan(fs2)) { 116812120Sar4jc@virginia.edu fd = fs1; 116912120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 117012120Sar4jc@virginia.edu } else if (issignalingnan(fs1)) { 117112120Sar4jc@virginia.edu fd = fs2; 117212120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 117312120Sar4jc@virginia.edu } else { 117412120Sar4jc@virginia.edu fd = fmin(fs1, fs2); 117512120Sar4jc@virginia.edu } 117612120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 117712120Sar4jc@virginia.edu }}, FloatCmpOp); 117812120Sar4jc@virginia.edu 0x1: fmax_s({{ 117912120Sar4jc@virginia.edu uint32_t temp; 118012120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 118112120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 118212120Sar4jc@virginia.edu float fd; 118312120Sar4jc@virginia.edu 118412120Sar4jc@virginia.edu if (issignalingnan(fs2)) { 118512120Sar4jc@virginia.edu fd = fs1; 118612120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 118712120Sar4jc@virginia.edu } else if (issignalingnan(fs1)) { 118812120Sar4jc@virginia.edu fd = fs2; 118912120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 119012120Sar4jc@virginia.edu } else { 119112120Sar4jc@virginia.edu fd = fmax(fs1, fs2); 119212120Sar4jc@virginia.edu } 119312120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 119412120Sar4jc@virginia.edu }}, FloatCmpOp); 119512120Sar4jc@virginia.edu } 119612120Sar4jc@virginia.edu 0x15: decode ROUND_MODE { 119712120Sar4jc@virginia.edu 0x0: fmin_d({{ 119812120Sar4jc@virginia.edu if (issignalingnan(Fs2)) { 119912120Sar4jc@virginia.edu Fd = Fs1; 120012120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 120112120Sar4jc@virginia.edu } else if (issignalingnan(Fs1)) { 120212120Sar4jc@virginia.edu Fd = Fs2; 120312120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 120412120Sar4jc@virginia.edu } else { 120512120Sar4jc@virginia.edu Fd = fmin(Fs1, Fs2); 120612120Sar4jc@virginia.edu } 120712120Sar4jc@virginia.edu }}, FloatCmpOp); 120812120Sar4jc@virginia.edu 0x1: fmax_d({{ 120912120Sar4jc@virginia.edu if (issignalingnan(Fs2)) { 121012120Sar4jc@virginia.edu Fd = Fs1; 121112120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 121212120Sar4jc@virginia.edu } else if (issignalingnan(Fs1)) { 121312120Sar4jc@virginia.edu Fd = Fs2; 121412120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 121512120Sar4jc@virginia.edu } else { 121612120Sar4jc@virginia.edu Fd = fmax(Fs1, Fs2); 121712120Sar4jc@virginia.edu } 121812120Sar4jc@virginia.edu }}, FloatCmpOp); 121912120Sar4jc@virginia.edu } 122012120Sar4jc@virginia.edu 0x20: fcvt_s_d({{ 122112120Sar4jc@virginia.edu assert(CONV_SGN == 1); 122212120Sar4jc@virginia.edu float fd; 122312120Sar4jc@virginia.edu if (issignalingnan(Fs1)) { 122412120Sar4jc@virginia.edu fd = numeric_limits<float>::quiet_NaN(); 122511725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 122611725Sar4jc@virginia.edu } else { 122712120Sar4jc@virginia.edu fd = (float)Fs1; 122811725Sar4jc@virginia.edu } 122911725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 123012120Sar4jc@virginia.edu }}, FloatCvtOp); 123112120Sar4jc@virginia.edu 0x21: fcvt_d_s({{ 123212120Sar4jc@virginia.edu assert(CONV_SGN == 0); 123311725Sar4jc@virginia.edu uint32_t temp; 123411725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 123511725Sar4jc@virginia.edu 123612120Sar4jc@virginia.edu if (issignalingnan(fs1)) { 123712120Sar4jc@virginia.edu Fd = numeric_limits<double>::quiet_NaN(); 123811725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 123911725Sar4jc@virginia.edu } else { 124012120Sar4jc@virginia.edu Fd = (double)fs1; 124111725Sar4jc@virginia.edu } 124211725Sar4jc@virginia.edu }}, FloatCvtOp); 124312120Sar4jc@virginia.edu 0x2c: fsqrt_s({{ 124412120Sar4jc@virginia.edu assert(RS2 == 0); 124511725Sar4jc@virginia.edu uint32_t temp; 124611725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 124712120Sar4jc@virginia.edu float fd; 124811725Sar4jc@virginia.edu 124912120Sar4jc@virginia.edu if (issignalingnan(Fs1_sf)) { 125011725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 125112120Sar4jc@virginia.edu } 125212120Sar4jc@virginia.edu fd = sqrt(fs1); 125312120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 125412120Sar4jc@virginia.edu }}, FloatSqrtOp); 125512120Sar4jc@virginia.edu 0x2d: fsqrt_d({{ 125612120Sar4jc@virginia.edu assert(RS2 == 0); 125712120Sar4jc@virginia.edu Fd = sqrt(Fs1); 125812120Sar4jc@virginia.edu }}, FloatSqrtOp); 125912120Sar4jc@virginia.edu 0x50: decode ROUND_MODE { 126012120Sar4jc@virginia.edu 0x0: fle_s({{ 126112120Sar4jc@virginia.edu uint32_t temp; 126212120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 126312120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 126412120Sar4jc@virginia.edu 126512120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2)) { 126612120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 126712120Sar4jc@virginia.edu Rd = 0; 126812120Sar4jc@virginia.edu } else { 126912120Sar4jc@virginia.edu Rd = fs1 <= fs2 ? 1 : 0; 127011725Sar4jc@virginia.edu } 127112120Sar4jc@virginia.edu }}, FloatCmpOp); 127212120Sar4jc@virginia.edu 0x1: flt_s({{ 127312120Sar4jc@virginia.edu uint32_t temp; 127412120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 127512120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 127612120Sar4jc@virginia.edu 127712120Sar4jc@virginia.edu if (isnan(fs1) || isnan(fs2)) { 127812120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 127912120Sar4jc@virginia.edu Rd = 0; 128012120Sar4jc@virginia.edu } else { 128112120Sar4jc@virginia.edu Rd = fs1 < fs2 ? 1 : 0; 128212120Sar4jc@virginia.edu } 128312120Sar4jc@virginia.edu }}, FloatCmpOp); 128412120Sar4jc@virginia.edu 0x2: feq_s({{ 128512120Sar4jc@virginia.edu uint32_t temp; 128612120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 128712120Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 128812120Sar4jc@virginia.edu 128912120Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2)) { 129012120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 129112120Sar4jc@virginia.edu } 129212120Sar4jc@virginia.edu Rd = fs1 == fs2 ? 1 : 0; 129312120Sar4jc@virginia.edu }}, FloatCmpOp); 129412120Sar4jc@virginia.edu } 129512120Sar4jc@virginia.edu 0x51: decode ROUND_MODE { 129612120Sar4jc@virginia.edu 0x0: fle_d({{ 129712120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2)) { 129812120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 129912120Sar4jc@virginia.edu Rd = 0; 130012120Sar4jc@virginia.edu } else { 130112120Sar4jc@virginia.edu Rd = Fs1 <= Fs2 ? 1 : 0; 130212120Sar4jc@virginia.edu } 130312120Sar4jc@virginia.edu }}, FloatCmpOp); 130412120Sar4jc@virginia.edu 0x1: flt_d({{ 130512120Sar4jc@virginia.edu if (isnan(Fs1) || isnan(Fs2)) { 130612120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 130712120Sar4jc@virginia.edu Rd = 0; 130812120Sar4jc@virginia.edu } else { 130912120Sar4jc@virginia.edu Rd = Fs1 < Fs2 ? 1 : 0; 131012120Sar4jc@virginia.edu } 131112120Sar4jc@virginia.edu }}, FloatCmpOp); 131212120Sar4jc@virginia.edu 0x2: feq_d({{ 131312120Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2)) { 131412120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 131512120Sar4jc@virginia.edu } 131612120Sar4jc@virginia.edu Rd = Fs1 == Fs2 ? 1 : 0; 131712120Sar4jc@virginia.edu }}, FloatCmpOp); 131812120Sar4jc@virginia.edu } 131912120Sar4jc@virginia.edu 0x60: decode CONV_SGN { 132012120Sar4jc@virginia.edu 0x0: fcvt_w_s({{ 132112120Sar4jc@virginia.edu uint32_t temp; 132212120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 132312120Sar4jc@virginia.edu 132412120Sar4jc@virginia.edu if (isnan(fs1)) { 132512120Sar4jc@virginia.edu Rd_sd = numeric_limits<int32_t>::max(); 132612120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 132712120Sar4jc@virginia.edu } else { 132812120Sar4jc@virginia.edu Rd_sd = (int32_t)fs1; 132912120Sar4jc@virginia.edu if (fetestexcept(FE_INVALID)) { 133012120Sar4jc@virginia.edu if (signbit(fs1)) { 133112120Sar4jc@virginia.edu Rd_sd = numeric_limits<int32_t>::min(); 133212120Sar4jc@virginia.edu } else { 133312120Sar4jc@virginia.edu Rd_sd = numeric_limits<int32_t>::max(); 133412120Sar4jc@virginia.edu } 133512120Sar4jc@virginia.edu feclearexcept(FE_INEXACT); 133612120Sar4jc@virginia.edu } 133712120Sar4jc@virginia.edu } 133812120Sar4jc@virginia.edu }}, FloatCvtOp); 133912120Sar4jc@virginia.edu 0x1: fcvt_wu_s({{ 134012120Sar4jc@virginia.edu uint32_t temp; 134112120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 134212120Sar4jc@virginia.edu 134312120Sar4jc@virginia.edu if (fs1 < 0.0) { 134412120Sar4jc@virginia.edu Rd = 0; 134512120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 134612120Sar4jc@virginia.edu } else { 134712120Sar4jc@virginia.edu Rd = (uint32_t)fs1; 134812120Sar4jc@virginia.edu if (fetestexcept(FE_INVALID)) { 134912120Sar4jc@virginia.edu Rd = numeric_limits<uint64_t>::max(); 135012120Sar4jc@virginia.edu feclearexcept(FE_INEXACT); 135112120Sar4jc@virginia.edu } 135212120Sar4jc@virginia.edu } 135312120Sar4jc@virginia.edu }}, FloatCvtOp); 135412120Sar4jc@virginia.edu 0x2: fcvt_l_s({{ 135512120Sar4jc@virginia.edu uint32_t temp; 135612120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 135712120Sar4jc@virginia.edu 135812120Sar4jc@virginia.edu if (isnan(fs1)) { 135912120Sar4jc@virginia.edu Rd_sd = numeric_limits<int64_t>::max(); 136012120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 136112120Sar4jc@virginia.edu } else { 136212120Sar4jc@virginia.edu Rd_sd = (int64_t)fs1; 136312120Sar4jc@virginia.edu if (fetestexcept(FE_INVALID)) { 136412120Sar4jc@virginia.edu if (signbit(fs1)) { 136512120Sar4jc@virginia.edu Rd_sd = numeric_limits<int64_t>::min(); 136612120Sar4jc@virginia.edu } else { 136712120Sar4jc@virginia.edu Rd_sd = numeric_limits<int64_t>::max(); 136812120Sar4jc@virginia.edu } 136912120Sar4jc@virginia.edu feclearexcept(FE_INEXACT); 137012120Sar4jc@virginia.edu } 137112120Sar4jc@virginia.edu } 137212120Sar4jc@virginia.edu }}, FloatCvtOp); 137312120Sar4jc@virginia.edu 0x3: fcvt_lu_s({{ 137412120Sar4jc@virginia.edu uint32_t temp; 137512120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 137612120Sar4jc@virginia.edu 137712120Sar4jc@virginia.edu if (fs1 < 0.0) { 137812120Sar4jc@virginia.edu Rd = 0; 137912120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 138012120Sar4jc@virginia.edu } else { 138112120Sar4jc@virginia.edu Rd = (uint64_t)fs1; 138212120Sar4jc@virginia.edu if (fetestexcept(FE_INVALID)) { 138312120Sar4jc@virginia.edu Rd = numeric_limits<uint64_t>::max(); 138412120Sar4jc@virginia.edu feclearexcept(FE_INEXACT); 138512120Sar4jc@virginia.edu } 138612120Sar4jc@virginia.edu } 138712120Sar4jc@virginia.edu }}, FloatCvtOp); 138812120Sar4jc@virginia.edu } 138912120Sar4jc@virginia.edu 0x61: decode CONV_SGN { 139012120Sar4jc@virginia.edu 0x0: fcvt_w_d({{ 139112120Sar4jc@virginia.edu Rd_sd = (int32_t)Fs1; 139212120Sar4jc@virginia.edu if (fetestexcept(FE_INVALID)) { 139312120Sar4jc@virginia.edu if (Fs1 < 0.0) { 139412120Sar4jc@virginia.edu Rd_sd = numeric_limits<int32_t>::min(); 139512120Sar4jc@virginia.edu } else { 139612120Sar4jc@virginia.edu Rd_sd = numeric_limits<int32_t>::max(); 139712120Sar4jc@virginia.edu } 139812120Sar4jc@virginia.edu feclearexcept(FE_INEXACT); 139912120Sar4jc@virginia.edu } 140012120Sar4jc@virginia.edu }}, FloatCvtOp); 140112120Sar4jc@virginia.edu 0x1: fcvt_wu_d({{ 140212120Sar4jc@virginia.edu if (Fs1 < 0.0) { 140312120Sar4jc@virginia.edu Rd = 0; 140412120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 140512120Sar4jc@virginia.edu } else { 140612120Sar4jc@virginia.edu Rd = (uint32_t)Fs1; 140712120Sar4jc@virginia.edu if (fetestexcept(FE_INVALID)) { 140812120Sar4jc@virginia.edu Rd = numeric_limits<uint64_t>::max(); 140912120Sar4jc@virginia.edu feclearexcept(FE_INEXACT); 141012120Sar4jc@virginia.edu } 141112120Sar4jc@virginia.edu } 141212120Sar4jc@virginia.edu }}, FloatCvtOp); 141312120Sar4jc@virginia.edu 0x2: fcvt_l_d({{ 141412120Sar4jc@virginia.edu Rd_sd = Fs1; 141512120Sar4jc@virginia.edu if (fetestexcept(FE_INVALID)) { 141612120Sar4jc@virginia.edu if (Fs1 < 0.0) { 141712120Sar4jc@virginia.edu Rd_sd = numeric_limits<int64_t>::min(); 141812120Sar4jc@virginia.edu } else { 141912120Sar4jc@virginia.edu Rd_sd = numeric_limits<int64_t>::max(); 142012120Sar4jc@virginia.edu } 142112120Sar4jc@virginia.edu feclearexcept(FE_INEXACT); 142212120Sar4jc@virginia.edu } 142312120Sar4jc@virginia.edu }}, FloatCvtOp); 142412120Sar4jc@virginia.edu 0x3: fcvt_lu_d({{ 142512120Sar4jc@virginia.edu if (Fs1 < 0.0) { 142612120Sar4jc@virginia.edu Rd = 0; 142712120Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 142812120Sar4jc@virginia.edu } else { 142912120Sar4jc@virginia.edu Rd = (uint64_t)Fs1; 143012120Sar4jc@virginia.edu if (fetestexcept(FE_INVALID)) { 143112120Sar4jc@virginia.edu Rd = numeric_limits<uint64_t>::max(); 143212120Sar4jc@virginia.edu feclearexcept(FE_INEXACT); 143312120Sar4jc@virginia.edu } 143412120Sar4jc@virginia.edu } 143512120Sar4jc@virginia.edu }}, FloatCvtOp); 143612120Sar4jc@virginia.edu } 143712120Sar4jc@virginia.edu 0x68: decode CONV_SGN { 143812120Sar4jc@virginia.edu 0x0: fcvt_s_w({{ 143912120Sar4jc@virginia.edu float temp = (float)Rs1_sw; 144012120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp); 144112120Sar4jc@virginia.edu }}, FloatCvtOp); 144212120Sar4jc@virginia.edu 0x1: fcvt_s_wu({{ 144312120Sar4jc@virginia.edu float temp = (float)Rs1_uw; 144412120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp); 144512120Sar4jc@virginia.edu }}, FloatCvtOp); 144612120Sar4jc@virginia.edu 0x2: fcvt_s_l({{ 144712120Sar4jc@virginia.edu float temp = (float)Rs1_sd; 144812120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp); 144912120Sar4jc@virginia.edu }}, FloatCvtOp); 145012120Sar4jc@virginia.edu 0x3: fcvt_s_lu({{ 145112120Sar4jc@virginia.edu float temp = (float)Rs1; 145212120Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp); 145312120Sar4jc@virginia.edu }}, FloatCvtOp); 145412120Sar4jc@virginia.edu } 145512120Sar4jc@virginia.edu 0x69: decode CONV_SGN { 145612120Sar4jc@virginia.edu 0x0: fcvt_d_w({{ 145712120Sar4jc@virginia.edu Fd = (double)Rs1_sw; 145812120Sar4jc@virginia.edu }}, FloatCvtOp); 145912120Sar4jc@virginia.edu 0x1: fcvt_d_wu({{ 146012120Sar4jc@virginia.edu Fd = (double)Rs1_uw; 146112120Sar4jc@virginia.edu }}, FloatCvtOp); 146212120Sar4jc@virginia.edu 0x2: fcvt_d_l({{ 146312120Sar4jc@virginia.edu Fd = (double)Rs1_sd; 146412120Sar4jc@virginia.edu }}, FloatCvtOp); 146512120Sar4jc@virginia.edu 0x3: fcvt_d_lu({{ 146612120Sar4jc@virginia.edu Fd = (double)Rs1; 146712120Sar4jc@virginia.edu }}, FloatCvtOp); 146812120Sar4jc@virginia.edu } 146912120Sar4jc@virginia.edu 0x70: decode ROUND_MODE { 147012120Sar4jc@virginia.edu 0x0: fmv_x_s({{ 147112120Sar4jc@virginia.edu Rd = (uint32_t)Fs1_bits; 147212120Sar4jc@virginia.edu if ((Rd&0x80000000) != 0) { 147312120Sar4jc@virginia.edu Rd |= (0xFFFFFFFFULL << 32); 147412120Sar4jc@virginia.edu } 147512120Sar4jc@virginia.edu }}, FloatCvtOp); 147612120Sar4jc@virginia.edu 0x1: fclass_s({{ 147712120Sar4jc@virginia.edu uint32_t temp; 147812120Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 147912120Sar4jc@virginia.edu switch (fpclassify(fs1)) { 148012120Sar4jc@virginia.edu case FP_INFINITE: 148112120Sar4jc@virginia.edu if (signbit(fs1)) { 148212120Sar4jc@virginia.edu Rd = 1 << 0; 148312120Sar4jc@virginia.edu } else { 148412120Sar4jc@virginia.edu Rd = 1 << 7; 148512120Sar4jc@virginia.edu } 148612120Sar4jc@virginia.edu break; 148712120Sar4jc@virginia.edu case FP_NAN: 148812120Sar4jc@virginia.edu if (issignalingnan(fs1)) { 148912120Sar4jc@virginia.edu Rd = 1 << 8; 149012120Sar4jc@virginia.edu } else { 149112120Sar4jc@virginia.edu Rd = 1 << 9; 149212120Sar4jc@virginia.edu } 149312120Sar4jc@virginia.edu break; 149412120Sar4jc@virginia.edu case FP_ZERO: 149512120Sar4jc@virginia.edu if (signbit(fs1)) { 149612120Sar4jc@virginia.edu Rd = 1 << 3; 149712120Sar4jc@virginia.edu } else { 149812120Sar4jc@virginia.edu Rd = 1 << 4; 149912120Sar4jc@virginia.edu } 150012120Sar4jc@virginia.edu break; 150112120Sar4jc@virginia.edu case FP_SUBNORMAL: 150212120Sar4jc@virginia.edu if (signbit(fs1)) { 150312120Sar4jc@virginia.edu Rd = 1 << 2; 150412120Sar4jc@virginia.edu } else { 150512120Sar4jc@virginia.edu Rd = 1 << 5; 150612120Sar4jc@virginia.edu } 150712120Sar4jc@virginia.edu break; 150812120Sar4jc@virginia.edu case FP_NORMAL: 150912120Sar4jc@virginia.edu if (signbit(fs1)) { 151012120Sar4jc@virginia.edu Rd = 1 << 1; 151112120Sar4jc@virginia.edu } else { 151212120Sar4jc@virginia.edu Rd = 1 << 6; 151312120Sar4jc@virginia.edu } 151412120Sar4jc@virginia.edu break; 151512120Sar4jc@virginia.edu default: 151612120Sar4jc@virginia.edu panic("Unknown classification for operand."); 151712120Sar4jc@virginia.edu break; 151812120Sar4jc@virginia.edu } 151912120Sar4jc@virginia.edu }}); 152012120Sar4jc@virginia.edu } 152112120Sar4jc@virginia.edu 0x71: decode ROUND_MODE { 152212120Sar4jc@virginia.edu 0x0: fmv_x_d({{ 152312120Sar4jc@virginia.edu Rd = Fs1_bits; 152412120Sar4jc@virginia.edu }}, FloatCvtOp); 152512120Sar4jc@virginia.edu 0x1: fclass_d({{ 152612120Sar4jc@virginia.edu switch (fpclassify(Fs1)) { 152712120Sar4jc@virginia.edu case FP_INFINITE: 152812120Sar4jc@virginia.edu if (signbit(Fs1)) { 152912120Sar4jc@virginia.edu Rd = 1 << 0; 153012120Sar4jc@virginia.edu } else { 153112120Sar4jc@virginia.edu Rd = 1 << 7; 153212120Sar4jc@virginia.edu } 153312120Sar4jc@virginia.edu break; 153412120Sar4jc@virginia.edu case FP_NAN: 153512120Sar4jc@virginia.edu if (issignalingnan(Fs1)) { 153612120Sar4jc@virginia.edu Rd = 1 << 8; 153712120Sar4jc@virginia.edu } else { 153812120Sar4jc@virginia.edu Rd = 1 << 9; 153912120Sar4jc@virginia.edu } 154012120Sar4jc@virginia.edu break; 154112120Sar4jc@virginia.edu case FP_ZERO: 154212120Sar4jc@virginia.edu if (signbit(Fs1)) { 154312120Sar4jc@virginia.edu Rd = 1 << 3; 154412120Sar4jc@virginia.edu } else { 154512120Sar4jc@virginia.edu Rd = 1 << 4; 154612120Sar4jc@virginia.edu } 154712120Sar4jc@virginia.edu break; 154812120Sar4jc@virginia.edu case FP_SUBNORMAL: 154912120Sar4jc@virginia.edu if (signbit(Fs1)) { 155012120Sar4jc@virginia.edu Rd = 1 << 2; 155112120Sar4jc@virginia.edu } else { 155212120Sar4jc@virginia.edu Rd = 1 << 5; 155312120Sar4jc@virginia.edu } 155412120Sar4jc@virginia.edu break; 155512120Sar4jc@virginia.edu case FP_NORMAL: 155612120Sar4jc@virginia.edu if (signbit(Fs1)) { 155712120Sar4jc@virginia.edu Rd = 1 << 1; 155812120Sar4jc@virginia.edu } else { 155912120Sar4jc@virginia.edu Rd = 1 << 6; 156012120Sar4jc@virginia.edu } 156112120Sar4jc@virginia.edu break; 156212120Sar4jc@virginia.edu default: 156312120Sar4jc@virginia.edu panic("Unknown classification for operand."); 156412120Sar4jc@virginia.edu break; 156512120Sar4jc@virginia.edu } 156612120Sar4jc@virginia.edu }}); 156712120Sar4jc@virginia.edu } 156812120Sar4jc@virginia.edu 0x78: fmv_s_x({{ 156912120Sar4jc@virginia.edu Fd_bits = (uint64_t)Rs1_uw; 157011725Sar4jc@virginia.edu }}, FloatCvtOp); 157112120Sar4jc@virginia.edu 0x79: fmv_d_x({{ 157212120Sar4jc@virginia.edu Fd_bits = Rs1; 157311725Sar4jc@virginia.edu }}, FloatCvtOp); 157411725Sar4jc@virginia.edu } 157512120Sar4jc@virginia.edu } 157612120Sar4jc@virginia.edu 157712120Sar4jc@virginia.edu 0x18: decode FUNCT3 { 157812120Sar4jc@virginia.edu format BOp { 157912120Sar4jc@virginia.edu 0x0: beq({{ 158012120Sar4jc@virginia.edu if (Rs1 == Rs2) { 158112120Sar4jc@virginia.edu NPC = PC + imm; 158212120Sar4jc@virginia.edu } else { 158312120Sar4jc@virginia.edu NPC = NPC; 158411725Sar4jc@virginia.edu } 158512120Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 158612120Sar4jc@virginia.edu 0x1: bne({{ 158712120Sar4jc@virginia.edu if (Rs1 != Rs2) { 158812120Sar4jc@virginia.edu NPC = PC + imm; 158911725Sar4jc@virginia.edu } else { 159012120Sar4jc@virginia.edu NPC = NPC; 159111725Sar4jc@virginia.edu } 159212120Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 159312120Sar4jc@virginia.edu 0x4: blt({{ 159412120Sar4jc@virginia.edu if (Rs1_sd < Rs2_sd) { 159512120Sar4jc@virginia.edu NPC = PC + imm; 159612120Sar4jc@virginia.edu } else { 159712120Sar4jc@virginia.edu NPC = NPC; 159811725Sar4jc@virginia.edu } 159912120Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 160012120Sar4jc@virginia.edu 0x5: bge({{ 160112120Sar4jc@virginia.edu if (Rs1_sd >= Rs2_sd) { 160212120Sar4jc@virginia.edu NPC = PC + imm; 160311725Sar4jc@virginia.edu } else { 160412120Sar4jc@virginia.edu NPC = NPC; 160511725Sar4jc@virginia.edu } 160612120Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 160712120Sar4jc@virginia.edu 0x6: bltu({{ 160812120Sar4jc@virginia.edu if (Rs1 < Rs2) { 160912120Sar4jc@virginia.edu NPC = PC + imm; 161012120Sar4jc@virginia.edu } else { 161112120Sar4jc@virginia.edu NPC = NPC; 161212120Sar4jc@virginia.edu } 161312120Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 161412120Sar4jc@virginia.edu 0x7: bgeu({{ 161512120Sar4jc@virginia.edu if (Rs1 >= Rs2) { 161612120Sar4jc@virginia.edu NPC = PC + imm; 161712120Sar4jc@virginia.edu } else { 161812120Sar4jc@virginia.edu NPC = NPC; 161912120Sar4jc@virginia.edu } 162012120Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 162111725Sar4jc@virginia.edu } 162212120Sar4jc@virginia.edu } 162312120Sar4jc@virginia.edu 162412120Sar4jc@virginia.edu 0x19: decode FUNCT3 { 162512120Sar4jc@virginia.edu 0x0: Jump::jalr({{ 162612120Sar4jc@virginia.edu Rd = NPC; 162712120Sar4jc@virginia.edu NPC = (imm + Rs1) & (~0x1); 162812120Sar4jc@virginia.edu }}, IsIndirectControl, IsUncondControl, IsCall); 162912120Sar4jc@virginia.edu } 163012120Sar4jc@virginia.edu 163112120Sar4jc@virginia.edu 0x1b: JOp::jal({{ 163212120Sar4jc@virginia.edu Rd = NPC; 163312120Sar4jc@virginia.edu NPC = PC + imm; 163412120Sar4jc@virginia.edu }}, IsDirectControl, IsUncondControl, IsCall); 163512120Sar4jc@virginia.edu 163612120Sar4jc@virginia.edu 0x1c: decode FUNCT3 { 163712120Sar4jc@virginia.edu format SystemOp { 163812120Sar4jc@virginia.edu 0x0: decode FUNCT12 { 163912120Sar4jc@virginia.edu 0x0: ecall({{ 164012120Sar4jc@virginia.edu fault = make_shared<SyscallFault>(); 164112120Sar4jc@virginia.edu }}, IsSerializeAfter, IsNonSpeculative, IsSyscall, 164212120Sar4jc@virginia.edu No_OpClass); 164312120Sar4jc@virginia.edu 0x1: ebreak({{ 164412120Sar4jc@virginia.edu fault = make_shared<BreakpointFault>(); 164512120Sar4jc@virginia.edu }}, IsSerializeAfter, IsNonSpeculative, No_OpClass); 164612120Sar4jc@virginia.edu 0x100: eret({{ 164712120Sar4jc@virginia.edu fault = make_shared<UnimplementedFault>("eret"); 164812120Sar4jc@virginia.edu }}, No_OpClass); 164912120Sar4jc@virginia.edu } 165011725Sar4jc@virginia.edu } 165112120Sar4jc@virginia.edu format CSROp { 165212120Sar4jc@virginia.edu 0x1: csrrw({{ 165312120Sar4jc@virginia.edu Rd = xc->readMiscReg(csr); 165412120Sar4jc@virginia.edu xc->setMiscReg(csr, Rs1); 165512120Sar4jc@virginia.edu }}, IsNonSpeculative, No_OpClass); 165612120Sar4jc@virginia.edu 0x2: csrrs({{ 165712120Sar4jc@virginia.edu Rd = xc->readMiscReg(csr); 165812120Sar4jc@virginia.edu if (Rs1 != 0) { 165912120Sar4jc@virginia.edu xc->setMiscReg(csr, Rd | Rs1); 166012120Sar4jc@virginia.edu } 166112120Sar4jc@virginia.edu }}, IsNonSpeculative, No_OpClass); 166212120Sar4jc@virginia.edu 0x3: csrrc({{ 166312120Sar4jc@virginia.edu Rd = xc->readMiscReg(csr); 166412120Sar4jc@virginia.edu if (Rs1 != 0) { 166512120Sar4jc@virginia.edu xc->setMiscReg(csr, Rd & ~Rs1); 166612120Sar4jc@virginia.edu } 166712120Sar4jc@virginia.edu }}, IsNonSpeculative, No_OpClass); 166812120Sar4jc@virginia.edu 0x5: csrrwi({{ 166912120Sar4jc@virginia.edu Rd = xc->readMiscReg(csr); 167012120Sar4jc@virginia.edu xc->setMiscReg(csr, uimm); 167112120Sar4jc@virginia.edu }}, IsNonSpeculative, No_OpClass); 167212120Sar4jc@virginia.edu 0x6: csrrsi({{ 167312120Sar4jc@virginia.edu Rd = xc->readMiscReg(csr); 167412120Sar4jc@virginia.edu if (uimm != 0) { 167512120Sar4jc@virginia.edu xc->setMiscReg(csr, Rd | uimm); 167612120Sar4jc@virginia.edu } 167712120Sar4jc@virginia.edu }}, IsNonSpeculative, No_OpClass); 167812120Sar4jc@virginia.edu 0x7: csrrci({{ 167912120Sar4jc@virginia.edu Rd = xc->readMiscReg(csr); 168012120Sar4jc@virginia.edu if (uimm != 0) { 168112120Sar4jc@virginia.edu xc->setMiscReg(csr, Rd & ~uimm); 168212120Sar4jc@virginia.edu } 168312120Sar4jc@virginia.edu }}, IsNonSpeculative, No_OpClass); 168411725Sar4jc@virginia.edu } 168511725Sar4jc@virginia.edu } 168611725Sar4jc@virginia.edu } 168712120Sar4jc@virginia.edu}