decoder.isa revision 11726
111723Sar4jc@virginia.edu// -*- mode:c++ -*- 211723Sar4jc@virginia.edu 311723Sar4jc@virginia.edu// Copyright (c) 2015 RISC-V Foundation 411723Sar4jc@virginia.edu// Copyright (c) 2016 The University of Virginia 511723Sar4jc@virginia.edu// All rights reserved. 611723Sar4jc@virginia.edu// 711723Sar4jc@virginia.edu// Redistribution and use in source and binary forms, with or without 811723Sar4jc@virginia.edu// modification, are permitted provided that the following conditions are 911723Sar4jc@virginia.edu// met: redistributions of source code must retain the above copyright 1011723Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer; 1111723Sar4jc@virginia.edu// redistributions in binary form must reproduce the above copyright 1211723Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer in the 1311723Sar4jc@virginia.edu// documentation and/or other materials provided with the distribution; 1411723Sar4jc@virginia.edu// neither the name of the copyright holders nor the names of its 1511723Sar4jc@virginia.edu// contributors may be used to endorse or promote products derived from 1611723Sar4jc@virginia.edu// this software without specific prior written permission. 1711723Sar4jc@virginia.edu// 1811723Sar4jc@virginia.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1911723Sar4jc@virginia.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2011723Sar4jc@virginia.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2111723Sar4jc@virginia.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2211723Sar4jc@virginia.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2311723Sar4jc@virginia.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2411723Sar4jc@virginia.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2511723Sar4jc@virginia.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2611723Sar4jc@virginia.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2711723Sar4jc@virginia.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2811723Sar4jc@virginia.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2911723Sar4jc@virginia.edu// 3011723Sar4jc@virginia.edu// Authors: Alec Roelke 3111723Sar4jc@virginia.edu 3211723Sar4jc@virginia.edu//////////////////////////////////////////////////////////////////// 3311723Sar4jc@virginia.edu// 3411723Sar4jc@virginia.edu// The RISC-V ISA decoder 3511723Sar4jc@virginia.edu// 3611723Sar4jc@virginia.edu 3711723Sar4jc@virginia.edudecode OPCODE default Unknown::unknown() { 3811723Sar4jc@virginia.edu 0x03: decode FUNCT3 { 3911723Sar4jc@virginia.edu format Load { 4011723Sar4jc@virginia.edu 0x0: lb({{ 4111723Sar4jc@virginia.edu Rd_sd = Mem_sb; 4211723Sar4jc@virginia.edu }}); 4311723Sar4jc@virginia.edu 0x1: lh({{ 4411723Sar4jc@virginia.edu Rd_sd = Mem_sh; 4511723Sar4jc@virginia.edu }}); 4611723Sar4jc@virginia.edu 0x2: lw({{ 4711723Sar4jc@virginia.edu Rd_sd = Mem_sw; 4811723Sar4jc@virginia.edu }}); 4911723Sar4jc@virginia.edu 0x3: ld({{ 5011723Sar4jc@virginia.edu Rd_sd = Mem_sd; 5111723Sar4jc@virginia.edu }}); 5211723Sar4jc@virginia.edu 0x4: lbu({{ 5311723Sar4jc@virginia.edu Rd = Mem_ub; 5411723Sar4jc@virginia.edu }}); 5511723Sar4jc@virginia.edu 0x5: lhu({{ 5611723Sar4jc@virginia.edu Rd = Mem_uh; 5711723Sar4jc@virginia.edu }}); 5811723Sar4jc@virginia.edu 0x6: lwu({{ 5911723Sar4jc@virginia.edu Rd = Mem_uw; 6011723Sar4jc@virginia.edu }}); 6111723Sar4jc@virginia.edu } 6211723Sar4jc@virginia.edu } 6311723Sar4jc@virginia.edu 6411725Sar4jc@virginia.edu 0x07: decode FUNCT3 { 6511725Sar4jc@virginia.edu format Load { 6611725Sar4jc@virginia.edu 0x2: flw({{ 6711725Sar4jc@virginia.edu Fd_bits = (uint64_t)Mem_uw; 6811725Sar4jc@virginia.edu }}); 6911725Sar4jc@virginia.edu 0x3: fld({{ 7011725Sar4jc@virginia.edu Fd_bits = Mem; 7111725Sar4jc@virginia.edu }}); 7211725Sar4jc@virginia.edu } 7311725Sar4jc@virginia.edu } 7411725Sar4jc@virginia.edu 7511723Sar4jc@virginia.edu 0x0f: decode FUNCT3 { 7611723Sar4jc@virginia.edu format IOp { 7711723Sar4jc@virginia.edu 0x0: fence({{ 7811723Sar4jc@virginia.edu }}, IsNonSpeculative, IsMemBarrier, No_OpClass); 7911723Sar4jc@virginia.edu 0x1: fence_i({{ 8011723Sar4jc@virginia.edu }}, IsNonSpeculative, IsSerializeAfter, No_OpClass); 8111723Sar4jc@virginia.edu } 8211723Sar4jc@virginia.edu } 8311723Sar4jc@virginia.edu 8411723Sar4jc@virginia.edu 0x13: decode FUNCT3 { 8511723Sar4jc@virginia.edu format IOp { 8611723Sar4jc@virginia.edu 0x0: addi({{ 8711723Sar4jc@virginia.edu Rd_sd = Rs1_sd + imm; 8811723Sar4jc@virginia.edu }}); 8911723Sar4jc@virginia.edu 0x1: slli({{ 9011723Sar4jc@virginia.edu Rd = Rs1 << SHAMT6; 9111723Sar4jc@virginia.edu }}); 9211723Sar4jc@virginia.edu 0x2: slti({{ 9311723Sar4jc@virginia.edu Rd = (Rs1_sd < imm) ? 1 : 0; 9411723Sar4jc@virginia.edu }}); 9511723Sar4jc@virginia.edu 0x3: sltiu({{ 9611723Sar4jc@virginia.edu Rd = (Rs1 < (uint64_t)imm) ? 1 : 0; 9711723Sar4jc@virginia.edu }}); 9811723Sar4jc@virginia.edu 0x4: xori({{ 9911723Sar4jc@virginia.edu Rd = Rs1 ^ (uint64_t)imm; 10011723Sar4jc@virginia.edu }}); 10111723Sar4jc@virginia.edu 0x5: decode SRTYPE { 10211723Sar4jc@virginia.edu 0x0: srli({{ 10311723Sar4jc@virginia.edu Rd = Rs1 >> SHAMT6; 10411723Sar4jc@virginia.edu }}); 10511723Sar4jc@virginia.edu 0x1: srai({{ 10611723Sar4jc@virginia.edu Rd_sd = Rs1_sd >> SHAMT6; 10711723Sar4jc@virginia.edu }}); 10811723Sar4jc@virginia.edu } 10911723Sar4jc@virginia.edu 0x6: ori({{ 11011723Sar4jc@virginia.edu Rd = Rs1 | (uint64_t)imm; 11111723Sar4jc@virginia.edu }}); 11211723Sar4jc@virginia.edu 0x7: andi({{ 11311723Sar4jc@virginia.edu Rd = Rs1 & (uint64_t)imm; 11411723Sar4jc@virginia.edu }}); 11511723Sar4jc@virginia.edu } 11611723Sar4jc@virginia.edu } 11711723Sar4jc@virginia.edu 11811723Sar4jc@virginia.edu 0x17: UOp::auipc({{ 11911723Sar4jc@virginia.edu Rd = PC + imm; 12011723Sar4jc@virginia.edu }}); 12111723Sar4jc@virginia.edu 12211723Sar4jc@virginia.edu 0x1b: decode FUNCT3 { 12311723Sar4jc@virginia.edu format IOp { 12411723Sar4jc@virginia.edu 0x0: addiw({{ 12511723Sar4jc@virginia.edu Rd_sd = (int32_t)Rs1 + (int32_t)imm; 12611723Sar4jc@virginia.edu }}); 12711723Sar4jc@virginia.edu 0x1: slliw({{ 12811723Sar4jc@virginia.edu Rd_sd = Rs1_sw << SHAMT5; 12911723Sar4jc@virginia.edu }}); 13011723Sar4jc@virginia.edu 0x5: decode SRTYPE { 13111723Sar4jc@virginia.edu 0x0: srliw({{ 13211723Sar4jc@virginia.edu Rd = Rs1_uw >> SHAMT5; 13311723Sar4jc@virginia.edu }}); 13411723Sar4jc@virginia.edu 0x1: sraiw({{ 13511723Sar4jc@virginia.edu Rd_sd = Rs1_sw >> SHAMT5; 13611723Sar4jc@virginia.edu }}); 13711723Sar4jc@virginia.edu } 13811723Sar4jc@virginia.edu } 13911723Sar4jc@virginia.edu } 14011723Sar4jc@virginia.edu 14111723Sar4jc@virginia.edu 0x23: decode FUNCT3 { 14211723Sar4jc@virginia.edu format Store { 14311723Sar4jc@virginia.edu 0x0: sb({{ 14411723Sar4jc@virginia.edu Mem_ub = Rs2_ub; 14511723Sar4jc@virginia.edu }}); 14611723Sar4jc@virginia.edu 0x1: sh({{ 14711723Sar4jc@virginia.edu Mem_uh = Rs2_uh; 14811723Sar4jc@virginia.edu }}); 14911723Sar4jc@virginia.edu 0x2: sw({{ 15011723Sar4jc@virginia.edu Mem_uw = Rs2_uw; 15111723Sar4jc@virginia.edu }}); 15211723Sar4jc@virginia.edu 0x3: sd({{ 15311723Sar4jc@virginia.edu Mem_ud = Rs2_ud; 15411723Sar4jc@virginia.edu }}); 15511723Sar4jc@virginia.edu } 15611723Sar4jc@virginia.edu } 15711723Sar4jc@virginia.edu 15811725Sar4jc@virginia.edu 0x27: decode FUNCT3 { 15911725Sar4jc@virginia.edu format Store { 16011725Sar4jc@virginia.edu 0x2: fsw({{ 16111725Sar4jc@virginia.edu Mem_uw = (uint32_t)Fs2_bits; 16211725Sar4jc@virginia.edu }}); 16311725Sar4jc@virginia.edu 0x3: fsd({{ 16411725Sar4jc@virginia.edu Mem_ud = Fs2_bits; 16511725Sar4jc@virginia.edu }}); 16611725Sar4jc@virginia.edu } 16711725Sar4jc@virginia.edu } 16811725Sar4jc@virginia.edu 16911726Sar4jc@virginia.edu 0x2f: decode FUNCT3 { 17011726Sar4jc@virginia.edu 0x2: decode AMOFUNCT { 17111726Sar4jc@virginia.edu 0x2: LoadReserved::lr_w({{ 17211726Sar4jc@virginia.edu Rd_sd = Mem_sw; 17311726Sar4jc@virginia.edu }}, mem_flags=LLSC, aq=AQ, rl=RL); 17411726Sar4jc@virginia.edu 0x3: StoreCond::sc_w({{ 17511726Sar4jc@virginia.edu Mem_uw = Rs2_uw; 17611726Sar4jc@virginia.edu }}, {{ 17711726Sar4jc@virginia.edu Rd = result; 17811726Sar4jc@virginia.edu }}, inst_flags=IsStoreConditional, mem_flags=LLSC, aq=AQ, rl=RL); 17911726Sar4jc@virginia.edu format AtomicMemOp { 18011726Sar4jc@virginia.edu 0x0: amoadd_w({{Rt_sd = Mem_sw;}}, {{ 18111726Sar4jc@virginia.edu Mem_sw = Rs2_sw + Rt_sd; 18211726Sar4jc@virginia.edu Rd_sd = Rt_sd; 18311726Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 18411726Sar4jc@virginia.edu 0x1: amoswap_w({{Rt_sd = Mem_sw;}}, {{ 18511726Sar4jc@virginia.edu Mem_sw = Rs2_uw; 18611726Sar4jc@virginia.edu Rd_sd = Rt_sd; 18711726Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 18811726Sar4jc@virginia.edu 0x4: amoxor_w({{Rt_sd = Mem_sw;}}, {{ 18911726Sar4jc@virginia.edu Mem_sw = Rs2_uw^Rt_sd; 19011726Sar4jc@virginia.edu Rd_sd = Rt_sd; 19111726Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 19211726Sar4jc@virginia.edu 0x8: amoor_w({{Rt_sd = Mem_sw;}}, {{ 19311726Sar4jc@virginia.edu Mem_sw = Rs2_uw | Rt_sd; 19411726Sar4jc@virginia.edu Rd_sd = Rt_sd; 19511726Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 19611726Sar4jc@virginia.edu 0xc: amoand_w({{Rt_sd = Mem_sw;}}, {{ 19711726Sar4jc@virginia.edu Mem_sw = Rs2_uw&Rt_sd; 19811726Sar4jc@virginia.edu Rd_sd = Rt_sd; 19911726Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 20011726Sar4jc@virginia.edu 0x10: amomin_w({{Rt_sd = Mem_sw;}}, {{ 20111726Sar4jc@virginia.edu Mem_sw = std::min<int32_t>(Rs2_sw, Rt_sd); 20211726Sar4jc@virginia.edu Rd_sd = Rt_sd; 20311726Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 20411726Sar4jc@virginia.edu 0x14: amomax_w({{Rt_sd = Mem_sw;}}, {{ 20511726Sar4jc@virginia.edu Mem_sw = std::max<int32_t>(Rs2_sw, Rt_sd); 20611726Sar4jc@virginia.edu Rd_sd = Rt_sd; 20711726Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 20811726Sar4jc@virginia.edu 0x18: amominu_w({{Rt_sd = Mem_sw;}}, {{ 20911726Sar4jc@virginia.edu Mem_sw = std::min<uint32_t>(Rs2_uw, Rt_sd); 21011726Sar4jc@virginia.edu Rd_sd = Rt_sd; 21111726Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 21211726Sar4jc@virginia.edu 0x1c: amomaxu_w({{Rt_sd = Mem_sw;}}, {{ 21311726Sar4jc@virginia.edu Mem_sw = std::max<uint32_t>(Rs2_uw, Rt_sd); 21411726Sar4jc@virginia.edu Rd_sd = Rt_sd; 21511726Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 21611726Sar4jc@virginia.edu } 21711726Sar4jc@virginia.edu } 21811726Sar4jc@virginia.edu 0x3: decode AMOFUNCT { 21911726Sar4jc@virginia.edu 0x2: LoadReserved::lr_d({{ 22011726Sar4jc@virginia.edu Rd_sd = Mem_sd; 22111726Sar4jc@virginia.edu }}, aq=AQ, rl=RL); 22211726Sar4jc@virginia.edu 0x3: StoreCond::sc_d({{ 22311726Sar4jc@virginia.edu Mem = Rs2; 22411726Sar4jc@virginia.edu }}, {{ 22511726Sar4jc@virginia.edu Rd = result; 22611726Sar4jc@virginia.edu }}, aq=AQ, rl=RL); 22711726Sar4jc@virginia.edu format AtomicMemOp { 22811726Sar4jc@virginia.edu 0x0: amoadd_d({{Rt_sd = Mem_sd;}}, {{ 22911726Sar4jc@virginia.edu Mem_sd = Rs2_sd + Rt_sd; 23011726Sar4jc@virginia.edu Rd_sd = Rt_sd; 23111726Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 23211726Sar4jc@virginia.edu 0x1: amoswap_d({{Rt = Mem;}}, {{ 23311726Sar4jc@virginia.edu Mem = Rs2; 23411726Sar4jc@virginia.edu Rd = Rt; 23511726Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 23611726Sar4jc@virginia.edu 0x4: amoxor_d({{Rt = Mem;}}, {{ 23711726Sar4jc@virginia.edu Mem = Rs2^Rt; 23811726Sar4jc@virginia.edu Rd = Rt; 23911726Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 24011726Sar4jc@virginia.edu 0x8: amoor_d({{Rt = Mem;}}, {{ 24111726Sar4jc@virginia.edu Mem = Rs2 | Rt; 24211726Sar4jc@virginia.edu Rd = Rt; 24311726Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 24411726Sar4jc@virginia.edu 0xc: amoand_d({{Rt = Mem;}}, {{ 24511726Sar4jc@virginia.edu Mem = Rs2&Rt; 24611726Sar4jc@virginia.edu Rd = Rt; 24711726Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 24811726Sar4jc@virginia.edu 0x10: amomin_d({{Rt_sd = Mem_sd;}}, {{ 24911726Sar4jc@virginia.edu Mem_sd = std::min(Rs2_sd, Rt_sd); 25011726Sar4jc@virginia.edu Rd_sd = Rt_sd; 25111726Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 25211726Sar4jc@virginia.edu 0x14: amomax_d({{Rt_sd = Mem_sd;}}, {{ 25311726Sar4jc@virginia.edu Mem_sd = std::max(Rs2_sd, Rt_sd); 25411726Sar4jc@virginia.edu Rd_sd = Rt_sd; 25511726Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 25611726Sar4jc@virginia.edu 0x18: amominu_d({{Rt = Mem;}}, {{ 25711726Sar4jc@virginia.edu Mem = std::min(Rs2, Rt); 25811726Sar4jc@virginia.edu Rd = Rt; 25911726Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 26011726Sar4jc@virginia.edu 0x1c: amomaxu_d({{Rt = Mem;}}, {{ 26111726Sar4jc@virginia.edu Mem = std::max(Rs2, Rt); 26211726Sar4jc@virginia.edu Rd = Rt; 26311726Sar4jc@virginia.edu }}, {{EA = Rs1;}}); 26411726Sar4jc@virginia.edu } 26511726Sar4jc@virginia.edu } 26611726Sar4jc@virginia.edu } 26711723Sar4jc@virginia.edu 0x33: decode FUNCT3 { 26811723Sar4jc@virginia.edu format ROp { 26911723Sar4jc@virginia.edu 0x0: decode FUNCT7 { 27011723Sar4jc@virginia.edu 0x0: add({{ 27111723Sar4jc@virginia.edu Rd = Rs1_sd + Rs2_sd; 27211723Sar4jc@virginia.edu }}); 27311724Sar4jc@virginia.edu 0x1: mul({{ 27411724Sar4jc@virginia.edu Rd = Rs1_sd*Rs2_sd; 27511724Sar4jc@virginia.edu }}, IntMultOp); 27611723Sar4jc@virginia.edu 0x20: sub({{ 27711723Sar4jc@virginia.edu Rd = Rs1_sd - Rs2_sd; 27811723Sar4jc@virginia.edu }}); 27911723Sar4jc@virginia.edu } 28011723Sar4jc@virginia.edu 0x1: decode FUNCT7 { 28111723Sar4jc@virginia.edu 0x0: sll({{ 28211723Sar4jc@virginia.edu Rd = Rs1 << Rs2<5:0>; 28311723Sar4jc@virginia.edu }}); 28411724Sar4jc@virginia.edu 0x1: mulh({{ 28511724Sar4jc@virginia.edu bool negate = (Rs1_sd < 0) != (Rs2_sd < 0); 28611724Sar4jc@virginia.edu 28711724Sar4jc@virginia.edu uint64_t Rs1_lo = (uint32_t)std::abs(Rs1_sd); 28811724Sar4jc@virginia.edu uint64_t Rs1_hi = (uint64_t)std::abs(Rs1_sd) >> 32; 28911724Sar4jc@virginia.edu uint64_t Rs2_lo = (uint32_t)std::abs(Rs2_sd); 29011724Sar4jc@virginia.edu uint64_t Rs2_hi = (uint64_t)std::abs(Rs2_sd) >> 32; 29111724Sar4jc@virginia.edu 29211724Sar4jc@virginia.edu uint64_t hi = Rs1_hi*Rs2_hi; 29311724Sar4jc@virginia.edu uint64_t mid1 = Rs1_hi*Rs2_lo; 29411724Sar4jc@virginia.edu uint64_t mid2 = Rs1_lo*Rs2_hi; 29511724Sar4jc@virginia.edu uint64_t lo = Rs2_lo*Rs1_lo; 29611724Sar4jc@virginia.edu uint64_t carry = ((uint64_t)(uint32_t)mid1 29711724Sar4jc@virginia.edu + (uint64_t)(uint32_t)mid2 + (lo >> 32)) >> 32; 29811724Sar4jc@virginia.edu 29911724Sar4jc@virginia.edu uint64_t res = hi + (mid1 >> 32) + (mid2 >> 32) + carry; 30011724Sar4jc@virginia.edu Rd = negate ? ~res + (Rs1_sd*Rs2_sd == 0 ? 1 : 0) : res; 30111724Sar4jc@virginia.edu }}, IntMultOp); 30211723Sar4jc@virginia.edu } 30311723Sar4jc@virginia.edu 0x2: decode FUNCT7 { 30411723Sar4jc@virginia.edu 0x0: slt({{ 30511723Sar4jc@virginia.edu Rd = (Rs1_sd < Rs2_sd) ? 1 : 0; 30611723Sar4jc@virginia.edu }}); 30711724Sar4jc@virginia.edu 0x1: mulhsu({{ 30811724Sar4jc@virginia.edu bool negate = Rs1_sd < 0; 30911724Sar4jc@virginia.edu uint64_t Rs1_lo = (uint32_t)std::abs(Rs1_sd); 31011724Sar4jc@virginia.edu uint64_t Rs1_hi = (uint64_t)std::abs(Rs1_sd) >> 32; 31111724Sar4jc@virginia.edu uint64_t Rs2_lo = (uint32_t)Rs2; 31211724Sar4jc@virginia.edu uint64_t Rs2_hi = Rs2 >> 32; 31311724Sar4jc@virginia.edu 31411724Sar4jc@virginia.edu uint64_t hi = Rs1_hi*Rs2_hi; 31511724Sar4jc@virginia.edu uint64_t mid1 = Rs1_hi*Rs2_lo; 31611724Sar4jc@virginia.edu uint64_t mid2 = Rs1_lo*Rs2_hi; 31711724Sar4jc@virginia.edu uint64_t lo = Rs1_lo*Rs2_lo; 31811724Sar4jc@virginia.edu uint64_t carry = ((uint64_t)(uint32_t)mid1 31911724Sar4jc@virginia.edu + (uint64_t)(uint32_t)mid2 + (lo >> 32)) >> 32; 32011724Sar4jc@virginia.edu 32111724Sar4jc@virginia.edu uint64_t res = hi + (mid1 >> 32) + (mid2 >> 32) + carry; 32211724Sar4jc@virginia.edu Rd = negate ? ~res + (Rs1_sd*Rs2 == 0 ? 1 : 0) : res; 32311724Sar4jc@virginia.edu }}, IntMultOp); 32411723Sar4jc@virginia.edu } 32511723Sar4jc@virginia.edu 0x3: decode FUNCT7 { 32611723Sar4jc@virginia.edu 0x0: sltu({{ 32711723Sar4jc@virginia.edu Rd = (Rs1 < Rs2) ? 1 : 0; 32811723Sar4jc@virginia.edu }}); 32911724Sar4jc@virginia.edu 0x1: mulhu({{ 33011724Sar4jc@virginia.edu uint64_t Rs1_lo = (uint32_t)Rs1; 33111724Sar4jc@virginia.edu uint64_t Rs1_hi = Rs1 >> 32; 33211724Sar4jc@virginia.edu uint64_t Rs2_lo = (uint32_t)Rs2; 33311724Sar4jc@virginia.edu uint64_t Rs2_hi = Rs2 >> 32; 33411724Sar4jc@virginia.edu 33511724Sar4jc@virginia.edu uint64_t hi = Rs1_hi*Rs2_hi; 33611724Sar4jc@virginia.edu uint64_t mid1 = Rs1_hi*Rs2_lo; 33711724Sar4jc@virginia.edu uint64_t mid2 = Rs1_lo*Rs2_hi; 33811724Sar4jc@virginia.edu uint64_t lo = Rs1_lo*Rs2_lo; 33911724Sar4jc@virginia.edu uint64_t carry = ((uint64_t)(uint32_t)mid1 34011724Sar4jc@virginia.edu + (uint64_t)(uint32_t)mid2 + (lo >> 32)) >> 32; 34111724Sar4jc@virginia.edu 34211724Sar4jc@virginia.edu Rd = hi + (mid1 >> 32) + (mid2 >> 32) + carry; 34311724Sar4jc@virginia.edu }}, IntMultOp); 34411723Sar4jc@virginia.edu } 34511723Sar4jc@virginia.edu 0x4: decode FUNCT7 { 34611723Sar4jc@virginia.edu 0x0: xor({{ 34711723Sar4jc@virginia.edu Rd = Rs1 ^ Rs2; 34811723Sar4jc@virginia.edu }}); 34911724Sar4jc@virginia.edu 0x1: div({{ 35011724Sar4jc@virginia.edu if (Rs2_sd == 0) { 35111724Sar4jc@virginia.edu Rd_sd = -1; 35211724Sar4jc@virginia.edu } else if (Rs1_sd == std::numeric_limits<int64_t>::min() 35311724Sar4jc@virginia.edu && Rs2_sd == -1) { 35411724Sar4jc@virginia.edu Rd_sd = std::numeric_limits<int64_t>::min(); 35511724Sar4jc@virginia.edu } else { 35611724Sar4jc@virginia.edu Rd_sd = Rs1_sd/Rs2_sd; 35711724Sar4jc@virginia.edu } 35811724Sar4jc@virginia.edu }}, IntDivOp); 35911723Sar4jc@virginia.edu } 36011723Sar4jc@virginia.edu 0x5: decode FUNCT7 { 36111723Sar4jc@virginia.edu 0x0: srl({{ 36211723Sar4jc@virginia.edu Rd = Rs1 >> Rs2<5:0>; 36311723Sar4jc@virginia.edu }}); 36411724Sar4jc@virginia.edu 0x1: divu({{ 36511724Sar4jc@virginia.edu if (Rs2 == 0) { 36611724Sar4jc@virginia.edu Rd = std::numeric_limits<uint64_t>::max(); 36711724Sar4jc@virginia.edu } else { 36811724Sar4jc@virginia.edu Rd = Rs1/Rs2; 36911724Sar4jc@virginia.edu } 37011724Sar4jc@virginia.edu }}, IntDivOp); 37111723Sar4jc@virginia.edu 0x20: sra({{ 37211723Sar4jc@virginia.edu Rd_sd = Rs1_sd >> Rs2<5:0>; 37311723Sar4jc@virginia.edu }}); 37411723Sar4jc@virginia.edu } 37511723Sar4jc@virginia.edu 0x6: decode FUNCT7 { 37611723Sar4jc@virginia.edu 0x0: or({{ 37711723Sar4jc@virginia.edu Rd = Rs1 | Rs2; 37811723Sar4jc@virginia.edu }}); 37911724Sar4jc@virginia.edu 0x1: rem({{ 38011724Sar4jc@virginia.edu if (Rs2_sd == 0) { 38111724Sar4jc@virginia.edu Rd = Rs1_sd; 38211724Sar4jc@virginia.edu } else if (Rs1_sd == std::numeric_limits<int64_t>::min() 38311724Sar4jc@virginia.edu && Rs2_sd == -1) { 38411724Sar4jc@virginia.edu Rd = 0; 38511724Sar4jc@virginia.edu } else { 38611724Sar4jc@virginia.edu Rd = Rs1_sd%Rs2_sd; 38711724Sar4jc@virginia.edu } 38811724Sar4jc@virginia.edu }}, IntDivOp); 38911723Sar4jc@virginia.edu } 39011723Sar4jc@virginia.edu 0x7: decode FUNCT7 { 39111723Sar4jc@virginia.edu 0x0: and({{ 39211723Sar4jc@virginia.edu Rd = Rs1 & Rs2; 39311723Sar4jc@virginia.edu }}); 39411724Sar4jc@virginia.edu 0x1: remu({{ 39511724Sar4jc@virginia.edu if (Rs2 == 0) { 39611724Sar4jc@virginia.edu Rd = Rs1; 39711724Sar4jc@virginia.edu } else { 39811724Sar4jc@virginia.edu Rd = Rs1%Rs2; 39911724Sar4jc@virginia.edu } 40011724Sar4jc@virginia.edu }}, IntDivOp); 40111723Sar4jc@virginia.edu } 40211723Sar4jc@virginia.edu } 40311723Sar4jc@virginia.edu } 40411723Sar4jc@virginia.edu 40511723Sar4jc@virginia.edu 0x37: UOp::lui({{ 40611723Sar4jc@virginia.edu Rd = (uint64_t)imm; 40711723Sar4jc@virginia.edu }}); 40811723Sar4jc@virginia.edu 40911723Sar4jc@virginia.edu 0x3b: decode FUNCT3 { 41011723Sar4jc@virginia.edu format ROp { 41111723Sar4jc@virginia.edu 0x0: decode FUNCT7 { 41211723Sar4jc@virginia.edu 0x0: addw({{ 41311723Sar4jc@virginia.edu Rd_sd = Rs1_sw + Rs2_sw; 41411723Sar4jc@virginia.edu }}); 41511724Sar4jc@virginia.edu 0x1: mulw({{ 41611724Sar4jc@virginia.edu Rd_sd = (int32_t)(Rs1_sw*Rs2_sw); 41711724Sar4jc@virginia.edu }}, IntMultOp); 41811723Sar4jc@virginia.edu 0x20: subw({{ 41911723Sar4jc@virginia.edu Rd_sd = Rs1_sw - Rs2_sw; 42011723Sar4jc@virginia.edu }}); 42111723Sar4jc@virginia.edu } 42211723Sar4jc@virginia.edu 0x1: sllw({{ 42311723Sar4jc@virginia.edu Rd_sd = Rs1_sw << Rs2<4:0>; 42411723Sar4jc@virginia.edu }}); 42511724Sar4jc@virginia.edu 0x4: divw({{ 42611724Sar4jc@virginia.edu if (Rs2_sw == 0) { 42711724Sar4jc@virginia.edu Rd_sd = -1; 42811724Sar4jc@virginia.edu } else if (Rs1_sw == std::numeric_limits<int32_t>::min() 42911724Sar4jc@virginia.edu && Rs2_sw == -1) { 43011724Sar4jc@virginia.edu Rd_sd = std::numeric_limits<int32_t>::min(); 43111724Sar4jc@virginia.edu } else { 43211724Sar4jc@virginia.edu Rd_sd = Rs1_sw/Rs2_sw; 43311724Sar4jc@virginia.edu } 43411724Sar4jc@virginia.edu }}, IntDivOp); 43511723Sar4jc@virginia.edu 0x5: decode FUNCT7 { 43611723Sar4jc@virginia.edu 0x0: srlw({{ 43711723Sar4jc@virginia.edu Rd_uw = Rs1_uw >> Rs2<4:0>; 43811723Sar4jc@virginia.edu }}); 43911724Sar4jc@virginia.edu 0x1: divuw({{ 44011724Sar4jc@virginia.edu if (Rs2_uw == 0) { 44111724Sar4jc@virginia.edu Rd_sd = std::numeric_limits<IntReg>::max(); 44211724Sar4jc@virginia.edu } else { 44311724Sar4jc@virginia.edu Rd_sd = (int32_t)(Rs1_uw/Rs2_uw); 44411724Sar4jc@virginia.edu } 44511724Sar4jc@virginia.edu }}, IntDivOp); 44611723Sar4jc@virginia.edu 0x20: sraw({{ 44711723Sar4jc@virginia.edu Rd_sd = Rs1_sw >> Rs2<4:0>; 44811723Sar4jc@virginia.edu }}); 44911723Sar4jc@virginia.edu } 45011724Sar4jc@virginia.edu 0x6: remw({{ 45111724Sar4jc@virginia.edu if (Rs2_sw == 0) { 45211724Sar4jc@virginia.edu Rd_sd = Rs1_sw; 45311724Sar4jc@virginia.edu } else if (Rs1_sw == std::numeric_limits<int32_t>::min() 45411724Sar4jc@virginia.edu && Rs2_sw == -1) { 45511724Sar4jc@virginia.edu Rd_sd = 0; 45611724Sar4jc@virginia.edu } else { 45711724Sar4jc@virginia.edu Rd_sd = Rs1_sw%Rs2_sw; 45811724Sar4jc@virginia.edu } 45911724Sar4jc@virginia.edu }}, IntDivOp); 46011724Sar4jc@virginia.edu 0x7: remuw({{ 46111724Sar4jc@virginia.edu if (Rs2_uw == 0) { 46211724Sar4jc@virginia.edu Rd_sd = (int32_t)Rs1_uw; 46311724Sar4jc@virginia.edu } else { 46411724Sar4jc@virginia.edu Rd_sd = (int32_t)(Rs1_uw%Rs2_uw); 46511724Sar4jc@virginia.edu } 46611724Sar4jc@virginia.edu }}, IntDivOp); 46711723Sar4jc@virginia.edu } 46811723Sar4jc@virginia.edu } 46911723Sar4jc@virginia.edu 47011725Sar4jc@virginia.edu format FPR4Op { 47111725Sar4jc@virginia.edu 0x43: decode FUNCT2 { 47211725Sar4jc@virginia.edu 0x0: fmadd_s({{ 47311725Sar4jc@virginia.edu uint32_t temp; 47411725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 47511725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 47611725Sar4jc@virginia.edu float fs3 = reinterpret_cast<float&>(temp = Fs3_bits); 47711725Sar4jc@virginia.edu float fd; 47811725Sar4jc@virginia.edu 47911725Sar4jc@virginia.edu if (std::isnan(fs1) || std::isnan(fs2) || std::isnan(fs3)) { 48011725Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2) 48111725Sar4jc@virginia.edu || issignalingnan(fs3)) { 48211725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 48311725Sar4jc@virginia.edu } 48411725Sar4jc@virginia.edu fd = std::numeric_limits<float>::quiet_NaN(); 48511725Sar4jc@virginia.edu } else if (std::isinf(fs1) || std::isinf(fs2) || 48611725Sar4jc@virginia.edu std::isinf(fs3)) { 48711725Sar4jc@virginia.edu if (std::signbit(fs1) == std::signbit(fs2) 48811725Sar4jc@virginia.edu && !std::isinf(fs3)) { 48911725Sar4jc@virginia.edu fd = std::numeric_limits<float>::infinity(); 49011725Sar4jc@virginia.edu } else if (std::signbit(fs1) != std::signbit(fs2) 49111725Sar4jc@virginia.edu && !std::isinf(fs3)) { 49211725Sar4jc@virginia.edu fd = -std::numeric_limits<float>::infinity(); 49311725Sar4jc@virginia.edu } else { // Fs3_sf is infinity 49411725Sar4jc@virginia.edu fd = fs3; 49511725Sar4jc@virginia.edu } 49611725Sar4jc@virginia.edu } else { 49711725Sar4jc@virginia.edu fd = fs1*fs2 + fs3; 49811725Sar4jc@virginia.edu } 49911725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 50011725Sar4jc@virginia.edu }}, FloatMultOp); 50111725Sar4jc@virginia.edu 0x1: fmadd_d({{ 50211725Sar4jc@virginia.edu if (std::isnan(Fs1) || std::isnan(Fs2) || std::isnan(Fs3)) { 50311725Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2) 50411725Sar4jc@virginia.edu || issignalingnan(Fs3)) { 50511725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 50611725Sar4jc@virginia.edu } 50711725Sar4jc@virginia.edu Fd = std::numeric_limits<double>::quiet_NaN(); 50811725Sar4jc@virginia.edu } else if (std::isinf(Fs1) || std::isinf(Fs2) || 50911725Sar4jc@virginia.edu std::isinf(Fs3)) { 51011725Sar4jc@virginia.edu if (std::signbit(Fs1) == std::signbit(Fs2) 51111725Sar4jc@virginia.edu && !std::isinf(Fs3)) { 51211725Sar4jc@virginia.edu Fd = std::numeric_limits<double>::infinity(); 51311725Sar4jc@virginia.edu } else if (std::signbit(Fs1) != std::signbit(Fs2) 51411725Sar4jc@virginia.edu && !std::isinf(Fs3)) { 51511725Sar4jc@virginia.edu Fd = -std::numeric_limits<double>::infinity(); 51611725Sar4jc@virginia.edu } else { 51711725Sar4jc@virginia.edu Fd = Fs3; 51811725Sar4jc@virginia.edu } 51911725Sar4jc@virginia.edu } else { 52011725Sar4jc@virginia.edu Fd = Fs1*Fs2 + Fs3; 52111725Sar4jc@virginia.edu } 52211725Sar4jc@virginia.edu }}, FloatMultOp); 52311725Sar4jc@virginia.edu } 52411725Sar4jc@virginia.edu 0x47: decode FUNCT2 { 52511725Sar4jc@virginia.edu 0x0: fmsub_s({{ 52611725Sar4jc@virginia.edu uint32_t temp; 52711725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 52811725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 52911725Sar4jc@virginia.edu float fs3 = reinterpret_cast<float&>(temp = Fs3_bits); 53011725Sar4jc@virginia.edu float fd; 53111725Sar4jc@virginia.edu 53211725Sar4jc@virginia.edu if (std::isnan(fs1) || std::isnan(fs2) || std::isnan(fs3)) { 53311725Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2) 53411725Sar4jc@virginia.edu || issignalingnan(fs3)) { 53511725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 53611725Sar4jc@virginia.edu } 53711725Sar4jc@virginia.edu fd = std::numeric_limits<float>::quiet_NaN(); 53811725Sar4jc@virginia.edu } else if (std::isinf(fs1) || std::isinf(fs2) || 53911725Sar4jc@virginia.edu std::isinf(fs3)) { 54011725Sar4jc@virginia.edu if (std::signbit(fs1) == std::signbit(fs2) 54111725Sar4jc@virginia.edu && !std::isinf(fs3)) { 54211725Sar4jc@virginia.edu fd = std::numeric_limits<float>::infinity(); 54311725Sar4jc@virginia.edu } else if (std::signbit(fs1) != std::signbit(fs2) 54411725Sar4jc@virginia.edu && !std::isinf(fs3)) { 54511725Sar4jc@virginia.edu fd = -std::numeric_limits<float>::infinity(); 54611725Sar4jc@virginia.edu } else { // Fs3_sf is infinity 54711725Sar4jc@virginia.edu fd = -fs3; 54811725Sar4jc@virginia.edu } 54911725Sar4jc@virginia.edu } else { 55011725Sar4jc@virginia.edu fd = fs1*fs2 - fs3; 55111725Sar4jc@virginia.edu } 55211725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 55311725Sar4jc@virginia.edu }}, FloatMultOp); 55411725Sar4jc@virginia.edu 0x1: fmsub_d({{ 55511725Sar4jc@virginia.edu if (std::isnan(Fs1) || std::isnan(Fs2) || std::isnan(Fs3)) { 55611725Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2) 55711725Sar4jc@virginia.edu || issignalingnan(Fs3)) { 55811725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 55911725Sar4jc@virginia.edu } 56011725Sar4jc@virginia.edu Fd = std::numeric_limits<double>::quiet_NaN(); 56111725Sar4jc@virginia.edu } else if (std::isinf(Fs1) || std::isinf(Fs2) || 56211725Sar4jc@virginia.edu std::isinf(Fs3)) { 56311725Sar4jc@virginia.edu if (std::signbit(Fs1) == std::signbit(Fs2) 56411725Sar4jc@virginia.edu && !std::isinf(Fs3)) { 56511725Sar4jc@virginia.edu Fd = std::numeric_limits<double>::infinity(); 56611725Sar4jc@virginia.edu } else if (std::signbit(Fs1) != std::signbit(Fs2) 56711725Sar4jc@virginia.edu && !std::isinf(Fs3)) { 56811725Sar4jc@virginia.edu Fd = -std::numeric_limits<double>::infinity(); 56911725Sar4jc@virginia.edu } else { 57011725Sar4jc@virginia.edu Fd = -Fs3; 57111725Sar4jc@virginia.edu } 57211725Sar4jc@virginia.edu } else { 57311725Sar4jc@virginia.edu Fd = Fs1*Fs2 - Fs3; 57411725Sar4jc@virginia.edu } 57511725Sar4jc@virginia.edu }}, FloatMultOp); 57611725Sar4jc@virginia.edu } 57711725Sar4jc@virginia.edu 0x4b: decode FUNCT2 { 57811725Sar4jc@virginia.edu 0x0: fnmsub_s({{ 57911725Sar4jc@virginia.edu uint32_t temp; 58011725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 58111725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 58211725Sar4jc@virginia.edu float fs3 = reinterpret_cast<float&>(temp = Fs3_bits); 58311725Sar4jc@virginia.edu float fd; 58411725Sar4jc@virginia.edu 58511725Sar4jc@virginia.edu if (std::isnan(fs1) || std::isnan(fs2) || std::isnan(fs3)) { 58611725Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2) 58711725Sar4jc@virginia.edu || issignalingnan(fs3)) { 58811725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 58911725Sar4jc@virginia.edu } 59011725Sar4jc@virginia.edu fd = std::numeric_limits<float>::quiet_NaN(); 59111725Sar4jc@virginia.edu } else if (std::isinf(fs1) || std::isinf(fs2) || 59211725Sar4jc@virginia.edu std::isinf(fs3)) { 59311725Sar4jc@virginia.edu if (std::signbit(fs1) == std::signbit(fs2) 59411725Sar4jc@virginia.edu && !std::isinf(fs3)) { 59511725Sar4jc@virginia.edu fd = -std::numeric_limits<float>::infinity(); 59611725Sar4jc@virginia.edu } else if (std::signbit(fs1) != std::signbit(fs2) 59711725Sar4jc@virginia.edu && !std::isinf(fs3)) { 59811725Sar4jc@virginia.edu fd = std::numeric_limits<float>::infinity(); 59911725Sar4jc@virginia.edu } else { // Fs3_sf is infinity 60011725Sar4jc@virginia.edu fd = fs3; 60111725Sar4jc@virginia.edu } 60211725Sar4jc@virginia.edu } else { 60311725Sar4jc@virginia.edu fd = -(fs1*fs2 - fs3); 60411725Sar4jc@virginia.edu } 60511725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 60611725Sar4jc@virginia.edu }}, FloatMultOp); 60711725Sar4jc@virginia.edu 0x1: fnmsub_d({{ 60811725Sar4jc@virginia.edu if (std::isnan(Fs1) || std::isnan(Fs2) || std::isnan(Fs3)) { 60911725Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2) 61011725Sar4jc@virginia.edu || issignalingnan(Fs3)) { 61111725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 61211725Sar4jc@virginia.edu } 61311725Sar4jc@virginia.edu Fd = std::numeric_limits<double>::quiet_NaN(); 61411725Sar4jc@virginia.edu } else if (std::isinf(Fs1) || std::isinf(Fs2) 61511725Sar4jc@virginia.edu || std::isinf(Fs3)) { 61611725Sar4jc@virginia.edu if (std::signbit(Fs1) == std::signbit(Fs2) 61711725Sar4jc@virginia.edu && !std::isinf(Fs3)) { 61811725Sar4jc@virginia.edu Fd = -std::numeric_limits<double>::infinity(); 61911725Sar4jc@virginia.edu } else if (std::signbit(Fs1) != std::signbit(Fs2) 62011725Sar4jc@virginia.edu && !std::isinf(Fs3)) { 62111725Sar4jc@virginia.edu Fd = std::numeric_limits<double>::infinity(); 62211725Sar4jc@virginia.edu } else { 62311725Sar4jc@virginia.edu Fd = Fs3; 62411725Sar4jc@virginia.edu } 62511725Sar4jc@virginia.edu } else { 62611725Sar4jc@virginia.edu Fd = -(Fs1*Fs2 - Fs3); 62711725Sar4jc@virginia.edu } 62811725Sar4jc@virginia.edu }}, FloatMultOp); 62911725Sar4jc@virginia.edu } 63011725Sar4jc@virginia.edu 0x4f: decode FUNCT2 { 63111725Sar4jc@virginia.edu 0x0: fnmadd_s({{ 63211725Sar4jc@virginia.edu uint32_t temp; 63311725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 63411725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 63511725Sar4jc@virginia.edu float fs3 = reinterpret_cast<float&>(temp = Fs3_bits); 63611725Sar4jc@virginia.edu float fd; 63711725Sar4jc@virginia.edu 63811725Sar4jc@virginia.edu if (std::isnan(fs1) || std::isnan(fs2) || std::isnan(fs3)) { 63911725Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2) 64011725Sar4jc@virginia.edu || issignalingnan(fs3)) { 64111725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 64211725Sar4jc@virginia.edu } 64311725Sar4jc@virginia.edu fd = std::numeric_limits<float>::quiet_NaN(); 64411725Sar4jc@virginia.edu } else if (std::isinf(fs1) || std::isinf(fs2) || 64511725Sar4jc@virginia.edu std::isinf(fs3)) { 64611725Sar4jc@virginia.edu if (std::signbit(fs1) == std::signbit(fs2) 64711725Sar4jc@virginia.edu && !std::isinf(fs3)) { 64811725Sar4jc@virginia.edu fd = -std::numeric_limits<float>::infinity(); 64911725Sar4jc@virginia.edu } else if (std::signbit(fs1) != std::signbit(fs2) 65011725Sar4jc@virginia.edu && !std::isinf(fs3)) { 65111725Sar4jc@virginia.edu fd = std::numeric_limits<float>::infinity(); 65211725Sar4jc@virginia.edu } else { // Fs3_sf is infinity 65311725Sar4jc@virginia.edu fd = -fs3; 65411725Sar4jc@virginia.edu } 65511725Sar4jc@virginia.edu } else { 65611725Sar4jc@virginia.edu fd = -(fs1*fs2 + fs3); 65711725Sar4jc@virginia.edu } 65811725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 65911725Sar4jc@virginia.edu }}, FloatMultOp); 66011725Sar4jc@virginia.edu 0x1: fnmadd_d({{ 66111725Sar4jc@virginia.edu if (std::isnan(Fs1) || std::isnan(Fs2) || std::isnan(Fs3)) { 66211725Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2) 66311725Sar4jc@virginia.edu || issignalingnan(Fs3)) { 66411725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 66511725Sar4jc@virginia.edu } 66611725Sar4jc@virginia.edu Fd = std::numeric_limits<double>::quiet_NaN(); 66711725Sar4jc@virginia.edu } else if (std::isinf(Fs1) || std::isinf(Fs2) || 66811725Sar4jc@virginia.edu std::isinf(Fs3)) { 66911725Sar4jc@virginia.edu if (std::signbit(Fs1) == std::signbit(Fs2) 67011725Sar4jc@virginia.edu && !std::isinf(Fs3)) { 67111725Sar4jc@virginia.edu Fd = -std::numeric_limits<double>::infinity(); 67211725Sar4jc@virginia.edu } else if (std::signbit(Fs1) != std::signbit(Fs2) 67311725Sar4jc@virginia.edu && !std::isinf(Fs3)) { 67411725Sar4jc@virginia.edu Fd = std::numeric_limits<double>::infinity(); 67511725Sar4jc@virginia.edu } else { 67611725Sar4jc@virginia.edu Fd = -Fs3; 67711725Sar4jc@virginia.edu } 67811725Sar4jc@virginia.edu } else { 67911725Sar4jc@virginia.edu Fd = -(Fs1*Fs2 + Fs3); 68011725Sar4jc@virginia.edu } 68111725Sar4jc@virginia.edu }}, FloatMultOp); 68211725Sar4jc@virginia.edu } 68311725Sar4jc@virginia.edu } 68411725Sar4jc@virginia.edu 68511725Sar4jc@virginia.edu 0x53: decode FUNCT7 { 68611725Sar4jc@virginia.edu format FPROp { 68711725Sar4jc@virginia.edu 0x0: fadd_s({{ 68811725Sar4jc@virginia.edu uint32_t temp; 68911725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 69011725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 69111725Sar4jc@virginia.edu float fd; 69211725Sar4jc@virginia.edu 69311725Sar4jc@virginia.edu if (std::isnan(fs1) || std::isnan(fs2)) { 69411725Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2)) { 69511725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 69611725Sar4jc@virginia.edu } 69711725Sar4jc@virginia.edu fd = std::numeric_limits<float>::quiet_NaN(); 69811725Sar4jc@virginia.edu } else { 69911725Sar4jc@virginia.edu fd = fs1 + fs2; 70011725Sar4jc@virginia.edu } 70111725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 70211725Sar4jc@virginia.edu }}, FloatAddOp); 70311725Sar4jc@virginia.edu 0x1: fadd_d({{ 70411725Sar4jc@virginia.edu if (std::isnan(Fs1) || std::isnan(Fs2)) { 70511725Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2)) { 70611725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 70711725Sar4jc@virginia.edu } 70811725Sar4jc@virginia.edu Fd = std::numeric_limits<double>::quiet_NaN(); 70911725Sar4jc@virginia.edu } else { 71011725Sar4jc@virginia.edu Fd = Fs1 + Fs2; 71111725Sar4jc@virginia.edu } 71211725Sar4jc@virginia.edu }}, FloatAddOp); 71311725Sar4jc@virginia.edu 0x4: fsub_s({{ 71411725Sar4jc@virginia.edu uint32_t temp; 71511725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 71611725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 71711725Sar4jc@virginia.edu float fd; 71811725Sar4jc@virginia.edu 71911725Sar4jc@virginia.edu if (std::isnan(fs1) || std::isnan(fs2)) { 72011725Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2)) { 72111725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 72211725Sar4jc@virginia.edu } 72311725Sar4jc@virginia.edu fd = std::numeric_limits<float>::quiet_NaN(); 72411725Sar4jc@virginia.edu } else { 72511725Sar4jc@virginia.edu fd = fs1 - fs2; 72611725Sar4jc@virginia.edu } 72711725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 72811725Sar4jc@virginia.edu }}, FloatAddOp); 72911725Sar4jc@virginia.edu 0x5: fsub_d({{ 73011725Sar4jc@virginia.edu if (std::isnan(Fs1) || std::isnan(Fs2)) { 73111725Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2)) { 73211725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 73311725Sar4jc@virginia.edu } 73411725Sar4jc@virginia.edu Fd = std::numeric_limits<double>::quiet_NaN(); 73511725Sar4jc@virginia.edu } else { 73611725Sar4jc@virginia.edu Fd = Fs1 - Fs2; 73711725Sar4jc@virginia.edu } 73811725Sar4jc@virginia.edu }}, FloatAddOp); 73911725Sar4jc@virginia.edu 0x8: fmul_s({{ 74011725Sar4jc@virginia.edu uint32_t temp; 74111725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 74211725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 74311725Sar4jc@virginia.edu float fd; 74411725Sar4jc@virginia.edu 74511725Sar4jc@virginia.edu if (std::isnan(fs1) || std::isnan(fs2)) { 74611725Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2)) { 74711725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 74811725Sar4jc@virginia.edu } 74911725Sar4jc@virginia.edu fd = std::numeric_limits<float>::quiet_NaN(); 75011725Sar4jc@virginia.edu } else { 75111725Sar4jc@virginia.edu fd = fs1*fs2; 75211725Sar4jc@virginia.edu } 75311725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 75411725Sar4jc@virginia.edu }}, FloatMultOp); 75511725Sar4jc@virginia.edu 0x9: fmul_d({{ 75611725Sar4jc@virginia.edu if (std::isnan(Fs1) || std::isnan(Fs2)) { 75711725Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2)) { 75811725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 75911725Sar4jc@virginia.edu } 76011725Sar4jc@virginia.edu Fd = std::numeric_limits<double>::quiet_NaN(); 76111725Sar4jc@virginia.edu } else { 76211725Sar4jc@virginia.edu Fd = Fs1*Fs2; 76311725Sar4jc@virginia.edu } 76411725Sar4jc@virginia.edu }}, FloatMultOp); 76511725Sar4jc@virginia.edu 0xc: fdiv_s({{ 76611725Sar4jc@virginia.edu uint32_t temp; 76711725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 76811725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 76911725Sar4jc@virginia.edu float fd; 77011725Sar4jc@virginia.edu 77111725Sar4jc@virginia.edu if (std::isnan(fs1) || std::isnan(fs2)) { 77211725Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2)) { 77311725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 77411725Sar4jc@virginia.edu } 77511725Sar4jc@virginia.edu fd = std::numeric_limits<float>::quiet_NaN(); 77611725Sar4jc@virginia.edu } else { 77711725Sar4jc@virginia.edu fd = fs1/fs2; 77811725Sar4jc@virginia.edu } 77911725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 78011725Sar4jc@virginia.edu }}, FloatDivOp); 78111725Sar4jc@virginia.edu 0xd: fdiv_d({{ 78211725Sar4jc@virginia.edu if (std::isnan(Fs1) || std::isnan(Fs2)) { 78311725Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2)) { 78411725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 78511725Sar4jc@virginia.edu } 78611725Sar4jc@virginia.edu Fd = std::numeric_limits<double>::quiet_NaN(); 78711725Sar4jc@virginia.edu } else { 78811725Sar4jc@virginia.edu Fd = Fs1/Fs2; 78911725Sar4jc@virginia.edu } 79011725Sar4jc@virginia.edu }}, FloatDivOp); 79111725Sar4jc@virginia.edu 0x10: decode ROUND_MODE { 79211725Sar4jc@virginia.edu 0x0: fsgnj_s({{ 79311725Sar4jc@virginia.edu uint32_t temp; 79411725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 79511725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 79611725Sar4jc@virginia.edu float fd; 79711725Sar4jc@virginia.edu 79811725Sar4jc@virginia.edu if (issignalingnan(fs1)) { 79911725Sar4jc@virginia.edu fd = std::numeric_limits<float>::signaling_NaN(); 80011725Sar4jc@virginia.edu std::feclearexcept(FE_INVALID); 80111725Sar4jc@virginia.edu } else { 80211725Sar4jc@virginia.edu fd = std::copysign(fs1, fs2); 80311725Sar4jc@virginia.edu } 80411725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 80511725Sar4jc@virginia.edu }}); 80611725Sar4jc@virginia.edu 0x1: fsgnjn_s({{ 80711725Sar4jc@virginia.edu uint32_t temp; 80811725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 80911725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 81011725Sar4jc@virginia.edu float fd; 81111725Sar4jc@virginia.edu 81211725Sar4jc@virginia.edu if (issignalingnan(fs1)) { 81311725Sar4jc@virginia.edu fd = std::numeric_limits<float>::signaling_NaN(); 81411725Sar4jc@virginia.edu std::feclearexcept(FE_INVALID); 81511725Sar4jc@virginia.edu } else { 81611725Sar4jc@virginia.edu fd = std::copysign(fs1, -fs2); 81711725Sar4jc@virginia.edu } 81811725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 81911725Sar4jc@virginia.edu }}); 82011725Sar4jc@virginia.edu 0x2: fsgnjx_s({{ 82111725Sar4jc@virginia.edu uint32_t temp; 82211725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 82311725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 82411725Sar4jc@virginia.edu float fd; 82511725Sar4jc@virginia.edu 82611725Sar4jc@virginia.edu if (issignalingnan(fs1)) { 82711725Sar4jc@virginia.edu fd = std::numeric_limits<float>::signaling_NaN(); 82811725Sar4jc@virginia.edu std::feclearexcept(FE_INVALID); 82911725Sar4jc@virginia.edu } else { 83011725Sar4jc@virginia.edu fd = fs1*(std::signbit(fs2) ? -1.0 : 1.0); 83111725Sar4jc@virginia.edu } 83211725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 83311725Sar4jc@virginia.edu }}); 83411725Sar4jc@virginia.edu } 83511725Sar4jc@virginia.edu 0x11: decode ROUND_MODE { 83611725Sar4jc@virginia.edu 0x0: fsgnj_d({{ 83711725Sar4jc@virginia.edu if (issignalingnan(Fs1)) { 83811725Sar4jc@virginia.edu Fd = std::numeric_limits<double>::signaling_NaN(); 83911725Sar4jc@virginia.edu std::feclearexcept(FE_INVALID); 84011725Sar4jc@virginia.edu } else { 84111725Sar4jc@virginia.edu Fd = std::copysign(Fs1, Fs2); 84211725Sar4jc@virginia.edu } 84311725Sar4jc@virginia.edu }}); 84411725Sar4jc@virginia.edu 0x1: fsgnjn_d({{ 84511725Sar4jc@virginia.edu if (issignalingnan(Fs1)) { 84611725Sar4jc@virginia.edu Fd = std::numeric_limits<double>::signaling_NaN(); 84711725Sar4jc@virginia.edu std::feclearexcept(FE_INVALID); 84811725Sar4jc@virginia.edu } else { 84911725Sar4jc@virginia.edu Fd = std::copysign(Fs1, -Fs2); 85011725Sar4jc@virginia.edu } 85111725Sar4jc@virginia.edu }}); 85211725Sar4jc@virginia.edu 0x2: fsgnjx_d({{ 85311725Sar4jc@virginia.edu if (issignalingnan(Fs1)) { 85411725Sar4jc@virginia.edu Fd = std::numeric_limits<double>::signaling_NaN(); 85511725Sar4jc@virginia.edu std::feclearexcept(FE_INVALID); 85611725Sar4jc@virginia.edu } else { 85711725Sar4jc@virginia.edu Fd = Fs1*(std::signbit(Fs2) ? -1.0 : 1.0); 85811725Sar4jc@virginia.edu } 85911725Sar4jc@virginia.edu }}); 86011725Sar4jc@virginia.edu } 86111725Sar4jc@virginia.edu 0x14: decode ROUND_MODE { 86211725Sar4jc@virginia.edu 0x0: fmin_s({{ 86311725Sar4jc@virginia.edu uint32_t temp; 86411725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 86511725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 86611725Sar4jc@virginia.edu float fd; 86711725Sar4jc@virginia.edu 86811725Sar4jc@virginia.edu if (issignalingnan(fs2)) { 86911725Sar4jc@virginia.edu fd = fs1; 87011725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 87111725Sar4jc@virginia.edu } else if (issignalingnan(fs1)) { 87211725Sar4jc@virginia.edu fd = fs2; 87311725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 87411725Sar4jc@virginia.edu } else { 87511725Sar4jc@virginia.edu fd = std::fmin(fs1, fs2); 87611725Sar4jc@virginia.edu } 87711725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 87811725Sar4jc@virginia.edu }}, FloatCmpOp); 87911725Sar4jc@virginia.edu 0x1: fmax_s({{ 88011725Sar4jc@virginia.edu uint32_t temp; 88111725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 88211725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 88311725Sar4jc@virginia.edu float fd; 88411725Sar4jc@virginia.edu 88511725Sar4jc@virginia.edu if (issignalingnan(fs2)) { 88611725Sar4jc@virginia.edu fd = fs1; 88711725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 88811725Sar4jc@virginia.edu } else if (issignalingnan(fs1)) { 88911725Sar4jc@virginia.edu fd = fs2; 89011725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 89111725Sar4jc@virginia.edu } else { 89211725Sar4jc@virginia.edu fd = std::fmax(fs1, fs2); 89311725Sar4jc@virginia.edu } 89411725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 89511725Sar4jc@virginia.edu }}, FloatCmpOp); 89611725Sar4jc@virginia.edu } 89711725Sar4jc@virginia.edu 0x15: decode ROUND_MODE { 89811725Sar4jc@virginia.edu 0x0: fmin_d({{ 89911725Sar4jc@virginia.edu if (issignalingnan(Fs2)) { 90011725Sar4jc@virginia.edu Fd = Fs1; 90111725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 90211725Sar4jc@virginia.edu } else if (issignalingnan(Fs1)) { 90311725Sar4jc@virginia.edu Fd = Fs2; 90411725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 90511725Sar4jc@virginia.edu } else { 90611725Sar4jc@virginia.edu Fd = std::fmin(Fs1, Fs2); 90711725Sar4jc@virginia.edu } 90811725Sar4jc@virginia.edu }}, FloatCmpOp); 90911725Sar4jc@virginia.edu 0x1: fmax_d({{ 91011725Sar4jc@virginia.edu if (issignalingnan(Fs2)) { 91111725Sar4jc@virginia.edu Fd = Fs1; 91211725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 91311725Sar4jc@virginia.edu } else if (issignalingnan(Fs1)) { 91411725Sar4jc@virginia.edu Fd = Fs2; 91511725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 91611725Sar4jc@virginia.edu } else { 91711725Sar4jc@virginia.edu Fd = std::fmax(Fs1, Fs2); 91811725Sar4jc@virginia.edu } 91911725Sar4jc@virginia.edu }}, FloatCmpOp); 92011725Sar4jc@virginia.edu } 92111725Sar4jc@virginia.edu 0x20: fcvt_s_d({{ 92211725Sar4jc@virginia.edu assert(CONV_SGN == 1); 92311725Sar4jc@virginia.edu float fd; 92411725Sar4jc@virginia.edu if (issignalingnan(Fs1)) { 92511725Sar4jc@virginia.edu fd = std::numeric_limits<float>::quiet_NaN(); 92611725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 92711725Sar4jc@virginia.edu } else { 92811725Sar4jc@virginia.edu fd = (float)Fs1; 92911725Sar4jc@virginia.edu } 93011725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 93111725Sar4jc@virginia.edu }}, FloatCvtOp); 93211725Sar4jc@virginia.edu 0x21: fcvt_d_s({{ 93311725Sar4jc@virginia.edu assert(CONV_SGN == 0); 93411725Sar4jc@virginia.edu uint32_t temp; 93511725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 93611725Sar4jc@virginia.edu 93711725Sar4jc@virginia.edu if (issignalingnan(fs1)) { 93811725Sar4jc@virginia.edu Fd = std::numeric_limits<double>::quiet_NaN(); 93911725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 94011725Sar4jc@virginia.edu } else { 94111725Sar4jc@virginia.edu Fd = (double)fs1; 94211725Sar4jc@virginia.edu } 94311725Sar4jc@virginia.edu }}, FloatCvtOp); 94411725Sar4jc@virginia.edu 0x2c: fsqrt_s({{ 94511725Sar4jc@virginia.edu assert(RS2 == 0); 94611725Sar4jc@virginia.edu uint32_t temp; 94711725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 94811725Sar4jc@virginia.edu float fd; 94911725Sar4jc@virginia.edu 95011725Sar4jc@virginia.edu if (issignalingnan(Fs1_sf)) { 95111725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 95211725Sar4jc@virginia.edu } 95311725Sar4jc@virginia.edu fd = std::sqrt(fs1); 95411725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(fd); 95511725Sar4jc@virginia.edu }}, FloatSqrtOp); 95611725Sar4jc@virginia.edu 0x2d: fsqrt_d({{ 95711725Sar4jc@virginia.edu assert(RS2 == 0); 95811725Sar4jc@virginia.edu Fd = std::sqrt(Fs1); 95911725Sar4jc@virginia.edu }}, FloatSqrtOp); 96011725Sar4jc@virginia.edu 0x50: decode ROUND_MODE { 96111725Sar4jc@virginia.edu 0x0: fle_s({{ 96211725Sar4jc@virginia.edu uint32_t temp; 96311725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 96411725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 96511725Sar4jc@virginia.edu 96611725Sar4jc@virginia.edu if (std::isnan(fs1) || std::isnan(fs2)) { 96711725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 96811725Sar4jc@virginia.edu Rd = 0; 96911725Sar4jc@virginia.edu } else { 97011725Sar4jc@virginia.edu Rd = fs1 <= fs2 ? 1 : 0; 97111725Sar4jc@virginia.edu } 97211725Sar4jc@virginia.edu }}, FloatCmpOp); 97311725Sar4jc@virginia.edu 0x1: flt_s({{ 97411725Sar4jc@virginia.edu uint32_t temp; 97511725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 97611725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 97711725Sar4jc@virginia.edu 97811725Sar4jc@virginia.edu if (std::isnan(fs1) || std::isnan(fs2)) { 97911725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 98011725Sar4jc@virginia.edu Rd = 0; 98111725Sar4jc@virginia.edu } else { 98211725Sar4jc@virginia.edu Rd = fs1 < fs2 ? 1 : 0; 98311725Sar4jc@virginia.edu } 98411725Sar4jc@virginia.edu }}, FloatCmpOp); 98511725Sar4jc@virginia.edu 0x2: feq_s({{ 98611725Sar4jc@virginia.edu uint32_t temp; 98711725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 98811725Sar4jc@virginia.edu float fs2 = reinterpret_cast<float&>(temp = Fs2_bits); 98911725Sar4jc@virginia.edu 99011725Sar4jc@virginia.edu if (issignalingnan(fs1) || issignalingnan(fs2)) { 99111725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 99211725Sar4jc@virginia.edu } 99311725Sar4jc@virginia.edu Rd = fs1 == fs2 ? 1 : 0; 99411725Sar4jc@virginia.edu }}, FloatCmpOp); 99511725Sar4jc@virginia.edu } 99611725Sar4jc@virginia.edu 0x51: decode ROUND_MODE { 99711725Sar4jc@virginia.edu 0x0: fle_d({{ 99811725Sar4jc@virginia.edu if (std::isnan(Fs1) || std::isnan(Fs2)) { 99911725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 100011725Sar4jc@virginia.edu Rd = 0; 100111725Sar4jc@virginia.edu } else { 100211725Sar4jc@virginia.edu Rd = Fs1 <= Fs2 ? 1 : 0; 100311725Sar4jc@virginia.edu } 100411725Sar4jc@virginia.edu }}, FloatCmpOp); 100511725Sar4jc@virginia.edu 0x1: flt_d({{ 100611725Sar4jc@virginia.edu if (std::isnan(Fs1) || std::isnan(Fs2)) { 100711725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 100811725Sar4jc@virginia.edu Rd = 0; 100911725Sar4jc@virginia.edu } else { 101011725Sar4jc@virginia.edu Rd = Fs1 < Fs2 ? 1 : 0; 101111725Sar4jc@virginia.edu } 101211725Sar4jc@virginia.edu }}, FloatCmpOp); 101311725Sar4jc@virginia.edu 0x2: feq_d({{ 101411725Sar4jc@virginia.edu if (issignalingnan(Fs1) || issignalingnan(Fs2)) { 101511725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 101611725Sar4jc@virginia.edu } 101711725Sar4jc@virginia.edu Rd = Fs1 == Fs2 ? 1 : 0; 101811725Sar4jc@virginia.edu }}, FloatCmpOp); 101911725Sar4jc@virginia.edu } 102011725Sar4jc@virginia.edu 0x60: decode CONV_SGN { 102111725Sar4jc@virginia.edu 0x0: fcvt_w_s({{ 102211725Sar4jc@virginia.edu uint32_t temp; 102311725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 102411725Sar4jc@virginia.edu 102511725Sar4jc@virginia.edu if (std::isnan(fs1)) { 102611725Sar4jc@virginia.edu Rd_sd = std::numeric_limits<int32_t>::max(); 102711725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 102811725Sar4jc@virginia.edu } else { 102911725Sar4jc@virginia.edu Rd_sd = (int32_t)fs1; 103011725Sar4jc@virginia.edu if (std::fetestexcept(FE_INVALID)) { 103111725Sar4jc@virginia.edu if (std::signbit(fs1)) { 103211725Sar4jc@virginia.edu Rd_sd = std::numeric_limits<int32_t>::min(); 103311725Sar4jc@virginia.edu } else { 103411725Sar4jc@virginia.edu Rd_sd = std::numeric_limits<int32_t>::max(); 103511725Sar4jc@virginia.edu } 103611725Sar4jc@virginia.edu std::feclearexcept(FE_INEXACT); 103711725Sar4jc@virginia.edu } 103811725Sar4jc@virginia.edu } 103911725Sar4jc@virginia.edu }}, FloatCvtOp); 104011725Sar4jc@virginia.edu 0x1: fcvt_wu_s({{ 104111725Sar4jc@virginia.edu uint32_t temp; 104211725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 104311725Sar4jc@virginia.edu 104411725Sar4jc@virginia.edu if (fs1 < 0.0) { 104511725Sar4jc@virginia.edu Rd = 0; 104611725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 104711725Sar4jc@virginia.edu } else { 104811725Sar4jc@virginia.edu Rd = (uint32_t)fs1; 104911725Sar4jc@virginia.edu if (std::fetestexcept(FE_INVALID)) { 105011725Sar4jc@virginia.edu Rd = std::numeric_limits<uint64_t>::max(); 105111725Sar4jc@virginia.edu std::feclearexcept(FE_INEXACT); 105211725Sar4jc@virginia.edu } 105311725Sar4jc@virginia.edu } 105411725Sar4jc@virginia.edu }}, FloatCvtOp); 105511725Sar4jc@virginia.edu 0x2: fcvt_l_s({{ 105611725Sar4jc@virginia.edu uint32_t temp; 105711725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 105811725Sar4jc@virginia.edu 105911725Sar4jc@virginia.edu if (std::isnan(fs1)) { 106011725Sar4jc@virginia.edu Rd_sd = std::numeric_limits<int64_t>::max(); 106111725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 106211725Sar4jc@virginia.edu } else { 106311725Sar4jc@virginia.edu Rd_sd = (int64_t)fs1; 106411725Sar4jc@virginia.edu if (std::fetestexcept(FE_INVALID)) { 106511725Sar4jc@virginia.edu if (std::signbit(fs1)) { 106611725Sar4jc@virginia.edu Rd_sd = std::numeric_limits<int64_t>::min(); 106711725Sar4jc@virginia.edu } else { 106811725Sar4jc@virginia.edu Rd_sd = std::numeric_limits<int64_t>::max(); 106911725Sar4jc@virginia.edu } 107011725Sar4jc@virginia.edu std::feclearexcept(FE_INEXACT); 107111725Sar4jc@virginia.edu } 107211725Sar4jc@virginia.edu } 107311725Sar4jc@virginia.edu }}, FloatCvtOp); 107411725Sar4jc@virginia.edu 0x3: fcvt_lu_s({{ 107511725Sar4jc@virginia.edu uint32_t temp; 107611725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 107711725Sar4jc@virginia.edu 107811725Sar4jc@virginia.edu if (fs1 < 0.0) { 107911725Sar4jc@virginia.edu Rd = 0; 108011725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 108111725Sar4jc@virginia.edu } else { 108211725Sar4jc@virginia.edu Rd = (uint64_t)fs1; 108311725Sar4jc@virginia.edu if (std::fetestexcept(FE_INVALID)) { 108411725Sar4jc@virginia.edu Rd = std::numeric_limits<uint64_t>::max(); 108511725Sar4jc@virginia.edu std::feclearexcept(FE_INEXACT); 108611725Sar4jc@virginia.edu } 108711725Sar4jc@virginia.edu } 108811725Sar4jc@virginia.edu }}, FloatCvtOp); 108911725Sar4jc@virginia.edu } 109011725Sar4jc@virginia.edu 0x61: decode CONV_SGN { 109111725Sar4jc@virginia.edu 0x0: fcvt_w_d({{ 109211725Sar4jc@virginia.edu Rd_sd = (int32_t)Fs1; 109311725Sar4jc@virginia.edu if (std::fetestexcept(FE_INVALID)) { 109411725Sar4jc@virginia.edu if (Fs1 < 0.0) { 109511725Sar4jc@virginia.edu Rd_sd = std::numeric_limits<int32_t>::min(); 109611725Sar4jc@virginia.edu } else { 109711725Sar4jc@virginia.edu Rd_sd = std::numeric_limits<int32_t>::max(); 109811725Sar4jc@virginia.edu } 109911725Sar4jc@virginia.edu std::feclearexcept(FE_INEXACT); 110011725Sar4jc@virginia.edu } 110111725Sar4jc@virginia.edu }}, FloatCvtOp); 110211725Sar4jc@virginia.edu 0x1: fcvt_wu_d({{ 110311725Sar4jc@virginia.edu if (Fs1 < 0.0) { 110411725Sar4jc@virginia.edu Rd = 0; 110511725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 110611725Sar4jc@virginia.edu } else { 110711725Sar4jc@virginia.edu Rd = (uint32_t)Fs1; 110811725Sar4jc@virginia.edu if (std::fetestexcept(FE_INVALID)) { 110911725Sar4jc@virginia.edu Rd = std::numeric_limits<uint64_t>::max(); 111011725Sar4jc@virginia.edu std::feclearexcept(FE_INEXACT); 111111725Sar4jc@virginia.edu } 111211725Sar4jc@virginia.edu } 111311725Sar4jc@virginia.edu }}, FloatCvtOp); 111411725Sar4jc@virginia.edu 0x2: fcvt_l_d({{ 111511725Sar4jc@virginia.edu Rd_sd = Fs1; 111611725Sar4jc@virginia.edu if (std::fetestexcept(FE_INVALID)) { 111711725Sar4jc@virginia.edu if (Fs1 < 0.0) { 111811725Sar4jc@virginia.edu Rd_sd = std::numeric_limits<int64_t>::min(); 111911725Sar4jc@virginia.edu } else { 112011725Sar4jc@virginia.edu Rd_sd = std::numeric_limits<int64_t>::max(); 112111725Sar4jc@virginia.edu } 112211725Sar4jc@virginia.edu std::feclearexcept(FE_INEXACT); 112311725Sar4jc@virginia.edu } 112411725Sar4jc@virginia.edu }}, FloatCvtOp); 112511725Sar4jc@virginia.edu 0x3: fcvt_lu_d({{ 112611725Sar4jc@virginia.edu if (Fs1 < 0.0) { 112711725Sar4jc@virginia.edu Rd = 0; 112811725Sar4jc@virginia.edu FFLAGS |= FloatInvalid; 112911725Sar4jc@virginia.edu } else { 113011725Sar4jc@virginia.edu Rd = (uint64_t)Fs1; 113111725Sar4jc@virginia.edu if (std::fetestexcept(FE_INVALID)) { 113211725Sar4jc@virginia.edu Rd = std::numeric_limits<uint64_t>::max(); 113311725Sar4jc@virginia.edu std::feclearexcept(FE_INEXACT); 113411725Sar4jc@virginia.edu } 113511725Sar4jc@virginia.edu } 113611725Sar4jc@virginia.edu }}, FloatCvtOp); 113711725Sar4jc@virginia.edu } 113811725Sar4jc@virginia.edu 0x68: decode CONV_SGN { 113911725Sar4jc@virginia.edu 0x0: fcvt_s_w({{ 114011725Sar4jc@virginia.edu float temp = (float)Rs1_sw; 114111725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp); 114211725Sar4jc@virginia.edu }}, FloatCvtOp); 114311725Sar4jc@virginia.edu 0x1: fcvt_s_wu({{ 114411725Sar4jc@virginia.edu float temp = (float)Rs1_uw; 114511725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp); 114611725Sar4jc@virginia.edu }}, FloatCvtOp); 114711725Sar4jc@virginia.edu 0x2: fcvt_s_l({{ 114811725Sar4jc@virginia.edu float temp = (float)Rs1_sd; 114911725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp); 115011725Sar4jc@virginia.edu }}, FloatCvtOp); 115111725Sar4jc@virginia.edu 0x3: fcvt_s_lu({{ 115211725Sar4jc@virginia.edu float temp = (float)Rs1; 115311725Sar4jc@virginia.edu Fd_bits = (uint64_t)reinterpret_cast<uint32_t&>(temp); 115411725Sar4jc@virginia.edu }}, FloatCvtOp); 115511725Sar4jc@virginia.edu } 115611725Sar4jc@virginia.edu 0x69: decode CONV_SGN { 115711725Sar4jc@virginia.edu 0x0: fcvt_d_w({{ 115811725Sar4jc@virginia.edu Fd = (double)Rs1_sw; 115911725Sar4jc@virginia.edu }}, FloatCvtOp); 116011725Sar4jc@virginia.edu 0x1: fcvt_d_wu({{ 116111725Sar4jc@virginia.edu Fd = (double)Rs1_uw; 116211725Sar4jc@virginia.edu }}, FloatCvtOp); 116311725Sar4jc@virginia.edu 0x2: fcvt_d_l({{ 116411725Sar4jc@virginia.edu Fd = (double)Rs1_sd; 116511725Sar4jc@virginia.edu }}, FloatCvtOp); 116611725Sar4jc@virginia.edu 0x3: fcvt_d_lu({{ 116711725Sar4jc@virginia.edu Fd = (double)Rs1; 116811725Sar4jc@virginia.edu }}, FloatCvtOp); 116911725Sar4jc@virginia.edu } 117011725Sar4jc@virginia.edu 0x70: decode ROUND_MODE { 117111725Sar4jc@virginia.edu 0x0: fmv_x_s({{ 117211725Sar4jc@virginia.edu Rd = (uint32_t)Fs1_bits; 117311725Sar4jc@virginia.edu if ((Rd&0x80000000) != 0) { 117411725Sar4jc@virginia.edu Rd |= (0xFFFFFFFFULL << 32); 117511725Sar4jc@virginia.edu } 117611725Sar4jc@virginia.edu }}, FloatCvtOp); 117711725Sar4jc@virginia.edu 0x1: fclass_s({{ 117811725Sar4jc@virginia.edu uint32_t temp; 117911725Sar4jc@virginia.edu float fs1 = reinterpret_cast<float&>(temp = Fs1_bits); 118011725Sar4jc@virginia.edu switch (std::fpclassify(fs1)) { 118111725Sar4jc@virginia.edu case FP_INFINITE: 118211725Sar4jc@virginia.edu if (std::signbit(fs1)) { 118311725Sar4jc@virginia.edu Rd = 1 << 0; 118411725Sar4jc@virginia.edu } else { 118511725Sar4jc@virginia.edu Rd = 1 << 7; 118611725Sar4jc@virginia.edu } 118711725Sar4jc@virginia.edu break; 118811725Sar4jc@virginia.edu case FP_NAN: 118911725Sar4jc@virginia.edu if (issignalingnan(fs1)) { 119011725Sar4jc@virginia.edu Rd = 1 << 8; 119111725Sar4jc@virginia.edu } else { 119211725Sar4jc@virginia.edu Rd = 1 << 9; 119311725Sar4jc@virginia.edu } 119411725Sar4jc@virginia.edu break; 119511725Sar4jc@virginia.edu case FP_ZERO: 119611725Sar4jc@virginia.edu if (std::signbit(fs1)) { 119711725Sar4jc@virginia.edu Rd = 1 << 3; 119811725Sar4jc@virginia.edu } else { 119911725Sar4jc@virginia.edu Rd = 1 << 4; 120011725Sar4jc@virginia.edu } 120111725Sar4jc@virginia.edu break; 120211725Sar4jc@virginia.edu case FP_SUBNORMAL: 120311725Sar4jc@virginia.edu if (std::signbit(fs1)) { 120411725Sar4jc@virginia.edu Rd = 1 << 2; 120511725Sar4jc@virginia.edu } else { 120611725Sar4jc@virginia.edu Rd = 1 << 5; 120711725Sar4jc@virginia.edu } 120811725Sar4jc@virginia.edu break; 120911725Sar4jc@virginia.edu case FP_NORMAL: 121011725Sar4jc@virginia.edu if (std::signbit(fs1)) { 121111725Sar4jc@virginia.edu Rd = 1 << 1; 121211725Sar4jc@virginia.edu } else { 121311725Sar4jc@virginia.edu Rd = 1 << 6; 121411725Sar4jc@virginia.edu } 121511725Sar4jc@virginia.edu break; 121611725Sar4jc@virginia.edu default: 121711725Sar4jc@virginia.edu panic("Unknown classification for operand."); 121811725Sar4jc@virginia.edu break; 121911725Sar4jc@virginia.edu } 122011725Sar4jc@virginia.edu }}); 122111725Sar4jc@virginia.edu } 122211725Sar4jc@virginia.edu 0x71: decode ROUND_MODE { 122311725Sar4jc@virginia.edu 0x0: fmv_x_d({{ 122411725Sar4jc@virginia.edu Rd = Fs1_bits; 122511725Sar4jc@virginia.edu }}, FloatCvtOp); 122611725Sar4jc@virginia.edu 0x1: fclass_d({{ 122711725Sar4jc@virginia.edu switch (std::fpclassify(Fs1)) { 122811725Sar4jc@virginia.edu case FP_INFINITE: 122911725Sar4jc@virginia.edu if (std::signbit(Fs1)) { 123011725Sar4jc@virginia.edu Rd = 1 << 0; 123111725Sar4jc@virginia.edu } else { 123211725Sar4jc@virginia.edu Rd = 1 << 7; 123311725Sar4jc@virginia.edu } 123411725Sar4jc@virginia.edu break; 123511725Sar4jc@virginia.edu case FP_NAN: 123611725Sar4jc@virginia.edu if (issignalingnan(Fs1)) { 123711725Sar4jc@virginia.edu Rd = 1 << 8; 123811725Sar4jc@virginia.edu } else { 123911725Sar4jc@virginia.edu Rd = 1 << 9; 124011725Sar4jc@virginia.edu } 124111725Sar4jc@virginia.edu break; 124211725Sar4jc@virginia.edu case FP_ZERO: 124311725Sar4jc@virginia.edu if (std::signbit(Fs1)) { 124411725Sar4jc@virginia.edu Rd = 1 << 3; 124511725Sar4jc@virginia.edu } else { 124611725Sar4jc@virginia.edu Rd = 1 << 4; 124711725Sar4jc@virginia.edu } 124811725Sar4jc@virginia.edu break; 124911725Sar4jc@virginia.edu case FP_SUBNORMAL: 125011725Sar4jc@virginia.edu if (std::signbit(Fs1)) { 125111725Sar4jc@virginia.edu Rd = 1 << 2; 125211725Sar4jc@virginia.edu } else { 125311725Sar4jc@virginia.edu Rd = 1 << 5; 125411725Sar4jc@virginia.edu } 125511725Sar4jc@virginia.edu break; 125611725Sar4jc@virginia.edu case FP_NORMAL: 125711725Sar4jc@virginia.edu if (std::signbit(Fs1)) { 125811725Sar4jc@virginia.edu Rd = 1 << 1; 125911725Sar4jc@virginia.edu } else { 126011725Sar4jc@virginia.edu Rd = 1 << 6; 126111725Sar4jc@virginia.edu } 126211725Sar4jc@virginia.edu break; 126311725Sar4jc@virginia.edu default: 126411725Sar4jc@virginia.edu panic("Unknown classification for operand."); 126511725Sar4jc@virginia.edu break; 126611725Sar4jc@virginia.edu } 126711725Sar4jc@virginia.edu }}); 126811725Sar4jc@virginia.edu } 126911725Sar4jc@virginia.edu 0x78: fmv_s_x({{ 127011725Sar4jc@virginia.edu Fd_bits = (uint64_t)Rs1_uw; 127111725Sar4jc@virginia.edu }}, FloatCvtOp); 127211725Sar4jc@virginia.edu 0x79: fmv_d_x({{ 127311725Sar4jc@virginia.edu Fd_bits = Rs1; 127411725Sar4jc@virginia.edu }}, FloatCvtOp); 127511725Sar4jc@virginia.edu } 127611725Sar4jc@virginia.edu } 127711723Sar4jc@virginia.edu 0x63: decode FUNCT3 { 127811723Sar4jc@virginia.edu format SBOp { 127911723Sar4jc@virginia.edu 0x0: beq({{ 128011723Sar4jc@virginia.edu if (Rs1 == Rs2) { 128111723Sar4jc@virginia.edu NPC = PC + imm; 128211723Sar4jc@virginia.edu } else { 128311723Sar4jc@virginia.edu NPC = NPC; 128411723Sar4jc@virginia.edu } 128511723Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 128611723Sar4jc@virginia.edu 0x1: bne({{ 128711723Sar4jc@virginia.edu if (Rs1 != Rs2) { 128811723Sar4jc@virginia.edu NPC = PC + imm; 128911723Sar4jc@virginia.edu } else { 129011723Sar4jc@virginia.edu NPC = NPC; 129111723Sar4jc@virginia.edu } 129211723Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 129311723Sar4jc@virginia.edu 0x4: blt({{ 129411723Sar4jc@virginia.edu if (Rs1_sd < Rs2_sd) { 129511723Sar4jc@virginia.edu NPC = PC + imm; 129611723Sar4jc@virginia.edu } else { 129711723Sar4jc@virginia.edu NPC = NPC; 129811723Sar4jc@virginia.edu } 129911723Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 130011723Sar4jc@virginia.edu 0x5: bge({{ 130111723Sar4jc@virginia.edu if (Rs1_sd >= Rs2_sd) { 130211723Sar4jc@virginia.edu NPC = PC + imm; 130311723Sar4jc@virginia.edu } else { 130411723Sar4jc@virginia.edu NPC = NPC; 130511723Sar4jc@virginia.edu } 130611723Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 130711723Sar4jc@virginia.edu 0x6: bltu({{ 130811723Sar4jc@virginia.edu if (Rs1 < Rs2) { 130911723Sar4jc@virginia.edu NPC = PC + imm; 131011723Sar4jc@virginia.edu } else { 131111723Sar4jc@virginia.edu NPC = NPC; 131211723Sar4jc@virginia.edu } 131311723Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 131411723Sar4jc@virginia.edu 0x7: bgeu({{ 131511723Sar4jc@virginia.edu if (Rs1 >= Rs2) { 131611723Sar4jc@virginia.edu NPC = PC + imm; 131711723Sar4jc@virginia.edu } else { 131811723Sar4jc@virginia.edu NPC = NPC; 131911723Sar4jc@virginia.edu } 132011723Sar4jc@virginia.edu }}, IsDirectControl, IsCondControl); 132111723Sar4jc@virginia.edu } 132211723Sar4jc@virginia.edu } 132311723Sar4jc@virginia.edu 132411723Sar4jc@virginia.edu 0x67: decode FUNCT3 { 132511723Sar4jc@virginia.edu 0x0: Jump::jalr({{ 132611723Sar4jc@virginia.edu Rd = NPC; 132711723Sar4jc@virginia.edu NPC = (imm + Rs1) & (~0x1); 132811723Sar4jc@virginia.edu }}, IsIndirectControl, IsUncondControl, IsCall); 132911723Sar4jc@virginia.edu } 133011723Sar4jc@virginia.edu 133111723Sar4jc@virginia.edu 0x6f: UJOp::jal({{ 133211723Sar4jc@virginia.edu Rd = NPC; 133311723Sar4jc@virginia.edu NPC = PC + imm; 133411723Sar4jc@virginia.edu }}, IsDirectControl, IsUncondControl, IsCall); 133511723Sar4jc@virginia.edu 133611723Sar4jc@virginia.edu 0x73: decode FUNCT3 { 133711723Sar4jc@virginia.edu format IOp { 133811723Sar4jc@virginia.edu 0x0: decode FUNCT12 { 133911723Sar4jc@virginia.edu 0x0: ecall({{ 134011723Sar4jc@virginia.edu fault = std::make_shared<SyscallFault>(); 134111723Sar4jc@virginia.edu }}, IsSerializeAfter, IsNonSpeculative, IsSyscall, No_OpClass); 134211723Sar4jc@virginia.edu 0x1: ebreak({{ 134311723Sar4jc@virginia.edu fault = std::make_shared<BreakpointFault>(); 134411723Sar4jc@virginia.edu }}, IsSerializeAfter, IsNonSpeculative, No_OpClass); 134511723Sar4jc@virginia.edu 0x100: eret({{ 134611723Sar4jc@virginia.edu fault = std::make_shared<UnimplementedFault>("eret"); 134711723Sar4jc@virginia.edu }}, No_OpClass); 134811723Sar4jc@virginia.edu } 134911723Sar4jc@virginia.edu 0x1: csrrw({{ 135011723Sar4jc@virginia.edu Rd = xc->readMiscReg(FUNCT12); 135111723Sar4jc@virginia.edu xc->setMiscReg(FUNCT12, Rs1); 135211723Sar4jc@virginia.edu }}, IsNonSpeculative, No_OpClass); 135311723Sar4jc@virginia.edu 0x2: csrrs({{ 135411723Sar4jc@virginia.edu Rd = xc->readMiscReg(FUNCT12); 135511723Sar4jc@virginia.edu if (Rs1 != 0) { 135611723Sar4jc@virginia.edu xc->setMiscReg(FUNCT12, Rd | Rs1); 135711723Sar4jc@virginia.edu } 135811723Sar4jc@virginia.edu }}, IsNonSpeculative, No_OpClass); 135911723Sar4jc@virginia.edu 0x3: csrrc({{ 136011723Sar4jc@virginia.edu Rd = xc->readMiscReg(FUNCT12); 136111723Sar4jc@virginia.edu if (Rs1 != 0) { 136211723Sar4jc@virginia.edu xc->setMiscReg(FUNCT12, Rd & ~Rs1); 136311723Sar4jc@virginia.edu } 136411723Sar4jc@virginia.edu }}, IsNonSpeculative, No_OpClass); 136511723Sar4jc@virginia.edu 0x5: csrrwi({{ 136611723Sar4jc@virginia.edu Rd = xc->readMiscReg(FUNCT12); 136711723Sar4jc@virginia.edu xc->setMiscReg(FUNCT12, ZIMM); 136811723Sar4jc@virginia.edu }}, IsNonSpeculative, No_OpClass); 136911723Sar4jc@virginia.edu 0x6: csrrsi({{ 137011723Sar4jc@virginia.edu Rd = xc->readMiscReg(FUNCT12); 137111723Sar4jc@virginia.edu if (ZIMM != 0) { 137211723Sar4jc@virginia.edu xc->setMiscReg(FUNCT12, Rd | ZIMM); 137311723Sar4jc@virginia.edu } 137411723Sar4jc@virginia.edu }}, IsNonSpeculative, No_OpClass); 137511723Sar4jc@virginia.edu 0x7: csrrci({{ 137611723Sar4jc@virginia.edu Rd = xc->readMiscReg(FUNCT12); 137711723Sar4jc@virginia.edu if (ZIMM != 0) { 137811723Sar4jc@virginia.edu xc->setMiscReg(FUNCT12, Rd & ~ZIMM); 137911723Sar4jc@virginia.edu } 138011723Sar4jc@virginia.edu }}, IsNonSpeculative, No_OpClass); 138111723Sar4jc@virginia.edu } 138211723Sar4jc@virginia.edu } 138311723Sar4jc@virginia.edu} 1384