faults.hh revision 13547
18853Sandreas.hansson@arm.com/* 212532Sandreas.sandberg@arm.com * Copyright (c) 2016 RISC-V Foundation 38853Sandreas.hansson@arm.com * Copyright (c) 2016 The University of Virginia 48853Sandreas.hansson@arm.com * Copyright (c) 2018 TU Dresden 58853Sandreas.hansson@arm.com * All rights reserved. 68853Sandreas.hansson@arm.com * 78853Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 88853Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 98853Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 108853Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 118853Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 128853Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 138853Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 148853Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 158853Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 168853Sandreas.hansson@arm.com * this software without specific prior written permission. 178853Sandreas.hansson@arm.com * 188853Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 198853Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 208853Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 218853Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 228853Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 238853Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 248853Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 258853Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 268853Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 278853Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 288853Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 298853Sandreas.hansson@arm.com * 308853Sandreas.hansson@arm.com * Authors: Alec Roelke 318853Sandreas.hansson@arm.com * Robert Scheffel 328853Sandreas.hansson@arm.com */ 338853Sandreas.hansson@arm.com 348853Sandreas.hansson@arm.com#ifndef __ARCH_RISCV_FAULTS_HH__ 358853Sandreas.hansson@arm.com#define __ARCH_RISCV_FAULTS_HH__ 368853Sandreas.hansson@arm.com 378853Sandreas.hansson@arm.com#include <map> 388853Sandreas.hansson@arm.com#include <string> 398853Sandreas.hansson@arm.com 4011793Sbrandon.potter@amd.com#include "arch/riscv/isa.hh" 4111793Sbrandon.potter@amd.com#include "arch/riscv/registers.hh" 428853Sandreas.hansson@arm.com#include "cpu/thread_context.hh" 438853Sandreas.hansson@arm.com#include "sim/faults.hh" 448853Sandreas.hansson@arm.com 4512532Sandreas.sandberg@arm.comnamespace RiscvISA 4614009Sgabeblack@google.com{ 478853Sandreas.hansson@arm.com 4810564Sandreas.hansson@arm.comenum FloatException : MiscReg { 4910564Sandreas.hansson@arm.com FloatInexact = 0x1, 5012749Sgiacomo.travaglini@arm.com FloatUnderflow = 0x2, 5112749Sgiacomo.travaglini@arm.com FloatOverflow = 0x4, 5212749Sgiacomo.travaglini@arm.com FloatDivZero = 0x8, 5312749Sgiacomo.travaglini@arm.com FloatInvalid = 0x10 5412749Sgiacomo.travaglini@arm.com}; 5514009Sgabeblack@google.com 568853Sandreas.hansson@arm.comenum ExceptionCode : MiscReg { 5714009Sgabeblack@google.com INST_ADDR_MISALIGNED = 0, 588853Sandreas.hansson@arm.com INST_ACCESS = 1, 598853Sandreas.hansson@arm.com INST_ILLEGAL = 2, 608853Sandreas.hansson@arm.com BREAKPOINT = 3, 618853Sandreas.hansson@arm.com LOAD_ADDR_MISALIGNED = 4, 6212532Sandreas.sandberg@arm.com LOAD_ACCESS = 5, 6314009Sgabeblack@google.com STORE_ADDR_MISALIGNED = 6, 6410564Sandreas.hansson@arm.com AMO_ADDR_MISALIGNED = 6, 6510564Sandreas.hansson@arm.com STORE_ACCESS = 7, 6610564Sandreas.hansson@arm.com AMO_ACCESS = 7, 6712749Sgiacomo.travaglini@arm.com ECALL_USER = 8, 6812749Sgiacomo.travaglini@arm.com ECALL_SUPER = 9, 6912749Sgiacomo.travaglini@arm.com ECALL_MACHINE = 11, 7012749Sgiacomo.travaglini@arm.com INST_PAGE = 12, 7112749Sgiacomo.travaglini@arm.com LOAD_PAGE = 13, 7214009Sgabeblack@google.com STORE_PAGE = 15, 7310564Sandreas.hansson@arm.com AMO_PAGE = 15 7414009Sgabeblack@google.com}; 7510564Sandreas.hansson@arm.com 7610564Sandreas.hansson@arm.comclass RiscvFault : public FaultBase 7710564Sandreas.hansson@arm.com{ 7810564Sandreas.hansson@arm.com protected: 7912532Sandreas.sandberg@arm.com const FaultName _name; 8012532Sandreas.sandberg@arm.com const bool _interrupt; 818853Sandreas.hansson@arm.com ExceptionCode _code; 828853Sandreas.hansson@arm.com 838853Sandreas.hansson@arm.com RiscvFault(FaultName n, bool i, ExceptionCode c) 848853Sandreas.hansson@arm.com : _name(n), _interrupt(i), _code(c) 858853Sandreas.hansson@arm.com {} 8612532Sandreas.sandberg@arm.com 878853Sandreas.hansson@arm.com FaultName name() const override { return _name; } 888853Sandreas.hansson@arm.com bool isInterrupt() const { return _interrupt; } 898853Sandreas.hansson@arm.com ExceptionCode exception() const { return _code; } 9014008Sgabeblack@google.com virtual MiscReg trap_value() const { return 0; } 9114008Sgabeblack@google.com 9214008Sgabeblack@google.com virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst); 9314008Sgabeblack@google.com void invoke(ThreadContext *tc, const StaticInstPtr &inst) override; 9414008Sgabeblack@google.com}; 9514009Sgabeblack@google.com 9614008Sgabeblack@google.comclass Reset : public FaultBase 9714008Sgabeblack@google.com{ 9814008Sgabeblack@google.com private: 9914008Sgabeblack@google.com const FaultName _name; 10014008Sgabeblack@google.com 10114008Sgabeblack@google.com public: 10214008Sgabeblack@google.com Reset() : _name("reset") {} 10314008Sgabeblack@google.com FaultName name() const override { return _name; } 10414008Sgabeblack@google.com 10514008Sgabeblack@google.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 10614008Sgabeblack@google.com StaticInst::nullStaticInstPtr) override; 10714008Sgabeblack@google.com}; 10814008Sgabeblack@google.com 10914008Sgabeblack@google.comclass InstFault : public RiscvFault 11014008Sgabeblack@google.com{ 11114008Sgabeblack@google.com protected: 11214008Sgabeblack@google.com const ExtMachInst _inst; 113 114 public: 115 InstFault(FaultName n, const ExtMachInst inst) 116 : RiscvFault(n, false, INST_ILLEGAL), _inst(inst) 117 {} 118 119 MiscReg trap_value() const override { return _inst; } 120}; 121 122class UnknownInstFault : public InstFault 123{ 124 public: 125 UnknownInstFault(const ExtMachInst inst) 126 : InstFault("Unknown instruction", inst) 127 {} 128 129 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 130}; 131 132class IllegalInstFault : public InstFault 133{ 134 private: 135 const std::string reason; 136 137 public: 138 IllegalInstFault(std::string r, const ExtMachInst inst) 139 : InstFault("Illegal instruction", inst) 140 {} 141 142 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 143}; 144 145class UnimplementedFault : public InstFault 146{ 147 private: 148 const std::string instName; 149 150 public: 151 UnimplementedFault(std::string name, const ExtMachInst inst) 152 : InstFault("Unimplemented instruction", inst), 153 instName(name) 154 {} 155 156 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 157}; 158 159class IllegalFrmFault: public InstFault 160{ 161 private: 162 const uint8_t frm; 163 164 public: 165 IllegalFrmFault(uint8_t r, const ExtMachInst inst) 166 : InstFault("Illegal floating-point rounding mode", inst), 167 frm(r) 168 {} 169 170 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 171}; 172 173class AddressFault : public RiscvFault 174{ 175 private: 176 const Addr _addr; 177 178 public: 179 AddressFault(const Addr addr, ExceptionCode code) 180 : RiscvFault("Address", false, code), _addr(addr) 181 {} 182 183 MiscReg trap_value() const override { return _addr; } 184}; 185 186class BreakpointFault : public RiscvFault 187{ 188 private: 189 const PCState pcState; 190 191 public: 192 BreakpointFault(const PCState &pc) 193 : RiscvFault("Breakpoint", false, BREAKPOINT), pcState(pc) 194 {} 195 196 MiscReg trap_value() const override { return pcState.pc(); } 197 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 198}; 199 200class SyscallFault : public RiscvFault 201{ 202 public: 203 SyscallFault(PrivilegeMode prv) 204 : RiscvFault("System call", false, ECALL_USER) 205 { 206 switch (prv) { 207 case PRV_U: 208 _code = ECALL_USER; 209 break; 210 case PRV_S: 211 _code = ECALL_SUPER; 212 break; 213 case PRV_M: 214 _code = ECALL_MACHINE; 215 break; 216 default: 217 panic("Unknown privilege mode %d.", prv); 218 break; 219 } 220 } 221 222 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 223}; 224 225} // namespace RiscvISA 226 227#endif // __ARCH_RISCV_FAULTS_HH__ 228