faults.hh revision 13547
16019SN/A/* 214238Sciro.santilli@arm.com * Copyright (c) 2016 RISC-V Foundation 37649Sminkyu.jeong@arm.com * Copyright (c) 2016 The University of Virginia 47649Sminkyu.jeong@arm.com * Copyright (c) 2018 TU Dresden 57649Sminkyu.jeong@arm.com * All rights reserved. 67649Sminkyu.jeong@arm.com * 77649Sminkyu.jeong@arm.com * Redistribution and use in source and binary forms, with or without 87649Sminkyu.jeong@arm.com * modification, are permitted provided that the following conditions are 97649Sminkyu.jeong@arm.com * met: redistributions of source code must retain the above copyright 107649Sminkyu.jeong@arm.com * notice, this list of conditions and the following disclaimer; 117649Sminkyu.jeong@arm.com * redistributions in binary form must reproduce the above copyright 127649Sminkyu.jeong@arm.com * notice, this list of conditions and the following disclaimer in the 137649Sminkyu.jeong@arm.com * documentation and/or other materials provided with the distribution; 146019SN/A * neither the name of the copyright holders nor the names of its 156019SN/A * contributors may be used to endorse or promote products derived from 166019SN/A * this software without specific prior written permission. 176019SN/A * 186019SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 196019SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 206019SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 216019SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 226019SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 236019SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 246019SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 256019SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 266019SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 276019SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 286019SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 296019SN/A * 306019SN/A * Authors: Alec Roelke 316019SN/A * Robert Scheffel 326019SN/A */ 336019SN/A 346019SN/A#ifndef __ARCH_RISCV_FAULTS_HH__ 356019SN/A#define __ARCH_RISCV_FAULTS_HH__ 366019SN/A 376019SN/A#include <map> 386019SN/A#include <string> 396019SN/A 406019SN/A#include "arch/riscv/isa.hh" 416019SN/A#include "arch/riscv/registers.hh" 426019SN/A#include "cpu/thread_context.hh" 436329Sgblack@eecs.umich.edu#include "sim/faults.hh" 446329Sgblack@eecs.umich.edu 456019SN/Anamespace RiscvISA 4612109SRekai.GonzalezAlberquilla@arm.com{ 478961Sgblack@eecs.umich.edu 488229Snate@binkert.orgenum FloatException : MiscReg { 496329Sgblack@eecs.umich.edu FloatInexact = 0x1, 5013610Sgiacomo.gabrielli@arm.com FloatUnderflow = 0x2, 5113610Sgiacomo.gabrielli@arm.com FloatOverflow = 0x4, 5212109SRekai.GonzalezAlberquilla@arm.com FloatDivZero = 0x8, 536328SN/A FloatInvalid = 0x10 546329Sgblack@eecs.umich.edu}; 556328SN/A 567848SAli.Saidi@ARM.comenum ExceptionCode : MiscReg { 577848SAli.Saidi@ARM.com INST_ADDR_MISALIGNED = 0, 587848SAli.Saidi@ARM.com INST_ACCESS = 1, 597848SAli.Saidi@ARM.com INST_ILLEGAL = 2, 607848SAli.Saidi@ARM.com BREAKPOINT = 3, 616329Sgblack@eecs.umich.edu LOAD_ADDR_MISALIGNED = 4, 629046SAli.Saidi@ARM.com LOAD_ACCESS = 5, 636328SN/A STORE_ADDR_MISALIGNED = 6, 6414238Sciro.santilli@arm.com AMO_ADDR_MISALIGNED = 6, 6514238Sciro.santilli@arm.com STORE_ACCESS = 7, 6614238Sciro.santilli@arm.com AMO_ACCESS = 7, 6712109SRekai.GonzalezAlberquilla@arm.com ECALL_USER = 8, 6813759Sgiacomo.gabrielli@arm.com ECALL_SUPER = 9, 6913759Sgiacomo.gabrielli@arm.com ECALL_MACHINE = 11, 7012109SRekai.GonzalezAlberquilla@arm.com INST_PAGE = 12, 7112109SRekai.GonzalezAlberquilla@arm.com LOAD_PAGE = 13, 7212109SRekai.GonzalezAlberquilla@arm.com STORE_PAGE = 15, 7312109SRekai.GonzalezAlberquilla@arm.com AMO_PAGE = 15 7412109SRekai.GonzalezAlberquilla@arm.com}; 7513759Sgiacomo.gabrielli@arm.com 7613759Sgiacomo.gabrielli@arm.comclass RiscvFault : public FaultBase 7713759Sgiacomo.gabrielli@arm.com{ 7813759Sgiacomo.gabrielli@arm.com protected: 7913759Sgiacomo.gabrielli@arm.com const FaultName _name; 8013610Sgiacomo.gabrielli@arm.com const bool _interrupt; 816329Sgblack@eecs.umich.edu ExceptionCode _code; 826717Sgblack@eecs.umich.edu 837177Sgblack@eecs.umich.edu RiscvFault(FaultName n, bool i, ExceptionCode c) 8410037SARM gem5 Developers : _name(n), _interrupt(i), _code(c) 8510037SARM gem5 Developers {} 8610037SARM gem5 Developers 8712109SRekai.GonzalezAlberquilla@arm.com FaultName name() const override { return _name; } 8812109SRekai.GonzalezAlberquilla@arm.com bool isInterrupt() const { return _interrupt; } 8912109SRekai.GonzalezAlberquilla@arm.com ExceptionCode exception() const { return _code; } 906328SN/A virtual MiscReg trap_value() const { return 0; } 9114106Sjavier.setoain@arm.com 926717Sgblack@eecs.umich.edu virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst); 9310037SARM gem5 Developers void invoke(ThreadContext *tc, const StaticInstPtr &inst) override; 9414106Sjavier.setoain@arm.com}; 9514028Sgiacomo.gabrielli@arm.com 9614091Sgabor.dozsa@arm.comclass Reset : public FaultBase 9713759Sgiacomo.gabrielli@arm.com{ 9814091Sgabor.dozsa@arm.com private: 9910338SCurtis.Dunham@arm.com const FaultName _name; 1006329Sgblack@eecs.umich.edu 10114106Sjavier.setoain@arm.com public: 10214106Sjavier.setoain@arm.com Reset() : _name("reset") {} 10314106Sjavier.setoain@arm.com FaultName name() const override { return _name; } 10414106Sjavier.setoain@arm.com 1056328SN/A void invoke(ThreadContext *tc, const StaticInstPtr &inst = 10610338SCurtis.Dunham@arm.com StaticInst::nullStaticInstPtr) override; 10710338SCurtis.Dunham@arm.com}; 10813610Sgiacomo.gabrielli@arm.com 10913610Sgiacomo.gabrielli@arm.comclass InstFault : public RiscvFault 1106328SN/A{ 1116329Sgblack@eecs.umich.edu protected: 1126329Sgblack@eecs.umich.edu const ExtMachInst _inst; 1136329Sgblack@eecs.umich.edu 1146329Sgblack@eecs.umich.edu public: 1157650SAli.Saidi@ARM.com InstFault(FaultName n, const ExtMachInst inst) 11610037SARM gem5 Developers : RiscvFault(n, false, INST_ILLEGAL), _inst(inst) 1176329Sgblack@eecs.umich.edu {} 1186329Sgblack@eecs.umich.edu 1196329Sgblack@eecs.umich.edu MiscReg trap_value() const override { return _inst; } 1206329Sgblack@eecs.umich.edu}; 1216329Sgblack@eecs.umich.edu 1226717Sgblack@eecs.umich.educlass UnknownInstFault : public InstFault 1236717Sgblack@eecs.umich.edu{ 1246717Sgblack@eecs.umich.edu public: 1256328SN/A UnknownInstFault(const ExtMachInst inst) 1266717Sgblack@eecs.umich.edu : InstFault("Unknown instruction", inst) 1276328SN/A {} 1286329Sgblack@eecs.umich.edu 1296329Sgblack@eecs.umich.edu void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 1306329Sgblack@eecs.umich.edu}; 1316328SN/A 1326328SN/Aclass IllegalInstFault : public InstFault 1336019SN/A{ 1346019SN/A private: 135 const std::string reason; 136 137 public: 138 IllegalInstFault(std::string r, const ExtMachInst inst) 139 : InstFault("Illegal instruction", inst) 140 {} 141 142 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 143}; 144 145class UnimplementedFault : public InstFault 146{ 147 private: 148 const std::string instName; 149 150 public: 151 UnimplementedFault(std::string name, const ExtMachInst inst) 152 : InstFault("Unimplemented instruction", inst), 153 instName(name) 154 {} 155 156 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 157}; 158 159class IllegalFrmFault: public InstFault 160{ 161 private: 162 const uint8_t frm; 163 164 public: 165 IllegalFrmFault(uint8_t r, const ExtMachInst inst) 166 : InstFault("Illegal floating-point rounding mode", inst), 167 frm(r) 168 {} 169 170 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 171}; 172 173class AddressFault : public RiscvFault 174{ 175 private: 176 const Addr _addr; 177 178 public: 179 AddressFault(const Addr addr, ExceptionCode code) 180 : RiscvFault("Address", false, code), _addr(addr) 181 {} 182 183 MiscReg trap_value() const override { return _addr; } 184}; 185 186class BreakpointFault : public RiscvFault 187{ 188 private: 189 const PCState pcState; 190 191 public: 192 BreakpointFault(const PCState &pc) 193 : RiscvFault("Breakpoint", false, BREAKPOINT), pcState(pc) 194 {} 195 196 MiscReg trap_value() const override { return pcState.pc(); } 197 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 198}; 199 200class SyscallFault : public RiscvFault 201{ 202 public: 203 SyscallFault(PrivilegeMode prv) 204 : RiscvFault("System call", false, ECALL_USER) 205 { 206 switch (prv) { 207 case PRV_U: 208 _code = ECALL_USER; 209 break; 210 case PRV_S: 211 _code = ECALL_SUPER; 212 break; 213 case PRV_M: 214 _code = ECALL_MACHINE; 215 break; 216 default: 217 panic("Unknown privilege mode %d.", prv); 218 break; 219 } 220 } 221 222 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override; 223}; 224 225} // namespace RiscvISA 226 227#endif // __ARCH_RISCV_FAULTS_HH__ 228