faults.cc revision 12808
111723Sar4jc@virginia.edu/* 211723Sar4jc@virginia.edu * Copyright (c) 2016 RISC-V Foundation 311723Sar4jc@virginia.edu * Copyright (c) 2016 The University of Virginia 412808Srobert.scheffel1@tu-dresden.de * Copyright (c) 2018 TU Dresden 511723Sar4jc@virginia.edu * All rights reserved. 611723Sar4jc@virginia.edu * 711723Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without 811723Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are 911723Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright 1011723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer; 1111723Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright 1211723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the 1311723Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution; 1411723Sar4jc@virginia.edu * neither the name of the copyright holders nor the names of its 1511723Sar4jc@virginia.edu * contributors may be used to endorse or promote products derived from 1611723Sar4jc@virginia.edu * this software without specific prior written permission. 1711723Sar4jc@virginia.edu * 1811723Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1911723Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2011723Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2111723Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2211723Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2311723Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2411723Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2511723Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2611723Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2711723Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2811723Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2911723Sar4jc@virginia.edu * 3011723Sar4jc@virginia.edu * Authors: Alec Roelke 3112808Srobert.scheffel1@tu-dresden.de * Robert Scheffel 3211723Sar4jc@virginia.edu */ 3311723Sar4jc@virginia.edu#include "arch/riscv/faults.hh" 3411723Sar4jc@virginia.edu 3512808Srobert.scheffel1@tu-dresden.de#include "arch/riscv/system.hh" 3611723Sar4jc@virginia.edu#include "arch/riscv/utility.hh" 3712808Srobert.scheffel1@tu-dresden.de#include "cpu/base.hh" 3811723Sar4jc@virginia.edu#include "cpu/thread_context.hh" 3911723Sar4jc@virginia.edu#include "sim/debug.hh" 4011723Sar4jc@virginia.edu#include "sim/full_system.hh" 4111723Sar4jc@virginia.edu 4211723Sar4jc@virginia.eduusing namespace RiscvISA; 4311723Sar4jc@virginia.edu 4411723Sar4jc@virginia.eduvoid 4511723Sar4jc@virginia.eduRiscvFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 4611723Sar4jc@virginia.edu{ 4711723Sar4jc@virginia.edu panic("Fault %s encountered at pc 0x%016llx.", name(), tc->pcState().pc()); 4811723Sar4jc@virginia.edu} 4911723Sar4jc@virginia.edu 5011723Sar4jc@virginia.eduvoid 5111723Sar4jc@virginia.eduRiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 5211723Sar4jc@virginia.edu{ 5311723Sar4jc@virginia.edu if (FullSystem) { 5411723Sar4jc@virginia.edu panic("Full system mode not supported for RISC-V."); 5511723Sar4jc@virginia.edu } else { 5611723Sar4jc@virginia.edu invoke_se(tc, inst); 5711723Sar4jc@virginia.edu PCState pcState = tc->pcState(); 5811723Sar4jc@virginia.edu advancePC(pcState, inst); 5911723Sar4jc@virginia.edu tc->pcState(pcState); 6011723Sar4jc@virginia.edu } 6111723Sar4jc@virginia.edu} 6211723Sar4jc@virginia.edu 6312808Srobert.scheffel1@tu-dresden.devoid Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst) 6412808Srobert.scheffel1@tu-dresden.de{ 6512808Srobert.scheffel1@tu-dresden.de if (FullSystem) { 6612808Srobert.scheffel1@tu-dresden.de tc->getCpuPtr()->clearInterrupts(tc->threadId()); 6712808Srobert.scheffel1@tu-dresden.de tc->clearArchRegs(); 6812808Srobert.scheffel1@tu-dresden.de } 6912808Srobert.scheffel1@tu-dresden.de 7012808Srobert.scheffel1@tu-dresden.de // Advance the PC to the implementation-defined reset vector 7112808Srobert.scheffel1@tu-dresden.de PCState pc = static_cast<RiscvSystem *>(tc->getSystemPtr())->resetVect(); 7212808Srobert.scheffel1@tu-dresden.de tc->pcState(pc); 7312808Srobert.scheffel1@tu-dresden.de} 7412808Srobert.scheffel1@tu-dresden.de 7511723Sar4jc@virginia.eduvoid 7611723Sar4jc@virginia.eduUnknownInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 7711723Sar4jc@virginia.edu{ 7811723Sar4jc@virginia.edu panic("Unknown instruction 0x%08x at pc 0x%016llx", inst->machInst, 7911723Sar4jc@virginia.edu tc->pcState().pc()); 8011723Sar4jc@virginia.edu} 8111723Sar4jc@virginia.edu 8211723Sar4jc@virginia.eduvoid 8312136Sar4jc@virginia.eduIllegalInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 8412136Sar4jc@virginia.edu{ 8512136Sar4jc@virginia.edu panic("Illegal instruction 0x%08x at pc 0x%016llx: %s", inst->machInst, 8612136Sar4jc@virginia.edu tc->pcState().pc(), reason.c_str()); 8712136Sar4jc@virginia.edu} 8812136Sar4jc@virginia.edu 8912136Sar4jc@virginia.eduvoid 9011723Sar4jc@virginia.eduUnimplementedFault::invoke_se(ThreadContext *tc, 9111723Sar4jc@virginia.edu const StaticInstPtr &inst) 9211723Sar4jc@virginia.edu{ 9311723Sar4jc@virginia.edu panic("Unimplemented instruction %s at pc 0x%016llx", instName, 9411723Sar4jc@virginia.edu tc->pcState().pc()); 9511723Sar4jc@virginia.edu} 9611723Sar4jc@virginia.edu 9711723Sar4jc@virginia.eduvoid 9811725Sar4jc@virginia.eduIllegalFrmFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 9911725Sar4jc@virginia.edu{ 10011725Sar4jc@virginia.edu panic("Illegal floating-point rounding mode 0x%x at pc 0x%016llx.", 10111725Sar4jc@virginia.edu frm, tc->pcState().pc()); 10211725Sar4jc@virginia.edu} 10311725Sar4jc@virginia.edu 10411725Sar4jc@virginia.eduvoid 10511723Sar4jc@virginia.eduBreakpointFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 10611723Sar4jc@virginia.edu{ 10711723Sar4jc@virginia.edu schedRelBreak(0); 10811723Sar4jc@virginia.edu} 10911723Sar4jc@virginia.edu 11011723Sar4jc@virginia.eduvoid 11111723Sar4jc@virginia.eduSyscallFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 11211723Sar4jc@virginia.edu{ 11311877Sbrandon.potter@amd.com Fault *fault = NoFault; 11411877Sbrandon.potter@amd.com tc->syscall(tc->readIntReg(SyscallNumReg), fault); 11511723Sar4jc@virginia.edu} 116