faults.cc revision 12808
1/* 2 * Copyright (c) 2016 RISC-V Foundation 3 * Copyright (c) 2016 The University of Virginia 4 * Copyright (c) 2018 TU Dresden 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer; 11 * redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution; 14 * neither the name of the copyright holders nor the names of its 15 * contributors may be used to endorse or promote products derived from 16 * this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 * Authors: Alec Roelke 31 * Robert Scheffel 32 */ 33#include "arch/riscv/faults.hh" 34 35#include "arch/riscv/system.hh" 36#include "arch/riscv/utility.hh" 37#include "cpu/base.hh" 38#include "cpu/thread_context.hh" 39#include "sim/debug.hh" 40#include "sim/full_system.hh" 41 42using namespace RiscvISA; 43 44void 45RiscvFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 46{ 47 panic("Fault %s encountered at pc 0x%016llx.", name(), tc->pcState().pc()); 48} 49 50void 51RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 52{ 53 if (FullSystem) { 54 panic("Full system mode not supported for RISC-V."); 55 } else { 56 invoke_se(tc, inst); 57 PCState pcState = tc->pcState(); 58 advancePC(pcState, inst); 59 tc->pcState(pcState); 60 } 61} 62 63void Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst) 64{ 65 if (FullSystem) { 66 tc->getCpuPtr()->clearInterrupts(tc->threadId()); 67 tc->clearArchRegs(); 68 } 69 70 // Advance the PC to the implementation-defined reset vector 71 PCState pc = static_cast<RiscvSystem *>(tc->getSystemPtr())->resetVect(); 72 tc->pcState(pc); 73} 74 75void 76UnknownInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 77{ 78 panic("Unknown instruction 0x%08x at pc 0x%016llx", inst->machInst, 79 tc->pcState().pc()); 80} 81 82void 83IllegalInstFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 84{ 85 panic("Illegal instruction 0x%08x at pc 0x%016llx: %s", inst->machInst, 86 tc->pcState().pc(), reason.c_str()); 87} 88 89void 90UnimplementedFault::invoke_se(ThreadContext *tc, 91 const StaticInstPtr &inst) 92{ 93 panic("Unimplemented instruction %s at pc 0x%016llx", instName, 94 tc->pcState().pc()); 95} 96 97void 98IllegalFrmFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 99{ 100 panic("Illegal floating-point rounding mode 0x%x at pc 0x%016llx.", 101 frm, tc->pcState().pc()); 102} 103 104void 105BreakpointFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 106{ 107 schedRelBreak(0); 108} 109 110void 111SyscallFault::invoke_se(ThreadContext *tc, const StaticInstPtr &inst) 112{ 113 Fault *fault = NoFault; 114 tc->syscall(tc->readIntReg(SyscallNumReg), fault); 115} 116