mem.isa revision 10184:bbfa3152bdea
16313Sgblack@eecs.umich.edu// -*- mode:c++ -*- 26313Sgblack@eecs.umich.edu 36313Sgblack@eecs.umich.edu// Copyright (c) 2009 The University of Edinburgh 46313Sgblack@eecs.umich.edu// All rights reserved. 56313Sgblack@eecs.umich.edu// 66313Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 76313Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 86313Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 96313Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 106313Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 116313Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 126313Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 136313Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 146313Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 156313Sgblack@eecs.umich.edu// this software without specific prior written permission. 166313Sgblack@eecs.umich.edu// 176313Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186313Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196313Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206313Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216313Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226313Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236313Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246313Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256313Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266313Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276313Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286313Sgblack@eecs.umich.edu// 296313Sgblack@eecs.umich.edu// Authors: Timothy M. Jones 306313Sgblack@eecs.umich.edu 316313Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 326336Sgblack@eecs.umich.edu// 336336Sgblack@eecs.umich.edu// Memory-format instructions 346313Sgblack@eecs.umich.edu// 356336Sgblack@eecs.umich.edu 366313Sgblack@eecs.umich.edudef template LoadStoreDeclare {{ 376313Sgblack@eecs.umich.edu /** 386313Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 396313Sgblack@eecs.umich.edu */ 406313Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 416336Sgblack@eecs.umich.edu { 426336Sgblack@eecs.umich.edu public: 436336Sgblack@eecs.umich.edu 446712Snate@binkert.org /// Constructor. 456336Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst); 466336Sgblack@eecs.umich.edu 476336Sgblack@eecs.umich.edu %(BasicExecDeclare)s 486336Sgblack@eecs.umich.edu 496336Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 506336Sgblack@eecs.umich.edu 516336Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 526336Sgblack@eecs.umich.edu }; 536336Sgblack@eecs.umich.edu}}; 546336Sgblack@eecs.umich.edu 556336Sgblack@eecs.umich.edu 566336Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 576336Sgblack@eecs.umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 586336Sgblack@eecs.umich.edu}}; 596336Sgblack@eecs.umich.edu 606336Sgblack@eecs.umich.edu 616336Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 626336Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 636336Sgblack@eecs.umich.edu}}; 646336Sgblack@eecs.umich.edu 656336Sgblack@eecs.umich.edu 666336Sgblack@eecs.umich.edudef template LoadStoreConstructor {{ 676336Sgblack@eecs.umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst) 686336Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 696336Sgblack@eecs.umich.edu { 706336Sgblack@eecs.umich.edu %(constructor)s; 716336Sgblack@eecs.umich.edu } 726336Sgblack@eecs.umich.edu}}; 736336Sgblack@eecs.umich.edu 746336Sgblack@eecs.umich.edu 756336Sgblack@eecs.umich.edudef template LoadExecute {{ 766336Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 776336Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 786336Sgblack@eecs.umich.edu { 796336Sgblack@eecs.umich.edu Addr EA; 806336Sgblack@eecs.umich.edu Fault fault = NoFault; 816336Sgblack@eecs.umich.edu 826336Sgblack@eecs.umich.edu %(op_decl)s; 836336Sgblack@eecs.umich.edu %(op_rd)s; 846336Sgblack@eecs.umich.edu %(ea_code)s; 856336Sgblack@eecs.umich.edu 866336Sgblack@eecs.umich.edu if (fault == NoFault) { 876336Sgblack@eecs.umich.edu fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 886336Sgblack@eecs.umich.edu %(memacc_code)s; 896336Sgblack@eecs.umich.edu } 906336Sgblack@eecs.umich.edu 916336Sgblack@eecs.umich.edu if (fault == NoFault) { 926336Sgblack@eecs.umich.edu %(op_wb)s; 936336Sgblack@eecs.umich.edu } 946336Sgblack@eecs.umich.edu 956336Sgblack@eecs.umich.edu return fault; 966336Sgblack@eecs.umich.edu } 976336Sgblack@eecs.umich.edu}}; 986336Sgblack@eecs.umich.edu 996336Sgblack@eecs.umich.edu 1006313Sgblack@eecs.umich.edudef template LoadInitiateAcc {{ 1016313Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 1026336Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1036336Sgblack@eecs.umich.edu { 1046336Sgblack@eecs.umich.edu Addr EA; 1056336Sgblack@eecs.umich.edu Fault fault = NoFault; 1066336Sgblack@eecs.umich.edu 1076313Sgblack@eecs.umich.edu %(op_src_decl)s; 1086313Sgblack@eecs.umich.edu %(op_rd)s; 1096313Sgblack@eecs.umich.edu %(ea_code)s; 1106313Sgblack@eecs.umich.edu 1116313Sgblack@eecs.umich.edu if (fault == NoFault) { 1126336Sgblack@eecs.umich.edu fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags); 1136336Sgblack@eecs.umich.edu xc->setEA(EA); 1146336Sgblack@eecs.umich.edu } 1156336Sgblack@eecs.umich.edu 1166336Sgblack@eecs.umich.edu return fault; 1176336Sgblack@eecs.umich.edu } 1186336Sgblack@eecs.umich.edu}}; 1196336Sgblack@eecs.umich.edu 1206336Sgblack@eecs.umich.edu 1216336Sgblack@eecs.umich.edudef template LoadCompleteAcc {{ 1226313Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 1236313Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 1246313Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1256336Sgblack@eecs.umich.edu { 1266313Sgblack@eecs.umich.edu Addr M5_VAR_USED EA; 1276336Sgblack@eecs.umich.edu Fault fault = NoFault; 1286336Sgblack@eecs.umich.edu 1296336Sgblack@eecs.umich.edu %(op_decl)s; 1306336Sgblack@eecs.umich.edu %(op_rd)s; 1316313Sgblack@eecs.umich.edu 1326313Sgblack@eecs.umich.edu EA = xc->getEA(); 1336313Sgblack@eecs.umich.edu 1346336Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 1356313Sgblack@eecs.umich.edu 1366336Sgblack@eecs.umich.edu if (fault == NoFault) { 1376336Sgblack@eecs.umich.edu %(memacc_code)s; 1386336Sgblack@eecs.umich.edu } 1396336Sgblack@eecs.umich.edu 1406336Sgblack@eecs.umich.edu if (fault == NoFault) { 1416336Sgblack@eecs.umich.edu %(op_wb)s; 1426336Sgblack@eecs.umich.edu } 1436336Sgblack@eecs.umich.edu 1446336Sgblack@eecs.umich.edu return fault; 1456313Sgblack@eecs.umich.edu } 1466313Sgblack@eecs.umich.edu}}; 1476313Sgblack@eecs.umich.edu 1486336Sgblack@eecs.umich.edu 1496313Sgblack@eecs.umich.edudef template StoreExecute {{ 1506336Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 1516336Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1526336Sgblack@eecs.umich.edu { 1536336Sgblack@eecs.umich.edu Addr EA; 1546336Sgblack@eecs.umich.edu Fault fault = NoFault; 1556336Sgblack@eecs.umich.edu 1566336Sgblack@eecs.umich.edu %(op_decl)s; 1576336Sgblack@eecs.umich.edu %(op_rd)s; 1586336Sgblack@eecs.umich.edu %(ea_code)s; 1596336Sgblack@eecs.umich.edu 1606336Sgblack@eecs.umich.edu if (fault == NoFault) { 1616336Sgblack@eecs.umich.edu %(memacc_code)s; 1626336Sgblack@eecs.umich.edu } 1636336Sgblack@eecs.umich.edu 1646336Sgblack@eecs.umich.edu if (fault == NoFault) { 1656336Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 1666336Sgblack@eecs.umich.edu NULL); 1676336Sgblack@eecs.umich.edu } 1686336Sgblack@eecs.umich.edu 1696336Sgblack@eecs.umich.edu if (fault == NoFault) { 1706336Sgblack@eecs.umich.edu %(op_wb)s; 1716336Sgblack@eecs.umich.edu } 1726336Sgblack@eecs.umich.edu 1736336Sgblack@eecs.umich.edu return fault; 1746336Sgblack@eecs.umich.edu } 1756336Sgblack@eecs.umich.edu}}; 1766336Sgblack@eecs.umich.edu 1776336Sgblack@eecs.umich.edu 1786336Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 1796336Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 1806336Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1816336Sgblack@eecs.umich.edu { 1826336Sgblack@eecs.umich.edu Addr EA; 1836336Sgblack@eecs.umich.edu Fault fault = NoFault; 1846336Sgblack@eecs.umich.edu 1856336Sgblack@eecs.umich.edu %(op_decl)s; 1866336Sgblack@eecs.umich.edu %(op_rd)s; 1876336Sgblack@eecs.umich.edu %(ea_code)s; 1886336Sgblack@eecs.umich.edu 1896336Sgblack@eecs.umich.edu if (fault == NoFault) { 1906336Sgblack@eecs.umich.edu %(memacc_code)s; 1916336Sgblack@eecs.umich.edu } 1926336Sgblack@eecs.umich.edu 1936336Sgblack@eecs.umich.edu if (fault == NoFault) { 1946336Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 1956336Sgblack@eecs.umich.edu NULL); 1966336Sgblack@eecs.umich.edu } 1976336Sgblack@eecs.umich.edu 1986336Sgblack@eecs.umich.edu // Need to write back any potential address register update 1996336Sgblack@eecs.umich.edu if (fault == NoFault) { 2006336Sgblack@eecs.umich.edu %(op_wb)s; 2016336Sgblack@eecs.umich.edu } 2026336Sgblack@eecs.umich.edu 2036336Sgblack@eecs.umich.edu return fault; 2046336Sgblack@eecs.umich.edu } 2056336Sgblack@eecs.umich.edu}}; 2066336Sgblack@eecs.umich.edu 2076336Sgblack@eecs.umich.edu 2086336Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 2096336Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 2106336Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 2116336Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2126336Sgblack@eecs.umich.edu { 2136336Sgblack@eecs.umich.edu return NoFault; 2146336Sgblack@eecs.umich.edu } 2156336Sgblack@eecs.umich.edu}}; 2166336Sgblack@eecs.umich.edu 2176336Sgblack@eecs.umich.edu 2186336Sgblack@eecs.umich.edu// The generic memory operation generator. This is called when two versions 2196336Sgblack@eecs.umich.edu// of an instruction are needed - when Ra == 0 and otherwise. This is so 2206336Sgblack@eecs.umich.edu// that instructions can use the value 0 when Ra == 0 but avoid having a 2216336Sgblack@eecs.umich.edu// dependence on Ra. 2226336Sgblack@eecs.umich.edulet {{ 2236336Sgblack@eecs.umich.edu 2246336Sgblack@eecs.umich.edudef GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0, base, 2256336Sgblack@eecs.umich.edu load_or_store, mem_flags = [], inst_flags = []): 2266336Sgblack@eecs.umich.edu 2276336Sgblack@eecs.umich.edu # First the version where Ra is non-zero 2286336Sgblack@eecs.umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 2296336Sgblack@eecs.umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 2306336Sgblack@eecs.umich.edu base_class = base, 2316336Sgblack@eecs.umich.edu decode_template = CheckRaDecode, 2326336Sgblack@eecs.umich.edu exec_template_base = load_or_store) 2336336Sgblack@eecs.umich.edu 2346336Sgblack@eecs.umich.edu # Now another version where Ra == 0 2356336Sgblack@eecs.umich.edu (header_output_ra0, decoder_output_ra0, _, exec_output_ra0) = \ 2366336Sgblack@eecs.umich.edu LoadStoreBase(name, Name + 'RaZero', ea_code_ra0, memacc_code, 2376336Sgblack@eecs.umich.edu mem_flags, inst_flags, 2386336Sgblack@eecs.umich.edu base_class = base, 2396336Sgblack@eecs.umich.edu exec_template_base = load_or_store) 2406336Sgblack@eecs.umich.edu 2416336Sgblack@eecs.umich.edu # Finally, add to the other outputs 2426336Sgblack@eecs.umich.edu header_output += header_output_ra0 2436336Sgblack@eecs.umich.edu decoder_output += decoder_output_ra0 2446336Sgblack@eecs.umich.edu exec_output += exec_output_ra0 2456336Sgblack@eecs.umich.edu return (header_output, decoder_output, decode_block, exec_output) 2466336Sgblack@eecs.umich.edu 2476336Sgblack@eecs.umich.edu}}; 2486336Sgblack@eecs.umich.edu 2496336Sgblack@eecs.umich.edu 2506336Sgblack@eecs.umich.edudef format LoadIndexOp(memacc_code, ea_code = {{ EA = Ra + Rb; }}, 2516336Sgblack@eecs.umich.edu ea_code_ra0 = {{ EA = Rb; }}, 2526336Sgblack@eecs.umich.edu mem_flags = [], inst_flags = []) {{ 2536336Sgblack@eecs.umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 2546336Sgblack@eecs.umich.edu GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0, 2556336Sgblack@eecs.umich.edu 'MemOp', 'Load', mem_flags, inst_flags) 2566336Sgblack@eecs.umich.edu}}; 2576336Sgblack@eecs.umich.edu 2586336Sgblack@eecs.umich.edu 2596336Sgblack@eecs.umich.edudef format StoreIndexOp(memacc_code, ea_code = {{ EA = Ra + Rb; }}, 2606336Sgblack@eecs.umich.edu ea_code_ra0 = {{ EA = Rb; }}, 2616336Sgblack@eecs.umich.edu mem_flags = [], inst_flags = []) {{ 2626336Sgblack@eecs.umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 2636336Sgblack@eecs.umich.edu GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0, 2646336Sgblack@eecs.umich.edu 'MemOp', 'Store', mem_flags, inst_flags) 2656336Sgblack@eecs.umich.edu}}; 2666336Sgblack@eecs.umich.edu 2676336Sgblack@eecs.umich.edu 2686336Sgblack@eecs.umich.edudef format LoadIndexUpdateOp(memacc_code, ea_code = {{ EA = Ra + Rb; }}, 2696336Sgblack@eecs.umich.edu mem_flags = [], inst_flags = []) {{ 2706336Sgblack@eecs.umich.edu 2716336Sgblack@eecs.umich.edu # Add in the update code 2726336Sgblack@eecs.umich.edu memacc_code += 'Ra = EA;' 2736336Sgblack@eecs.umich.edu 2746336Sgblack@eecs.umich.edu # Generate the class 2756336Sgblack@eecs.umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 2766336Sgblack@eecs.umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 2776336Sgblack@eecs.umich.edu base_class = 'MemOp', 2786336Sgblack@eecs.umich.edu exec_template_base = 'Load') 2796336Sgblack@eecs.umich.edu}}; 2806336Sgblack@eecs.umich.edu 2816336Sgblack@eecs.umich.edu 2826336Sgblack@eecs.umich.edudef format StoreIndexUpdateOp(memacc_code, ea_code = {{ EA = Ra + Rb; }}, 2836336Sgblack@eecs.umich.edu mem_flags = [], inst_flags = []) {{ 2846336Sgblack@eecs.umich.edu 2856336Sgblack@eecs.umich.edu # Add in the update code 2866336Sgblack@eecs.umich.edu memacc_code += 'Ra = EA;' 2876336Sgblack@eecs.umich.edu 2886336Sgblack@eecs.umich.edu # Generate the class 2896336Sgblack@eecs.umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 2906336Sgblack@eecs.umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 2916336Sgblack@eecs.umich.edu base_class = 'MemOp', 2926336Sgblack@eecs.umich.edu exec_template_base = 'Store') 2936336Sgblack@eecs.umich.edu}}; 2946336Sgblack@eecs.umich.edu 2956336Sgblack@eecs.umich.edu 2966336Sgblack@eecs.umich.edudef format LoadDispOp(memacc_code, ea_code = {{ EA = Ra + disp; }}, 2976336Sgblack@eecs.umich.edu ea_code_ra0 = {{ EA = disp; }}, 2986336Sgblack@eecs.umich.edu mem_flags = [], inst_flags = []) {{ 2996336Sgblack@eecs.umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 3006336Sgblack@eecs.umich.edu GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0, 3016336Sgblack@eecs.umich.edu 'MemDispOp', 'Load', mem_flags, inst_flags) 3026336Sgblack@eecs.umich.edu}}; 3036336Sgblack@eecs.umich.edu 3046336Sgblack@eecs.umich.edu 3056336Sgblack@eecs.umich.edudef format StoreDispOp(memacc_code, ea_code = {{ EA = Ra + disp; }}, 3066336Sgblack@eecs.umich.edu ea_code_ra0 = {{ EA = disp; }}, 3076336Sgblack@eecs.umich.edu mem_flags = [], inst_flags = []) {{ 3086336Sgblack@eecs.umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 3096336Sgblack@eecs.umich.edu GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0, 3106336Sgblack@eecs.umich.edu 'MemDispOp', 'Store', mem_flags, inst_flags) 3116336Sgblack@eecs.umich.edu}}; 3126336Sgblack@eecs.umich.edu 3136336Sgblack@eecs.umich.edu 3146336Sgblack@eecs.umich.edudef format LoadDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + disp; }}, 3156336Sgblack@eecs.umich.edu mem_flags = [], inst_flags = []) {{ 3166336Sgblack@eecs.umich.edu 3176336Sgblack@eecs.umich.edu # Add in the update code 3186336Sgblack@eecs.umich.edu memacc_code += 'Ra = EA;' 3196336Sgblack@eecs.umich.edu 3206336Sgblack@eecs.umich.edu # Generate the class 3216336Sgblack@eecs.umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 3226336Sgblack@eecs.umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 3236336Sgblack@eecs.umich.edu base_class = 'MemDispOp', 3246336Sgblack@eecs.umich.edu exec_template_base = 'Load') 3256336Sgblack@eecs.umich.edu}}; 3266336Sgblack@eecs.umich.edu 3276336Sgblack@eecs.umich.edu 3286336Sgblack@eecs.umich.edudef format StoreDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + disp; }}, 3296336Sgblack@eecs.umich.edu mem_flags = [], inst_flags = []) {{ 3306336Sgblack@eecs.umich.edu 3316336Sgblack@eecs.umich.edu # Add in the update code 3326336Sgblack@eecs.umich.edu memacc_code += 'Ra = EA;' 3336336Sgblack@eecs.umich.edu 3346336Sgblack@eecs.umich.edu # Generate the class 3356336Sgblack@eecs.umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 3366336Sgblack@eecs.umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 3376336Sgblack@eecs.umich.edu base_class = 'MemDispOp', 3386336Sgblack@eecs.umich.edu exec_template_base = 'Store') 3396336Sgblack@eecs.umich.edu}}; 3406336Sgblack@eecs.umich.edu