utility.hh revision 5254
12447SN/A/* 25254Sksewell@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 35254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 45254Sksewell@umich.edu * All rights reserved. 52447SN/A * 65254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 75254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 85254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 95254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 105254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 115254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 125254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 135254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 145254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 155254Sksewell@umich.edu * this software without specific prior written permission. 162447SN/A * 175254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282632Sstever@eecs.umich.edu * 295254Sksewell@umich.edu * Authors: Nathan Binkert 305254Sksewell@umich.edu * Steve Reinhardt 315254Sksewell@umich.edu * Korey Sewell 322447SN/A */ 332447SN/A 342447SN/A#ifndef __ARCH_MIPS_UTILITY_HH__ 352447SN/A#define __ARCH_MIPS_UTILITY_HH__ 365222Sksewell@umich.edu#include "config/full_system.hh" 372597SN/A#include "arch/mips/types.hh" 384661Sksewell@umich.edu#include "arch/mips/isa_traits.hh" 392597SN/A#include "base/misc.hh" 402980Sgblack@eecs.umich.edu#include "config/full_system.hh" 412972Sgblack@eecs.umich.edu//XXX This is needed for size_t. We should use something other than size_t 422980Sgblack@eecs.umich.edu//#include "kern/linux/linux.hh" 432597SN/A#include "sim/host.hh" 442597SN/A 454661Sksewell@umich.edu#include "cpu/thread_context.hh" 464661Sksewell@umich.edu 472980Sgblack@eecs.umich.educlass ThreadContext; 482980Sgblack@eecs.umich.edu 492597SN/Anamespace MipsISA { 502597SN/A 515222Sksewell@umich.edu uint64_t getArgument(ThreadContext *tc, int number, bool fp); 524826Ssaidi@eecs.umich.edu 535254Sksewell@umich.edu //////////////////////////////////////////////////////////////////////// 545254Sksewell@umich.edu // 555254Sksewell@umich.edu // Floating Point Utility Functions 565254Sksewell@umich.edu // 572686Sksewell@umich.edu uint64_t fpConvert(ConvertType cvt_type, double fp_val); 582686Sksewell@umich.edu double roundFP(double val, int digits); 592686Sksewell@umich.edu double truncFP(double val); 602686Sksewell@umich.edu 612686Sksewell@umich.edu bool getCondCode(uint32_t fcsr, int cc); 622686Sksewell@umich.edu uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val); 632686Sksewell@umich.edu uint32_t genInvalidVector(uint32_t fcsr); 642686Sksewell@umich.edu 652686Sksewell@umich.edu bool isNan(void *val_ptr, int size); 662686Sksewell@umich.edu bool isQnan(void *val_ptr, int size); 672686Sksewell@umich.edu bool isSnan(void *val_ptr, int size); 682972Sgblack@eecs.umich.edu 695222Sksewell@umich.edu static inline bool 705222Sksewell@umich.edu inUserMode(ThreadContext *tc) 715222Sksewell@umich.edu { 725222Sksewell@umich.edu MiscReg Stat = tc->readMiscReg(MipsISA::Status); 735222Sksewell@umich.edu MiscReg Dbg = tc->readMiscReg(MipsISA::Debug); 745222Sksewell@umich.edu 755222Sksewell@umich.edu if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible 765222Sksewell@umich.edu && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible 775222Sksewell@umich.edu && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode 785222Sksewell@umich.edu // Unable to use Status_CU0, etc directly, using bitfields & masks 795222Sksewell@umich.edu return true; 805222Sksewell@umich.edu } else { 815222Sksewell@umich.edu return false; 825222Sksewell@umich.edu } 835222Sksewell@umich.edu } 844661Sksewell@umich.edu 852972Sgblack@eecs.umich.edu // Instruction address compression hooks 862972Sgblack@eecs.umich.edu static inline Addr realPCToFetchPC(const Addr &addr) { 872972Sgblack@eecs.umich.edu return addr; 882972Sgblack@eecs.umich.edu } 892972Sgblack@eecs.umich.edu 902972Sgblack@eecs.umich.edu static inline Addr fetchPCToRealPC(const Addr &addr) { 912972Sgblack@eecs.umich.edu return addr; 922972Sgblack@eecs.umich.edu } 932972Sgblack@eecs.umich.edu 942972Sgblack@eecs.umich.edu // the size of "fetched" instructions (not necessarily the size 952972Sgblack@eecs.umich.edu // of real instructions for PISA) 962972Sgblack@eecs.umich.edu static inline size_t fetchInstSize() { 972972Sgblack@eecs.umich.edu return sizeof(MachInst); 982972Sgblack@eecs.umich.edu } 992972Sgblack@eecs.umich.edu 1005254Sksewell@umich.edu //////////////////////////////////////////////////////////////////////// 1015254Sksewell@umich.edu // 1025254Sksewell@umich.edu // Register File Utility Functions 1035254Sksewell@umich.edu // 1045222Sksewell@umich.edu static inline int flattenFloatIndex(ThreadContext * tc, int reg) 1055222Sksewell@umich.edu { 1065222Sksewell@umich.edu return reg; 1074194Ssaidi@eecs.umich.edu } 1085222Sksewell@umich.edu 1095254Sksewell@umich.edu static inline int flattenIntIndex(ThreadContext * tc, int reg) 1105254Sksewell@umich.edu { 1115254Sksewell@umich.edu // Implement Shadow Sets Stuff Here; 1125254Sksewell@umich.edu return reg; 1135254Sksewell@umich.edu } 1145254Sksewell@umich.edu 1155254Sksewell@umich.edu static inline MachInst makeRegisterCopy(int dest, int src) { 1165254Sksewell@umich.edu panic("makeRegisterCopy not implemented"); 1175254Sksewell@umich.edu return 0; 1185254Sksewell@umich.edu } 1195222Sksewell@umich.edu 1205222Sksewell@umich.edu void copyRegs(ThreadContext *src, ThreadContext *dest); 1215222Sksewell@umich.edu 1225222Sksewell@umich.edu void copyMiscRegs(ThreadContext *src, ThreadContext *dest); 1235222Sksewell@umich.edu 1245222Sksewell@umich.edu 1255222Sksewell@umich.edu template <class CPU> 1265222Sksewell@umich.edu void zeroRegisters(CPU *cpu); 1275222Sksewell@umich.edu 1285222Sksewell@umich.edu //////////////////////////////////////////////////////////////////////// 1295222Sksewell@umich.edu // 1305222Sksewell@umich.edu // Translation stuff 1315222Sksewell@umich.edu // 1325222Sksewell@umich.edu inline Addr 1335222Sksewell@umich.edu TruncPage(Addr addr) 1345222Sksewell@umich.edu { return addr & ~(PageBytes - 1); } 1355222Sksewell@umich.edu 1365222Sksewell@umich.edu inline Addr 1375222Sksewell@umich.edu RoundPage(Addr addr) 1385222Sksewell@umich.edu { return (addr + PageBytes - 1) & ~(PageBytes - 1); } 1395222Sksewell@umich.edu 1405254Sksewell@umich.edu //////////////////////////////////////////////////////////////////////// 1415254Sksewell@umich.edu // 1425254Sksewell@umich.edu // CPU Utility 1435254Sksewell@umich.edu // 1445222Sksewell@umich.edu void initCPU(ThreadContext *tc, int cpuId); 1455222Sksewell@umich.edu 1465222Sksewell@umich.edu /** 1475222Sksewell@umich.edu * Function to check for and process any interrupts. 1485222Sksewell@umich.edu * @param tc The thread context. 1495222Sksewell@umich.edu */ 1505222Sksewell@umich.edu template <class TC> 1515222Sksewell@umich.edu void processInterrupts(TC *tc); 1525222Sksewell@umich.edu 1535254Sksewell@umich.edu void startupCPU(ThreadContext *tc, int cpuId); 1542597SN/A}; 1552447SN/A 1562686Sksewell@umich.edu 1572447SN/A#endif 158