utility.hh revision 5254 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Nathan Binkert
30 *          Steve Reinhardt
31 *          Korey Sewell
32 */
33
34#ifndef __ARCH_MIPS_UTILITY_HH__
35#define __ARCH_MIPS_UTILITY_HH__
36#include "config/full_system.hh"
37#include "arch/mips/types.hh"
38#include "arch/mips/isa_traits.hh"
39#include "base/misc.hh"
40#include "config/full_system.hh"
41//XXX This is needed for size_t. We should use something other than size_t
42//#include "kern/linux/linux.hh"
43#include "sim/host.hh"
44
45#include "cpu/thread_context.hh"
46
47class ThreadContext;
48
49namespace MipsISA {
50
51    uint64_t getArgument(ThreadContext *tc, int number, bool fp);
52
53    ////////////////////////////////////////////////////////////////////////
54    //
55    // Floating Point Utility Functions
56    //
57    uint64_t fpConvert(ConvertType cvt_type, double fp_val);
58    double roundFP(double val, int digits);
59    double truncFP(double val);
60
61    bool getCondCode(uint32_t fcsr, int cc);
62    uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val);
63    uint32_t genInvalidVector(uint32_t fcsr);
64
65    bool isNan(void *val_ptr, int size);
66    bool isQnan(void *val_ptr, int size);
67    bool isSnan(void *val_ptr, int size);
68
69    static inline bool
70    inUserMode(ThreadContext *tc)
71    {
72        MiscReg Stat = tc->readMiscReg(MipsISA::Status);
73        MiscReg Dbg = tc->readMiscReg(MipsISA::Debug);
74
75        if((Stat & 0x10000006) == 0  // EXL, ERL or CU0 set, CP0 accessible
76           && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
77           && (Stat & 0x00000018) != 0) {  // KSU = 0, kernel mode is base mode
78            // Unable to use Status_CU0, etc directly, using bitfields & masks
79            return true;
80        } else {
81            return false;
82        }
83    }
84
85    // Instruction address compression hooks
86    static inline Addr realPCToFetchPC(const Addr &addr) {
87        return addr;
88    }
89
90    static inline Addr fetchPCToRealPC(const Addr &addr) {
91        return addr;
92    }
93
94    // the size of "fetched" instructions (not necessarily the size
95    // of real instructions for PISA)
96    static inline size_t fetchInstSize() {
97        return sizeof(MachInst);
98    }
99
100    ////////////////////////////////////////////////////////////////////////
101    //
102    //  Register File Utility Functions
103    //
104    static inline int flattenFloatIndex(ThreadContext * tc, int reg)
105    {
106        return reg;
107    }
108
109    static inline int flattenIntIndex(ThreadContext * tc, int reg)
110    {
111        // Implement Shadow Sets Stuff Here;
112        return reg;
113    }
114
115    static inline MachInst makeRegisterCopy(int dest, int src) {
116        panic("makeRegisterCopy not implemented");
117        return 0;
118    }
119
120    void copyRegs(ThreadContext *src, ThreadContext *dest);
121
122    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
123
124
125    template <class CPU>
126    void zeroRegisters(CPU *cpu);
127
128    ////////////////////////////////////////////////////////////////////////
129    //
130    //  Translation stuff
131    //
132    inline Addr
133    TruncPage(Addr addr)
134    { return addr & ~(PageBytes - 1); }
135
136    inline Addr
137    RoundPage(Addr addr)
138    { return (addr + PageBytes - 1) & ~(PageBytes - 1); }
139
140    ////////////////////////////////////////////////////////////////////////
141    //
142    // CPU Utility
143    //
144    void initCPU(ThreadContext *tc, int cpuId);
145
146    /**
147     * Function to check for and process any interrupts.
148     * @param tc The thread context.
149     */
150    template <class TC>
151    void processInterrupts(TC *tc);
152
153    void startupCPU(ThreadContext *tc, int cpuId);
154};
155
156
157#endif
158