tlb.hh revision 7878 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Nathan Binkert
30 *          Steve Reinhardt
31 *          Jaidev Patwardhan
32 *          Korey Sewell
33 */
34
35#ifndef __ARCH_MIPS_TLB_HH__
36#define __ARCH_MIPS_TLB_HH__
37
38#include <map>
39
40#include "arch/mips/isa_traits.hh"
41#include "arch/mips/utility.hh"
42#include "arch/mips/vtophys.hh"
43#include "arch/mips/pagetable.hh"
44#include "base/statistics.hh"
45#include "mem/request.hh"
46#include "params/MipsTLB.hh"
47#include "sim/fault_fwd.hh"
48#include "sim/tlb.hh"
49#include "sim/sim_object.hh"
50
51class ThreadContext;
52
53/* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB
54   However, to maintain compatibility with other architectures, we'll
55   simply create an ITLB and DTLB that will point to the real TLB */
56namespace MipsISA {
57
58// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
59struct TlbEntry
60{
61    Addr _pageStart;
62    TlbEntry() {}
63    TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
64
65    Addr pageStart()
66    {
67        return _pageStart;
68    }
69
70    void
71    updateVaddr(Addr new_vaddr) {}
72
73    void serialize(std::ostream &os)
74    {
75        SERIALIZE_SCALAR(_pageStart);
76    }
77
78    void unserialize(Checkpoint *cp, const std::string &section)
79    {
80        UNSERIALIZE_SCALAR(_pageStart);
81    }
82
83};
84
85class TLB : public BaseTLB
86{
87  protected:
88    typedef std::multimap<Addr, int> PageTable;
89    PageTable lookupTable;      // Quick lookup into page table
90
91    MipsISA::PTE *table;        // the Page Table
92    int size;                   // TLB Size
93    int nlu;                    // not last used entry (for replacement)
94
95    void nextnlu() { if (++nlu >= size) nlu = 0; }
96    MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const;
97
98    mutable Stats::Scalar read_hits;
99    mutable Stats::Scalar read_misses;
100    mutable Stats::Scalar read_acv;
101    mutable Stats::Scalar read_accesses;
102    mutable Stats::Scalar write_hits;
103    mutable Stats::Scalar write_misses;
104    mutable Stats::Scalar write_acv;
105    mutable Stats::Scalar write_accesses;
106    Stats::Formula hits;
107    Stats::Formula misses;
108    Stats::Formula accesses;
109
110  public:
111    typedef MipsTLBParams Params;
112    TLB(const Params *p);
113
114    int probeEntry(Addr vpn,uint8_t) const;
115    MipsISA::PTE *getEntry(unsigned) const;
116    virtual ~TLB();
117    int smallPages;
118    int getsize() const { return size; }
119
120    MipsISA::PTE &index(bool advance = true);
121    void insert(Addr vaddr, MipsISA::PTE &pte);
122    void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
123    void flushAll();
124    void demapPage(Addr vaddr, uint64_t asn)
125    {
126        panic("demapPage unimplemented.\n");
127    }
128
129    // static helper functions... really
130    static bool validVirtualAddress(Addr vaddr);
131
132    static Fault checkCacheability(RequestPtr &req);
133
134    // Checkpointing
135    void serialize(std::ostream &os);
136    void unserialize(Checkpoint *cp, const std::string &section);
137
138    void regStats();
139
140    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
141    void translateTiming(RequestPtr req, ThreadContext *tc,
142            Translation *translation, Mode mode);
143
144  private:
145    Fault translateInst(RequestPtr req, ThreadContext *tc);
146    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
147};
148
149}
150
151
152
153#endif // __MIPS_MEMORY_HH__
154