tlb.hh revision 5225:b1de028eea16
11689SN/A/* 22326SN/A * Copyright (c) 2007 MIPS Technologies, Inc. 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Jaidev Patwardhan 291689SN/A */ 301689SN/A 312292SN/A#ifndef __ARCH_MIPS_TLB_HH__ 322292SN/A#define __ARCH_MIPS_TLB_HH__ 331060SN/A 341060SN/A#include <map> 351060SN/A 361461SN/A#include "arch/mips/isa_traits.hh" 371060SN/A#include "arch/mips/utility.hh" 386221Snate@binkert.org#include "arch/mips/vtophys.hh" 391717SN/A#include "arch/mips/pagetable.hh" 402292SN/A#include "base/statistics.hh" 412292SN/A#include "mem/request.hh" 421060SN/A#include "params/MipsDTB.hh" 435529Snate@binkert.org#include "params/MipsITB.hh" 442292SN/A#include "sim/faults.hh" 452292SN/A#include "sim/tlb.hh" 462292SN/A#include "sim/sim_object.hh" 472326SN/A 482326SN/Aclass ThreadContext; 492326SN/A 502326SN/A/* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB 512326SN/A However, to maintain compatibility with other architectures, we'll 522292SN/A simply create an ITLB and DTLB that will point to the real TLB */ 532326SN/Anamespace MipsISA { 542326SN/A 552326SN/A// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA 562326SN/Astruct TlbEntry 572326SN/A{ 582326SN/A Addr _pageStart; 592326SN/A TlbEntry() {} 602326SN/A TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {} 612326SN/A 622326SN/A Addr pageStart() 632326SN/A { 642292SN/A return _pageStart; 651681SN/A } 662292SN/A 671060SN/A void serialize(std::ostream &os) 681060SN/A { 691060SN/A SERIALIZE_SCALAR(_pageStart); 701061SN/A } 711061SN/A 722733Sktlim@umich.edu void unserialize(Checkpoint *cp, const std::string §ion) 731060SN/A { 741681SN/A UNSERIALIZE_SCALAR(_pageStart); 751061SN/A } 762292SN/A 771060SN/A}; 781061SN/A 791061SN/Aclass TLB : public SimObject 801061SN/A{ 811061SN/A protected: 821060SN/A typedef std::multimap<Addr, int> PageTable; 832733Sktlim@umich.edu PageTable lookupTable; // Quick lookup into page table 842292SN/A 852292SN/A MipsISA::PTE *table; // the Page Table 861060SN/A int size; // TLB Size 872292SN/A int nlu; // not last used entry (for replacement) 882292SN/A 892292SN/A void nextnlu() { if (++nlu >= size) nlu = 0; } 901060SN/A MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const; 912292SN/A 922292SN/A mutable Stats::Scalar<> read_hits; 932292SN/A mutable Stats::Scalar<> read_misses; 942292SN/A mutable Stats::Scalar<> read_acv; 952292SN/A mutable Stats::Scalar<> read_accesses; 962292SN/A mutable Stats::Scalar<> write_hits; 971060SN/A mutable Stats::Scalar<> write_misses; 981060SN/A mutable Stats::Scalar<> write_acv; 991060SN/A mutable Stats::Scalar<> write_accesses; 1002292SN/A Stats::Formula hits; 1011060SN/A Stats::Formula misses; 1021060SN/A Stats::Formula invalids; 1031060SN/A Stats::Formula accesses; 1041060SN/A 1051060SN/A public: 1062292SN/A typedef MipsTLBParams Params; 1071060SN/A TLB(const Params *p); 1082292SN/A 1092292SN/A int probeEntry(Addr vpn,uint8_t) const; 1102292SN/A MipsISA::PTE *getEntry(unsigned) const; 1112292SN/A virtual ~TLB(); 1122292SN/A int smallPages; 1132292SN/A int getsize() const { return size; } 1141060SN/A 1151060SN/A MipsISA::PTE &index(bool advance = true); 1162292SN/A void insert(Addr vaddr, MipsISA::PTE &pte); 1175529Snate@binkert.org void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages); 1181060SN/A void flushAll(); 1192292SN/A 1202292SN/A // static helper functions... really 1211062SN/A static bool validVirtualAddress(Addr vaddr); 1222292SN/A 1232632Sstever@eecs.umich.edu static Fault checkCacheability(RequestPtr &req); 1242632Sstever@eecs.umich.edu 1252292SN/A // Checkpointing 1262292SN/A void serialize(std::ostream &os); 1272292SN/A void unserialize(Checkpoint *cp, const std::string §ion); 1282871Sktlim@umich.edu 1292871Sktlim@umich.edu void regStats(); 1302871Sktlim@umich.edu}; 1312292SN/A 1322632Sstever@eecs.umich.educlass ITB : public TLB { 1332632Sstever@eecs.umich.edu public: 1342292SN/A typedef MipsTLBParams Params; 1352632Sstever@eecs.umich.edu ITB(const Params *p); 1362632Sstever@eecs.umich.edu 1372292SN/A Fault translate(RequestPtr &req, ThreadContext *tc); 1382632Sstever@eecs.umich.edu}; 1392632Sstever@eecs.umich.edu 1402292SN/Aclass DTB : public TLB { 1416221Snate@binkert.org public: 1422632Sstever@eecs.umich.edu typedef MipsTLBParams Params; 1432292SN/A DTB(const Params *p); 1442292SN/A 1452632Sstever@eecs.umich.edu Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false); 1462843Sktlim@umich.edu}; 1472863Sktlim@umich.edu 1482843Sktlim@umich.educlass UTB : public ITB, public DTB { 1492843Sktlim@umich.edu public: 1502843Sktlim@umich.edu typedef MipsTLBParams Params; 1512632Sstever@eecs.umich.edu UTB(const Params *p); 1522348SN/A 1532843Sktlim@umich.edu}; 1542632Sstever@eecs.umich.edu 1552348SN/A} 1562307SN/A 1572632Sstever@eecs.umich.edu 1582348SN/A 1592307SN/A#endif // __MIPS_MEMORY_HH__ 1602632Sstever@eecs.umich.edu