tlb.hh revision 5225:b1de028eea16
114039Sstacze01@arm.com/* 214039Sstacze01@arm.com * Copyright (c) 2007 MIPS Technologies, Inc. 314039Sstacze01@arm.com * All rights reserved. 414039Sstacze01@arm.com * 514039Sstacze01@arm.com * Redistribution and use in source and binary forms, with or without 614039Sstacze01@arm.com * modification, are permitted provided that the following conditions are 714039Sstacze01@arm.com * met: redistributions of source code must retain the above copyright 814039Sstacze01@arm.com * notice, this list of conditions and the following disclaimer; 914039Sstacze01@arm.com * redistributions in binary form must reproduce the above copyright 1014039Sstacze01@arm.com * notice, this list of conditions and the following disclaimer in the 1114039Sstacze01@arm.com * documentation and/or other materials provided with the distribution; 1214039Sstacze01@arm.com * neither the name of the copyright holders nor the names of its 1314039Sstacze01@arm.com * contributors may be used to endorse or promote products derived from 1414039Sstacze01@arm.com * this software without specific prior written permission. 1514039Sstacze01@arm.com * 1614039Sstacze01@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1714039Sstacze01@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1814039Sstacze01@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1914039Sstacze01@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2014039Sstacze01@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2114039Sstacze01@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2214039Sstacze01@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2314039Sstacze01@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2414039Sstacze01@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2514039Sstacze01@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2614039Sstacze01@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2714039Sstacze01@arm.com * 2814039Sstacze01@arm.com * Authors: Jaidev Patwardhan 2914039Sstacze01@arm.com */ 3014039Sstacze01@arm.com 3114039Sstacze01@arm.com#ifndef __ARCH_MIPS_TLB_HH__ 3214039Sstacze01@arm.com#define __ARCH_MIPS_TLB_HH__ 3314039Sstacze01@arm.com 3414039Sstacze01@arm.com#include <map> 3514039Sstacze01@arm.com 3614039Sstacze01@arm.com#include "arch/mips/isa_traits.hh" 3714039Sstacze01@arm.com#include "arch/mips/utility.hh" 3814039Sstacze01@arm.com#include "arch/mips/vtophys.hh" 3914039Sstacze01@arm.com#include "arch/mips/pagetable.hh" 4014039Sstacze01@arm.com#include "base/statistics.hh" 4114039Sstacze01@arm.com#include "mem/request.hh" 4214039Sstacze01@arm.com#include "params/MipsDTB.hh" 4314039Sstacze01@arm.com#include "params/MipsITB.hh" 4414039Sstacze01@arm.com#include "sim/faults.hh" 4514039Sstacze01@arm.com#include "sim/tlb.hh" 4614039Sstacze01@arm.com#include "sim/sim_object.hh" 4714039Sstacze01@arm.com 4814039Sstacze01@arm.comclass ThreadContext; 4914039Sstacze01@arm.com 5014039Sstacze01@arm.com/* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB 5114252Sgabeblack@google.com However, to maintain compatibility with other architectures, we'll 5214039Sstacze01@arm.com simply create an ITLB and DTLB that will point to the real TLB */ 5314039Sstacze01@arm.comnamespace MipsISA { 5414039Sstacze01@arm.com 5514039Sstacze01@arm.com// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA 5614039Sstacze01@arm.comstruct TlbEntry 5714252Sgabeblack@google.com{ 5814039Sstacze01@arm.com Addr _pageStart; 5914064Sadrian.herrera@arm.com TlbEntry() {} 6014064Sadrian.herrera@arm.com TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {} 6114064Sadrian.herrera@arm.com 6214039Sstacze01@arm.com Addr pageStart() 6314039Sstacze01@arm.com { 6414039Sstacze01@arm.com return _pageStart; 6514039Sstacze01@arm.com } 6614039Sstacze01@arm.com 6714039Sstacze01@arm.com void serialize(std::ostream &os) 6814039Sstacze01@arm.com { 6914039Sstacze01@arm.com SERIALIZE_SCALAR(_pageStart); 7014039Sstacze01@arm.com } 7114039Sstacze01@arm.com 7214039Sstacze01@arm.com void unserialize(Checkpoint *cp, const std::string §ion) 7314039Sstacze01@arm.com { 7414039Sstacze01@arm.com UNSERIALIZE_SCALAR(_pageStart); 7514039Sstacze01@arm.com } 7614039Sstacze01@arm.com 7714039Sstacze01@arm.com}; 7814039Sstacze01@arm.com 7914039Sstacze01@arm.comclass TLB : public SimObject 8014039Sstacze01@arm.com{ 8114039Sstacze01@arm.com protected: 8214039Sstacze01@arm.com typedef std::multimap<Addr, int> PageTable; 8314039Sstacze01@arm.com PageTable lookupTable; // Quick lookup into page table 8414039Sstacze01@arm.com 8514039Sstacze01@arm.com MipsISA::PTE *table; // the Page Table 8614223Sgiacomo.travaglini@arm.com int size; // TLB Size 8714039Sstacze01@arm.com int nlu; // not last used entry (for replacement) 8814039Sstacze01@arm.com 8914039Sstacze01@arm.com void nextnlu() { if (++nlu >= size) nlu = 0; } 9014039Sstacze01@arm.com MipsISA::PTE *lookup(Addr vpn, uint8_t asn) const; 9114039Sstacze01@arm.com 9214039Sstacze01@arm.com mutable Stats::Scalar<> read_hits; 9314039Sstacze01@arm.com mutable Stats::Scalar<> read_misses; 9414039Sstacze01@arm.com mutable Stats::Scalar<> read_acv; 9514039Sstacze01@arm.com mutable Stats::Scalar<> read_accesses; 9614039Sstacze01@arm.com mutable Stats::Scalar<> write_hits; 9714039Sstacze01@arm.com mutable Stats::Scalar<> write_misses; 9814039Sstacze01@arm.com mutable Stats::Scalar<> write_acv; 9914039Sstacze01@arm.com mutable Stats::Scalar<> write_accesses; 10014039Sstacze01@arm.com Stats::Formula hits; 10114039Sstacze01@arm.com Stats::Formula misses; 10214039Sstacze01@arm.com Stats::Formula invalids; 10314039Sstacze01@arm.com Stats::Formula accesses; 10414039Sstacze01@arm.com 10514039Sstacze01@arm.com public: 10614039Sstacze01@arm.com typedef MipsTLBParams Params; 10714039Sstacze01@arm.com TLB(const Params *p); 10814039Sstacze01@arm.com 10914039Sstacze01@arm.com int probeEntry(Addr vpn,uint8_t) const; 11014039Sstacze01@arm.com MipsISA::PTE *getEntry(unsigned) const; 11114039Sstacze01@arm.com virtual ~TLB(); 11214039Sstacze01@arm.com int smallPages; 11314039Sstacze01@arm.com int getsize() const { return size; } 11414039Sstacze01@arm.com 11514039Sstacze01@arm.com MipsISA::PTE &index(bool advance = true); 11614039Sstacze01@arm.com void insert(Addr vaddr, MipsISA::PTE &pte); 11714039Sstacze01@arm.com void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages); 11814039Sstacze01@arm.com void flushAll(); 11914039Sstacze01@arm.com 12014092Smatteo.andreozzi@arm.com // static helper functions... really 12114039Sstacze01@arm.com static bool validVirtualAddress(Addr vaddr); 12214039Sstacze01@arm.com 12314039Sstacze01@arm.com static Fault checkCacheability(RequestPtr &req); 12414039Sstacze01@arm.com 12514039Sstacze01@arm.com // Checkpointing 12614039Sstacze01@arm.com void serialize(std::ostream &os); 12714039Sstacze01@arm.com void unserialize(Checkpoint *cp, const std::string §ion); 12814039Sstacze01@arm.com 12914039Sstacze01@arm.com void regStats(); 13014039Sstacze01@arm.com}; 13114064Sadrian.herrera@arm.com 13214064Sadrian.herrera@arm.comclass ITB : public TLB { 13314064Sadrian.herrera@arm.com public: 13414064Sadrian.herrera@arm.com typedef MipsTLBParams Params; 13514064Sadrian.herrera@arm.com ITB(const Params *p); 13614064Sadrian.herrera@arm.com 13714064Sadrian.herrera@arm.com Fault translate(RequestPtr &req, ThreadContext *tc); 13814064Sadrian.herrera@arm.com}; 13914039Sstacze01@arm.com 14014039Sstacze01@arm.comclass DTB : public TLB { 14114039Sstacze01@arm.com public: 14214039Sstacze01@arm.com typedef MipsTLBParams Params; 14314039Sstacze01@arm.com DTB(const Params *p); 144 145 Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false); 146}; 147 148class UTB : public ITB, public DTB { 149 public: 150 typedef MipsTLBParams Params; 151 UTB(const Params *p); 152 153}; 154 155} 156 157 158 159#endif // __MIPS_MEMORY_HH__ 160