isa_traits.hh revision 8775:1e3ca5d77b53 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 *          Korey Sewell
31 *          Jaidev Patwardhan
32 */
33
34#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
35#define __ARCH_MIPS_ISA_TRAITS_HH__
36
37#include "arch/mips/types.hh"
38#include "base/types.hh"
39#include "config/full_system.hh"
40#include "cpu/static_inst_fwd.hh"
41
42namespace LittleEndianGuest {}
43
44namespace MipsISA
45{
46
47using namespace LittleEndianGuest;
48
49StaticInstPtr decodeInst(ExtMachInst);
50
51// MIPS DOES have a delay slot
52#define ISA_HAS_DELAY_SLOT 1
53
54const Addr PageShift = 13;
55const Addr PageBytes = ULL(1) << PageShift;
56const Addr Page_Mask = ~(PageBytes - 1);
57const Addr PageOffset = PageBytes - 1;
58
59
60////////////////////////////////////////////////////////////////////////
61//
62//  Translation stuff
63//
64
65const Addr PteShift = 3;
66const Addr NPtePageShift = PageShift - PteShift;
67const Addr NPtePage = ULL(1) << NPtePageShift;
68const Addr PteMask = NPtePage - 1;
69
70//// All 'Mapped' segments go through the TLB
71//// All other segments are translated by dropping the MSB, to give
72//// the corresponding physical address
73// User Segment - Mapped
74const Addr USegBase = ULL(0x0);
75const Addr USegEnd = ULL(0x7FFFFFFF);
76
77// Kernel Segment 0 - Unmapped
78const Addr KSeg0End = ULL(0x9FFFFFFF);
79const Addr KSeg0Base =  ULL(0x80000000);
80const Addr KSeg0Mask = ULL(0x1FFFFFFF);
81
82// Kernel Segment 1 - Unmapped, Uncached
83const Addr KSeg1End = ULL(0xBFFFFFFF);
84const Addr KSeg1Base = ULL(0xA0000000);
85const Addr KSeg1Mask = ULL(0x1FFFFFFF);
86
87// Kernel/Supervisor Segment - Mapped
88const Addr KSSegEnd = ULL(0xDFFFFFFF);
89const Addr KSSegBase = ULL(0xC0000000);
90
91// Kernel Segment 3 - Mapped
92const Addr KSeg3End = ULL(0xFFFFFFFF);
93const Addr KSeg3Base = ULL(0xE0000000);
94
95
96inline Addr Phys2K0Seg(Addr addr)
97{
98    return addr | KSeg0Base;
99}
100
101
102const unsigned VABits = 32;
103const unsigned PABits = 32; // Is this correct?
104const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
105const Addr VAddrUnImplMask = ~VAddrImplMask;
106inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
107inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
108inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
109
110const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
111
112////////////////////////////////////////////////////////////////////////
113//
114//  Interrupt levels
115//
116enum InterruptLevels
117{
118    INTLEVEL_SOFTWARE_MIN = 4,
119    INTLEVEL_SOFTWARE_MAX = 19,
120
121    INTLEVEL_EXTERNAL_MIN = 20,
122    INTLEVEL_EXTERNAL_MAX = 34,
123
124    INTLEVEL_IRQ0 = 20,
125    INTLEVEL_IRQ1 = 21,
126    INTINDEX_ETHERNET = 0,
127    INTINDEX_SCSI = 1,
128    INTLEVEL_IRQ2 = 22,
129    INTLEVEL_IRQ3 = 23,
130
131    INTLEVEL_SERIAL = 33,
132
133    NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
134};
135
136// MIPS modes
137enum mode_type
138{
139    mode_kernel = 0,        // kernel
140    mode_supervisor = 1,    // supervisor
141    mode_user = 2,          // user mode
142    mode_debug = 3,         // debug mode
143    mode_number             // number of modes
144};
145
146// return a no-op instruction... used for instruction fetch faults
147const ExtMachInst NoopMachInst = 0x00000000;
148
149const int LogVMPageSize = 13;       // 8K bytes
150const int VMPageSize = (1 << LogVMPageSize);
151
152const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
153
154const int MachineBytes = 4;
155const int WordBytes = 4;
156const int HalfwordBytes = 2;
157const int ByteBytes = 1;
158
159const int ANNOTE_NONE = 0;
160const uint32_t ITOUCH_ANNOTE = 0xffffffff;
161
162const bool HasUnalignedMemAcc = true;
163
164} // namespace MipsISA
165
166#endif // __ARCH_MIPS_ISA_TRAITS_HH__
167