isa_traits.hh revision 8229:78bf55f23338 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 *          Korey Sewell
31 *          Jaidev Patwardhan
32 */
33
34#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
35#define __ARCH_MIPS_ISA_TRAITS_HH__
36
37#include "arch/mips/mips_core_specific.hh"
38#include "arch/mips/types.hh"
39#include "base/types.hh"
40#include "config/full_system.hh"
41
42namespace LittleEndianGuest {}
43
44class StaticInstPtr;
45
46namespace MipsISA
47{
48
49using namespace LittleEndianGuest;
50
51StaticInstPtr decodeInst(ExtMachInst);
52
53// MIPS DOES have a delay slot
54#define ISA_HAS_DELAY_SLOT 1
55
56const Addr PageShift = 13;
57const Addr PageBytes = ULL(1) << PageShift;
58const Addr Page_Mask = ~(PageBytes - 1);
59const Addr PageOffset = PageBytes - 1;
60
61
62////////////////////////////////////////////////////////////////////////
63//
64//  Translation stuff
65//
66
67const Addr PteShift = 3;
68const Addr NPtePageShift = PageShift - PteShift;
69const Addr NPtePage = ULL(1) << NPtePageShift;
70const Addr PteMask = NPtePage - 1;
71
72//// All 'Mapped' segments go through the TLB
73//// All other segments are translated by dropping the MSB, to give
74//// the corresponding physical address
75// User Segment - Mapped
76const Addr USegBase = ULL(0x0);
77const Addr USegEnd = ULL(0x7FFFFFFF);
78
79// Kernel Segment 0 - Unmapped
80const Addr KSeg0End = ULL(0x9FFFFFFF);
81const Addr KSeg0Base =  ULL(0x80000000);
82const Addr KSeg0Mask = ULL(0x1FFFFFFF);
83
84// Kernel Segment 1 - Unmapped, Uncached
85const Addr KSeg1End = ULL(0xBFFFFFFF);
86const Addr KSeg1Base = ULL(0xA0000000);
87const Addr KSeg1Mask = ULL(0x1FFFFFFF);
88
89// Kernel/Supervisor Segment - Mapped
90const Addr KSSegEnd = ULL(0xDFFFFFFF);
91const Addr KSSegBase = ULL(0xC0000000);
92
93// Kernel Segment 3 - Mapped
94const Addr KSeg3End = ULL(0xFFFFFFFF);
95const Addr KSeg3Base = ULL(0xE0000000);
96
97
98inline Addr Phys2K0Seg(Addr addr)
99{
100    return addr | KSeg0Base;
101}
102
103
104const unsigned VABits = 32;
105const unsigned PABits = 32; // Is this correct?
106const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
107const Addr VAddrUnImplMask = ~VAddrImplMask;
108inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
109inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
110inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
111
112const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
113
114////////////////////////////////////////////////////////////////////////
115//
116//  Interrupt levels
117//
118enum InterruptLevels
119{
120    INTLEVEL_SOFTWARE_MIN = 4,
121    INTLEVEL_SOFTWARE_MAX = 19,
122
123    INTLEVEL_EXTERNAL_MIN = 20,
124    INTLEVEL_EXTERNAL_MAX = 34,
125
126    INTLEVEL_IRQ0 = 20,
127    INTLEVEL_IRQ1 = 21,
128    INTINDEX_ETHERNET = 0,
129    INTINDEX_SCSI = 1,
130    INTLEVEL_IRQ2 = 22,
131    INTLEVEL_IRQ3 = 23,
132
133    INTLEVEL_SERIAL = 33,
134
135    NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
136};
137
138// MIPS modes
139enum mode_type
140{
141    mode_kernel = 0,        // kernel
142    mode_supervisor = 1,    // supervisor
143    mode_user = 2,          // user mode
144    mode_debug = 3,         // debug mode
145    mode_number             // number of modes
146};
147
148// return a no-op instruction... used for instruction fetch faults
149const ExtMachInst NoopMachInst = 0x00000000;
150
151const int LogVMPageSize = 13;       // 8K bytes
152const int VMPageSize = (1 << LogVMPageSize);
153
154const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
155
156const int MachineBytes = 4;
157const int WordBytes = 4;
158const int HalfwordBytes = 2;
159const int ByteBytes = 1;
160
161const int ANNOTE_NONE = 0;
162const uint32_t ITOUCH_ANNOTE = 0xffffffff;
163
164// Memory accesses cannot be unaligned
165const bool HasUnalignedMemAcc = false;
166
167} // namespace MipsISA
168
169#endif // __ARCH_MIPS_ISA_TRAITS_HH__
170