isa_traits.hh revision 6035:4d27997b548c
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Gabe Black 30 * Korey Sewell 31 * Jaidev Patwardhan 32 */ 33 34#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 35#define __ARCH_MIPS_ISA_TRAITS_HH__ 36 37#include "arch/mips/types.hh" 38#include "arch/mips/mips_core_specific.hh" 39#include "config/full_system.hh" 40#include "sim/host.hh" 41 42namespace LittleEndianGuest {}; 43 44#define TARGET_MIPS 45 46class StaticInstPtr; 47 48namespace MipsISA 49{ 50 using namespace LittleEndianGuest; 51 52 StaticInstPtr decodeInst(ExtMachInst); 53 54 // MIPS DOES have a delay slot 55 #define ISA_HAS_DELAY_SLOT 1 56 57 const Addr PageShift = 13; 58 const Addr PageBytes = ULL(1) << PageShift; 59 const Addr Page_Mask = ~(PageBytes - 1); 60 const Addr PageOffset = PageBytes - 1; 61 62 63 //////////////////////////////////////////////////////////////////////// 64 // 65 // Translation stuff 66 // 67 68 const Addr PteShift = 3; 69 const Addr NPtePageShift = PageShift - PteShift; 70 const Addr NPtePage = ULL(1) << NPtePageShift; 71 const Addr PteMask = NPtePage - 1; 72 73 //// All 'Mapped' segments go through the TLB 74 //// All other segments are translated by dropping the MSB, to give 75 //// the corresponding physical address 76 // User Segment - Mapped 77 const Addr USegBase = ULL(0x0); 78 const Addr USegEnd = ULL(0x7FFFFFFF); 79 80 // Kernel Segment 0 - Unmapped 81 const Addr KSeg0End = ULL(0x9FFFFFFF); 82 const Addr KSeg0Base = ULL(0x80000000); 83 const Addr KSeg0Mask = ULL(0x1FFFFFFF); 84 85 // Kernel Segment 1 - Unmapped, Uncached 86 const Addr KSeg1End = ULL(0xBFFFFFFF); 87 const Addr KSeg1Base = ULL(0xA0000000); 88 const Addr KSeg1Mask = ULL(0x1FFFFFFF); 89 90 // Kernel/Supervisor Segment - Mapped 91 const Addr KSSegEnd = ULL(0xDFFFFFFF); 92 const Addr KSSegBase = ULL(0xC0000000); 93 94 // Kernel Segment 3 - Mapped 95 const Addr KSeg3End = ULL(0xFFFFFFFF); 96 const Addr KSeg3Base = ULL(0xE0000000); 97 98 99 // For loading... XXX This maybe could be USegEnd?? --ali 100 const Addr LoadAddrMask = ULL(0xffffffffff); 101 102 inline Addr Phys2K0Seg(Addr addr) 103 { 104 // if (addr & PAddrUncachedBit43) { 105// addr &= PAddrUncachedMask; 106// addr |= PAddrUncachedBit40; 107// } 108 return addr | KSeg0Base; 109 } 110 111 112 const unsigned VABits = 32; 113 const unsigned PABits = 32; // Is this correct? 114 const Addr VAddrImplMask = (ULL(1) << VABits) - 1; 115 const Addr VAddrUnImplMask = ~VAddrImplMask; 116 inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 117 inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; } 118 inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; } 119 120 const Addr PAddrImplMask = (ULL(1) << PABits) - 1; 121 122 //////////////////////////////////////////////////////////////////////// 123 // 124 // Interrupt levels 125 // 126 enum InterruptLevels 127 { 128 INTLEVEL_SOFTWARE_MIN = 4, 129 INTLEVEL_SOFTWARE_MAX = 19, 130 131 INTLEVEL_EXTERNAL_MIN = 20, 132 INTLEVEL_EXTERNAL_MAX = 34, 133 134 INTLEVEL_IRQ0 = 20, 135 INTLEVEL_IRQ1 = 21, 136 INTINDEX_ETHERNET = 0, 137 INTINDEX_SCSI = 1, 138 INTLEVEL_IRQ2 = 22, 139 INTLEVEL_IRQ3 = 23, 140 141 INTLEVEL_SERIAL = 33, 142 143 NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 144 }; 145 146 147 // MIPS modes 148 enum mode_type 149 { 150 mode_kernel = 0, // kernel 151 mode_supervisor = 1, // supervisor 152 mode_user = 2, // user mode 153 mode_debug = 3, // debug mode 154 mode_number // number of modes 155 }; 156 157 inline mode_type getOperatingMode(MiscReg Stat) 158 { 159 if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0) 160 return mode_kernel; 161 else{ 162 if((Stat & 0x18) == 0x8) 163 return mode_supervisor; 164 else if((Stat & 0x18) == 0x10) 165 return mode_user; 166 else return mode_number; 167 } 168 } 169 170 171 // return a no-op instruction... used for instruction fetch faults 172 const ExtMachInst NoopMachInst = 0x00000000; 173 174 // Constants Related to the number of registers 175 const int NumIntArchRegs = 32; 176 const int NumIntSpecialRegs = 9; 177 const int NumFloatArchRegs = 32; 178 const int NumFloatSpecialRegs = 5; 179 180 const int MaxShadowRegSets = 16; // Maximum number of shadow register sets 181 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs 182 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// 183 184 // Static instruction parameters 185 const int MaxInstSrcRegs = 10; 186 const int MaxInstDestRegs = 8; 187 188 // semantically meaningful register indices 189 const int ZeroReg = 0; 190 const int AssemblerReg = 1; 191 const int KernelReg0 = 26; 192 const int KernelReg1 = 27; 193 const int GlobalPointerReg = 28; 194 const int StackPointerReg = 29; 195 const int FramePointerReg = 30; 196 const int ReturnAddressReg = 31; 197 198 const int SyscallPseudoReturnReg = 3; 199 200 const int LogVMPageSize = 13; // 8K bytes 201 const int VMPageSize = (1 << LogVMPageSize); 202 203 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 204 205 const int MachineBytes = 4; 206 const int WordBytes = 4; 207 const int HalfwordBytes = 2; 208 const int ByteBytes = 1; 209 210 const int ANNOTE_NONE = 0; 211 const uint32_t ITOUCH_ANNOTE = 0xffffffff; 212 213 // These help enumerate all the registers for dependence tracking. 214 const int FP_Base_DepTag = NumIntRegs; 215 const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; 216 217 // Enumerate names for 'Control' Registers in the CPU 218 // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 219 // (Register Number-Register Select) Summary of Register 220 //------------------------------------------------------ 221 // The first set of names classify the CP0 names as Register Banks 222 // for easy indexing when using the 'RD + SEL' index combination 223 // in CP0 instructions. 224 enum MiscRegTags { 225 Index = Ctrl_Base_DepTag + 0, //Bank 0: 0 - 3 226 MVPControl, 227 MVPConf0, 228 MVPConf1, 229 230 CP0_Random = Ctrl_Base_DepTag + 8, //Bank 1: 8 - 15 231 VPEControl, 232 VPEConf0, 233 VPEConf1, 234 YQMask, 235 VPESchedule, 236 VPEScheFBack, 237 VPEOpt, 238 239 EntryLo0 = Ctrl_Base_DepTag + 16, //Bank 2: 16 - 23 240 TCStatus, 241 TCBind, 242 TCRestart, 243 TCHalt, 244 TCContext, 245 TCSchedule, 246 TCScheFBack, 247 248 EntryLo1 = Ctrl_Base_DepTag + 24, // Bank 3: 24 249 250 Context = Ctrl_Base_DepTag + 32, // Bank 4: 32 - 33 251 ContextConfig, 252 253 PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41 254 PageGrain = Ctrl_Base_DepTag + 41, 255 256 Wired = Ctrl_Base_DepTag + 48, //Bank 6:48-55 257 SRSConf0, 258 SRSConf1, 259 SRSConf2, 260 SRSConf3, 261 SRSConf4, 262 263 HWRena = Ctrl_Base_DepTag + 56, //Bank 7: 56-63 264 265 BadVAddr = Ctrl_Base_DepTag + 64, //Bank 8: 64-71 266 267 Count = Ctrl_Base_DepTag + 72, //Bank 9: 72-79 268 269 EntryHi = Ctrl_Base_DepTag + 80, //Bank 10: 80-87 270 271 Compare = Ctrl_Base_DepTag + 88, //Bank 11: 88-95 272 273 Status = Ctrl_Base_DepTag + 96, //Bank 12: 96-103 274 IntCtl, 275 SRSCtl, 276 SRSMap, 277 278 Cause = Ctrl_Base_DepTag + 104, //Bank 13: 104-111 279 280 EPC = Ctrl_Base_DepTag + 112, //Bank 14: 112-119 281 282 PRId = Ctrl_Base_DepTag + 120, //Bank 15: 120-127, 283 EBase, 284 285 Config = Ctrl_Base_DepTag + 128, //Bank 16: 128-135 286 Config1, 287 Config2, 288 Config3, 289 Config4, 290 Config5, 291 Config6, 292 Config7, 293 294 295 LLAddr = Ctrl_Base_DepTag + 136, //Bank 17: 136-143 296 297 WatchLo0 = Ctrl_Base_DepTag + 144, //Bank 18: 144-151 298 WatchLo1, 299 WatchLo2, 300 WatchLo3, 301 WatchLo4, 302 WatchLo5, 303 WatchLo6, 304 WatchLo7, 305 306 WatchHi0 = Ctrl_Base_DepTag + 152, //Bank 19: 152-159 307 WatchHi1, 308 WatchHi2, 309 WatchHi3, 310 WatchHi4, 311 WatchHi5, 312 WatchHi6, 313 WatchHi7, 314 315 XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167 316 317 //Bank 21: 168-175 318 319 //Bank 22: 176-183 320 321 Debug = Ctrl_Base_DepTag + 184, //Bank 23: 184-191 322 TraceControl1, 323 TraceControl2, 324 UserTraceData, 325 TraceBPC, 326 327 DEPC = Ctrl_Base_DepTag + 192, //Bank 24: 192-199 328 329 PerfCnt0 = Ctrl_Base_DepTag + 200, //Bank 25: 200-207 330 PerfCnt1, 331 PerfCnt2, 332 PerfCnt3, 333 PerfCnt4, 334 PerfCnt5, 335 PerfCnt6, 336 PerfCnt7, 337 338 ErrCtl = Ctrl_Base_DepTag + 208, //Bank 26: 208-215 339 340 CacheErr0 = Ctrl_Base_DepTag + 216, //Bank 27: 216-223 341 CacheErr1, 342 CacheErr2, 343 CacheErr3, 344 345 TagLo0 = Ctrl_Base_DepTag + 224, //Bank 28: 224-231 346 DataLo1, 347 TagLo2, 348 DataLo3, 349 TagLo4, 350 DataLo5, 351 TagLo6, 352 DataLo7, 353 354 TagHi0 = Ctrl_Base_DepTag + 232, //Bank 29: 232-239 355 DataHi1, 356 TagHi2, 357 DataHi3, 358 TagHi4, 359 DataHi5, 360 TagHi6, 361 DataHi7, 362 363 364 ErrorEPC = Ctrl_Base_DepTag + 240, //Bank 30: 240-247 365 366 DESAVE = Ctrl_Base_DepTag + 248, //Bank 31: 248-256 367 368 LLFlag = Ctrl_Base_DepTag + 257, 369 370 NumControlRegs 371 }; 372 373 const int TotalDataRegs = NumIntRegs + NumFloatRegs; 374 375 const int NumMiscRegs = NumControlRegs; 376 377 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 378 379 380}; 381 382#endif // __ARCH_MIPS_ISA_TRAITS_HH__ 383