isa_traits.hh revision 2605
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 30#define __ARCH_MIPS_ISA_TRAITS_HH__ 31 32#include "arch/mips/constants.hh" 33#include "arch/mips/types.hh" 34#include "arch/mips/regfile.hh" 35#include "arch/mips/faults.hh" 36#include "arch/mips/utility.hh" 37#include "base/misc.hh" 38#include "config/full_system.hh" 39#include "sim/byteswap.hh" 40#include "sim/host.hh" 41#include "sim/faults.hh" 42 43#include <vector> 44 45class FastCPU; 46class FullCPU; 47class Checkpoint; 48class ExecContext; 49 50namespace LittleEndianGuest {}; 51 52#define TARGET_MIPS 53 54class StaticInst; 55class StaticInstPtr; 56 57namespace MIPS34K { 58int DTB_ASN_ASN(uint64_t reg); 59int ITB_ASN_ASN(uint64_t reg); 60}; 61 62#if !FULL_SYSTEM 63class SyscallReturn { 64 public: 65 template <class T> 66 SyscallReturn(T v, bool s) 67 { 68 retval = (uint32_t)v; 69 success = s; 70 } 71 72 template <class T> 73 SyscallReturn(T v) 74 { 75 success = (v >= 0); 76 retval = (uint32_t)v; 77 } 78 79 ~SyscallReturn() {} 80 81 SyscallReturn& operator=(const SyscallReturn& s) { 82 retval = s.retval; 83 success = s.success; 84 return *this; 85 } 86 87 bool successful() { return success; } 88 uint64_t value() { return retval; } 89 90 91 private: 92 uint64_t retval; 93 bool success; 94}; 95#endif 96 97namespace MipsISA 98{ 99 using namespace LittleEndianGuest; 100 101 static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs) 102 { 103 if (return_value.successful()) { 104 // no error 105 regs->setIntReg(SyscallSuccessReg, 0); 106 regs->setIntReg(ReturnValueReg1, return_value.value()); 107 } else { 108 // got an error, return details 109 regs->setIntReg(SyscallSuccessReg, (IntReg) -1); 110 regs->setIntReg(ReturnValueReg1, -return_value.value()); 111 } 112 } 113 114 StaticInstPtr decodeInst(ExtMachInst); 115 116 static inline ExtMachInst 117 makeExtMI(MachInst inst, const uint64_t &pc) { 118#if FULL_SYSTEM 119 ExtMachInst ext_inst = inst; 120 if (pc && 0x1) 121 return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32); 122 else 123 return ext_inst; 124#else 125 return ExtMachInst(inst); 126#endif 127 } 128 129 /** 130 * Function to insure ISA semantics about 0 registers. 131 * @param xc The execution context. 132 */ 133 template <class XC> 134 void zeroRegisters(XC *xc); 135 136 const Addr MaxAddr = (Addr)-1; 137 138 void copyRegs(ExecContext *src, ExecContext *dest); 139 140 uint64_t fpConvert(double fp_val, ConvertType cvt_type); 141 double roundFP(double val); 142 inline double truncFP(double val); 143 bool unorderedFP(uint32_t val); 144 bool unorderedFP(uint64_t val); 145 bool getConditionCode(int cc); 146 void setConditionCode(int num, bool val); 147 148 // Machine operations 149 150 void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 151 int regnum); 152 153 void restoreMachineReg(RegFile ®s, const AnyReg ®, 154 int regnum); 155 156#if 0 157 static void serializeSpecialRegs(const Serializable::Proxy &proxy, 158 const RegFile ®s); 159 160 static void unserializeSpecialRegs(const IniFile *db, 161 const std::string &category, 162 ConfigNode *node, 163 RegFile ®s); 164#endif 165 166 static inline Addr alignAddress(const Addr &addr, 167 unsigned int nbytes) { 168 return (addr & ~(nbytes - 1)); 169 } 170 171 // Instruction address compression hooks 172 static inline Addr realPCToFetchPC(const Addr &addr) { 173 return addr; 174 } 175 176 static inline Addr fetchPCToRealPC(const Addr &addr) { 177 return addr; 178 } 179 180 // the size of "fetched" instructions (not necessarily the size 181 // of real instructions for PISA) 182 static inline size_t fetchInstSize() { 183 return sizeof(MachInst); 184 } 185 186 static inline MachInst makeRegisterCopy(int dest, int src) { 187 panic("makeRegisterCopy not implemented"); 188 return 0; 189 } 190 191}; 192 193#if FULL_SYSTEM 194 195#include "arch/mips/mips34k.hh" 196 197#endif 198 199using namespace MipsISA; 200 201#endif // __ARCH_MIPS_ISA_TRAITS_HH__ 202