isa_traits.hh revision 2447
12033Sbinkertn@umich.edu/* 281Sstever@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 381Sstever@eecs.umich.edu * All rights reserved. 481Sstever@eecs.umich.edu * 581Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 681Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 781Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 881Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 981Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 1081Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 1181Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 1281Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 1381Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 1481Sstever@eecs.umich.edu * this software without specific prior written permission. 1581Sstever@eecs.umich.edu * 1681Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1781Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1881Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1981Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2081Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2181Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2281Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2381Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2481Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2581Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2681Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2781Sstever@eecs.umich.edu */ 2881Sstever@eecs.umich.edu 2981Sstever@eecs.umich.edu#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 3081Sstever@eecs.umich.edu#define __ARCH_MIPS_ISA_TRAITS_HH__ 31664Sbinkertn@umich.edu 322033Sbinkertn@umich.edu//#include "arch/mips/misc_regfile.hh" 33664Sbinkertn@umich.edu#include "base/misc.hh" 34664Sbinkertn@umich.edu#include "config/full_system.hh" 35664Sbinkertn@umich.edu#include "sim/host.hh" 36664Sbinkertn@umich.edu#include "sim/faults.hh" 37664Sbinkertn@umich.edu 38664Sbinkertn@umich.edu#include <vector> 39664Sbinkertn@umich.edu 40664Sbinkertn@umich.educlass FastCPU; 41664Sbinkertn@umich.educlass FullCPU; 42class Checkpoint; 43 44namespace LittleEndianGuest {}; 45using namespace LittleEndianGuest; 46 47#define TARGET_MIPS 48 49class StaticInst; 50class StaticInstPtr; 51 52namespace MIPS34K { 53int DTB_ASN_ASN(uint64_t reg); 54int ITB_ASN_ASN(uint64_t reg); 55}; 56 57#if !FULL_SYSTEM 58class SyscallReturn { 59 public: 60 template <class T> 61 SyscallReturn(T v, bool s) 62 { 63 retval = (uint64_t)v; 64 success = s; 65 } 66 67 template <class T> 68 SyscallReturn(T v) 69 { 70 success = (v >= 0); 71 retval = (uint64_t)v; 72 } 73 74 ~SyscallReturn() {} 75 76 SyscallReturn& operator=(const SyscallReturn& s) { 77 retval = s.retval; 78 success = s.success; 79 return *this; 80 } 81 82 bool successful() { return success; } 83 uint64_t value() { return retval; } 84 85 86 private: 87 uint64_t retval; 88 bool success; 89}; 90#endif 91 92namespace MipsISA 93{ 94 typedef uint32_t MachInst; 95 typedef uint32_t MachInst; 96 typedef uint64_t ExtMachInst; 97 typedef uint8_t RegIndex; 98// typedef uint64_t Addr; 99 enum { 100 MemoryEnd = 0xffffffffffffffffULL, 101 102 NumIntRegs = 32, 103 NumFloatRegs = 32, 104 NumMiscRegs = 258, //account for hi,lo regs 105 106 MaxRegsOfAnyType = 32, 107 // Static instruction parameters 108 MaxInstSrcRegs = 3, 109 MaxInstDestRegs = 2, 110 111 // semantically meaningful register indices 112 ZeroReg = 0, // architecturally meaningful 113 // the rest of these depend on the ABI 114 StackPointerReg = 30, 115 GlobalPointerReg = 29, 116 ProcedureValueReg = 27, 117 ReturnAddressReg = 26, 118 ReturnValueReg = 0, 119 FramePointerReg = 15, 120 ArgumentReg0 = 16, 121 ArgumentReg1 = 17, 122 ArgumentReg2 = 18, 123 ArgumentReg3 = 19, 124 ArgumentReg4 = 20, 125 ArgumentReg5 = 21, 126 SyscallNumReg = ReturnValueReg, 127 SyscallPseudoReturnReg = ArgumentReg4, 128 SyscallSuccessReg = 19, 129 LogVMPageSize = 13, // 8K bytes 130 VMPageSize = (1 << LogVMPageSize), 131 132 BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned 133 134 WordBytes = 4, 135 HalfwordBytes = 2, 136 ByteBytes = 1, 137 DepNA = 0, 138 }; 139 140 // These enumerate all the registers for dependence tracking. 141 enum DependenceTags { 142 // 0..31 are the integer regs 0..31 143 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 144 FP_Base_DepTag = 32, 145 Ctrl_Base_DepTag = 64, 146 Fpcr_DepTag = 64, // floating point control register 147 Uniq_DepTag = 65, 148 IPR_Base_DepTag = 66, 149 MiscReg_DepTag = 67 150 }; 151 152 typedef uint64_t IntReg; 153 typedef IntReg IntRegFile[NumIntRegs]; 154 155 // floating point register file entry type 156 typedef union { 157 uint64_t q; 158 double d; 159 } FloatReg; 160 161 typedef union { 162 uint64_t q[NumFloatRegs]; // integer qword view 163 double d[NumFloatRegs]; // double-precision floating point view 164 } FloatRegFile; 165 166 // cop-0/cop-1 system control register file 167 typedef uint64_t MiscReg; 168//typedef MiscReg MiscRegFile[NumMiscRegs]; 169 class MiscRegFile { 170 171 protected: 172 uint64_t fpcr; // floating point condition codes 173 uint64_t uniq; // process-unique register 174 bool lock_flag; // lock flag for LL/SC 175 Addr lock_addr; // lock address for LL/SC 176 177 MiscReg miscRegFile[NumMiscRegs]; 178 179 public: 180 //These functions should be removed once the simplescalar cpu model 181 //has been replaced. 182 int getInstAsid(); 183 int getDataAsid(); 184 185 void copyMiscRegs(ExecContext *xc); 186 187 MiscReg readReg(int misc_reg) 188 { return miscRegFile[misc_reg]; } 189 190 MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc) 191 { return miscRegFile[misc_reg];} 192 193 Fault setReg(int misc_reg, const MiscReg &val) 194 { miscRegFile[misc_reg] = val; return NoFault; } 195 196 Fault setRegWithEffect(int misc_reg, const MiscReg &val, 197 ExecContext *xc) 198 { miscRegFile[misc_reg] = val; return NoFault; } 199 200#if FULL_SYSTEM 201 void clearIprs() { } 202 203 protected: 204 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs 205 206 private: 207 MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { } 208 209 Fault setIpr(int idx, uint64_t val, ExecContext *xc) { } 210#endif 211 friend class RegFile; 212 }; 213 214 enum MiscRegTags { 215 //Coprocessor 0 Registers 216 //Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 217 //(Register Number-Register Select) Summary of Register 218 //------------------------------------------------------ 219 Index = 0, //0-0 Index into the TLB array 220 221 MVPControl = 1, //0-1 Per-processor register containing global 222 //MIPS� MT configuration data 223 224 MVPConf0 = 2, //0-2 Per-processor register containing global 225 //MIPS� MT configuration data 226 227 MVPConf1 = 3, //0-3 Per-processor register containing global 228 //MIPS� MT configuration data 229 230 Random = 8, //1-0 Randomly generated index into the TLB array 231 232 VPEControl = 9, //1-1 Per-VPE register containing relatively volatile 233 //thread configuration data 234 235 VPEConf0 = 10, //1-2 Per-VPE multi-thread configuration 236 //information 237 238 239 VPEConf1 = 11, //1-2 Per-VPE multi-thread configuration 240 //information 241 242 YQMask = 12, //Per-VPE register defining which YIELD 243 //qualifier bits may be used without generating 244 //an exception 245 246 VPESchedule = 13, 247 VPEScheFBack = 14, 248 VPEOpt = 15, 249 EntryLo0 = 16, // Bank 3: 16 - 23 250 TCStatus = 17, 251 TCBind = 18, 252 TCRestart = 19, 253 TCHalt = 20, 254 TCContext = 21, 255 TCSchedule = 22, 256 TCScheFBack = 23, 257 258 EntryLo1 = 24,// Bank 4: 24 - 31 259 260 Context = 32, // Bank 5: 32 - 39 261 ContextConfig = 33, 262 263 //PageMask = 40, //Bank 6: 40 - 47 264 PageGrain = 41, 265 266 Wired = 48, //Bank 7:48 - 55 267 SRSConf0 = 49, 268 SRSConf1 = 50, 269 SRSConf2 = 51, 270 SRSConf3 = 52, 271 SRSConf4 = 53, 272 BadVAddr = 54, 273 274 HWRena = 56,//Bank 8:56 - 63 275 276 Count = 64, //Bank 9:64 - 71 277 278 EntryHi = 72,//Bank 10:72 - 79 279 280 Compare = 80,//Bank 11:80 - 87 281 282 Status = 88,//Bank 12:88 - 96 //12-0 Processor status and control 283 IntCtl = 89, //12-1 Interrupt system status and control 284 SRSCtl = 90, //12-2 Shadow register set status and control 285 SRSMap = 91, //12-3 Shadow set IPL mapping 286 287 Cause = 97,//97-104 //13-0 Cause of last general exception 288 289 EPC = 105,//105-112 //14-0 Program counter at last exception 290 291 PRId = 113,//113-120, //15-0 Processor identification and revision 292 EBase = 114, //15-1 Exception vector base register 293 294 Config = 121,//Bank 16: 121-128 295 Config1 = 122, 296 Config2 = 123, 297 Config3 = 124, 298 Config6 = 127, 299 Config7 = 128, 300 301 302 LLAddr = 129,//Bank 17: 129-136 303 304 WatchLo0 = 137,//Bank 18: 137-144 305 WatchLo1 = 138, 306 WatchLo2 = 139, 307 WatchLo3 = 140, 308 WatchLo4 = 141, 309 WatchLo5 = 142, 310 WatchLo6 = 143, 311 WatchLo7 = 144, 312 313 WatchHi0 = 145,//Bank 19: 145-152 314 WatchHi1 = 146, 315 WatchHi2 = 147, 316 WatchHi3 = 148, 317 WatchHi4 = 149, 318 WatchHi5 = 150, 319 WatchHi6 = 151, 320 WatchHi7 = 152, 321 322 XCContext64 = 153,//Bank 20: 153-160 323 324 //Bank 21: 161-168 325 326 //Bank 22: 169-176 327 328 Debug = 177, //Bank 23: 177-184 329 TraceControl1 = 178, 330 TraceControl2 = 179, 331 UserTraceData = 180, 332 TraceBPC = 181, 333 334 DEPC = 185,//Bank 24: 185-192 335 336 PerfCnt0 = 193,//Bank 25: 193 - 200 337 PerfCnt1 = 194, 338 PerfCnt2 = 195, 339 PerfCnt3 = 196, 340 PerfCnt4 = 197, 341 PerfCnt5 = 198, 342 PerfCnt6 = 199, 343 PerfCnt7 = 200, 344 345 ErrCtl = 201, //Bank 26: 201 - 208 346 347 CacheErr0 = 209, //Bank 27: 209 - 216 348 CacheErr1 = 210, 349 CacheErr2 = 211, 350 CacheErr3 = 212, 351 352 TagLo0 = 217,//Bank 28: 217 - 224 353 DataLo1 = 218, 354 TagLo2 = 219, 355 DataLo3 = 220, 356 TagLo4 = 221, 357 DataLo5 = 222, 358 TagLo6 = 223, 359 DataLo7 = 234, 360 361 TagHi0 = 233,//Bank 29: 233 - 240 362 DataHi1 = 234, 363 TagHi2 = 235, 364 DataHi3 = 236, 365 TagHi4 = 237, 366 DataHi5 = 238, 367 TagHi6 = 239, 368 DataHi7 = 240, 369 370 371 ErrorEPC = 249,//Bank 30: 241 - 248 372 373 DESAVE = 257,//Bank 31: 249-256 374 375 //More Misc. Regs 376 Hi, 377 Lo, 378 FCSR, 379 FPCR, 380 381 //Alpha Regs, but here now, for 382 //compiling sake 383 UNIQ, 384 LockAddr, 385 LockFlag 386 }; 387 388extern const Addr PageShift; 389extern const Addr PageBytes; 390extern const Addr PageMask; 391extern const Addr PageOffset; 392 393#if FULL_SYSTEM 394 395 typedef uint64_t InternalProcReg; 396 397#include "arch/mips/isa_fullsys_traits.hh" 398 399#else 400 enum { 401 NumInternalProcRegs = 0 402 }; 403#endif 404 405 enum { 406 TotalNumRegs = 407 NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs 408 }; 409 410 enum { 411 TotalDataRegs = NumIntRegs + NumFloatRegs 412 }; 413 414 typedef union { 415 IntReg intreg; 416 FloatReg fpreg; 417 MiscReg ctrlreg; 418 } AnyReg; 419 420 struct RegFile { 421 IntRegFile intRegFile; // (signed) integer register file 422 FloatRegFile floatRegFile; // floating point register file 423 MiscRegFile miscRegs; // control register file 424 425 426 Addr pc; // program counter 427 Addr npc; // next-cycle program counter 428 Addr nnpc; // next-next-cycle program counter 429 // used to implement branch delay slot 430 // not real register 431 432 MiscReg hi; // MIPS HI Register 433 MiscReg lo; // MIPS LO Register 434 435 436#if FULL_SYSTEM 437 IntReg palregs[NumIntRegs]; // PAL shadow registers 438 InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs 439 int intrflag; // interrupt flag 440 bool pal_shadow; // using pal_shadow registers 441 inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); } 442 inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); } 443#endif // FULL_SYSTEM 444 445 //void initCP0Regs(); 446 void serialize(std::ostream &os); 447 void unserialize(Checkpoint *cp, const std::string §ion); 448 449 void createCP0Regs(); 450 void coldReset(); 451 }; 452 453 StaticInstPtr decodeInst(ExtMachInst); 454 455 // return a no-op instruction... used for instruction fetch faults 456 extern const MachInst NoopMachInst; 457 458 enum annotes { 459 ANNOTE_NONE = 0, 460 // An impossible number for instruction annotations 461 ITOUCH_ANNOTE = 0xffffffff, 462 }; 463 464//void getMiscRegIdx(int reg_name,int &idx, int &sel); 465 466 static inline ExtMachInst 467 makeExtMI(MachInst inst, const uint64_t &pc) { 468#if FULL_SYSTEM 469 ExtMachInst ext_inst = inst; 470 if (pc && 0x1) 471 return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32); 472 else 473 return ext_inst; 474#else 475 return ExtMachInst(inst); 476#endif 477 } 478 479 static inline bool isCallerSaveIntegerRegister(unsigned int reg) { 480 panic("register classification not implemented"); 481 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 482 } 483 484 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 485 panic("register classification not implemented"); 486 return (reg >= 9 && reg <= 15); 487 } 488 489 static inline bool isCallerSaveFloatRegister(unsigned int reg) { 490 panic("register classification not implemented"); 491 return false; 492 } 493 494 static inline bool isCalleeSaveFloatRegister(unsigned int reg) { 495 panic("register classification not implemented"); 496 return false; 497 } 498 499 static inline Addr alignAddress(const Addr &addr, 500 unsigned int nbytes) { 501 return (addr & ~(nbytes - 1)); 502 } 503 504 // Instruction address compression hooks 505 static inline Addr realPCToFetchPC(const Addr &addr) { 506 return addr; 507 } 508 509 static inline Addr fetchPCToRealPC(const Addr &addr) { 510 return addr; 511 } 512 513 // the size of "fetched" instructions (not necessarily the size 514 // of real instructions for PISA) 515 static inline size_t fetchInstSize() { 516 return sizeof(MachInst); 517 } 518 519 static inline MachInst makeRegisterCopy(int dest, int src) { 520 panic("makeRegisterCopy not implemented"); 521 return 0; 522 } 523 524 static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs) 525 { 526 // check for error condition. SPARC syscall convention is to 527 // indicate success/failure in reg the carry bit of the ccr 528 // and put the return value itself in the standard return value reg (). 529 if (return_value.successful()) { 530 // no error 531 //regs->miscRegFile.ccrFields.iccFields.c = 0; 532 regs->intRegFile[ReturnValueReg] = return_value.value(); 533 } else { 534 // got an error, return details 535 //regs->miscRegFile.ccrFields.iccFields.c = 1; 536 regs->intRegFile[ReturnValueReg] = -return_value.value(); 537 } 538 } 539 540 // Machine operations 541 542 void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 543 int regnum); 544 545 void restoreMachineReg(RegFile ®s, const AnyReg ®, 546 int regnum); 547 548#if 0 549 static void serializeSpecialRegs(const Serializable::Proxy &proxy, 550 const RegFile ®s); 551 552 static void unserializeSpecialRegs(const IniFile *db, 553 const std::string &category, 554 ConfigNode *node, 555 RegFile ®s); 556#endif 557 558 /** 559 * Function to insure ISA semantics about 0 registers. 560 * @param xc The execution context. 561 */ 562 template <class XC> 563 void zeroRegisters(XC *xc); 564 565 const Addr MaxAddr = (Addr)-1; 566}; 567 568#if FULL_SYSTEM 569//typedef TheISA::InternalProcReg InternalProcReg; 570//const int NumInternalProcRegs = TheISA::NumInternalProcRegs; 571//const int NumInterruptLevels = TheISA::NumInterruptLevels; 572 573#include "arch/mips/mips34k.hh" 574#endif 575 576using namespace MipsISA; 577 578#endif // __ARCH_MIPS_ISA_TRAITS_HH__ 579