isa_traits.hh revision 2428
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 30#define __ARCH_MIPS_ISA_TRAITS_HH__ 31 32//#include "arch/mips/misc_regfile.hh" 33#include "base/misc.hh" 34#include "config/full_system.hh" 35#include "sim/host.hh" 36#include "sim/faults.hh" 37 38#include <vector> 39 40class FastCPU; 41class FullCPU; 42class Checkpoint; 43 44namespace LittleEndianGuest {}; 45using namespace LittleEndianGuest; 46 47#define TARGET_MIPS 48 49class StaticInst; 50class StaticInstPtr; 51 52namespace MIPS34K { 53int DTB_ASN_ASN(uint64_t reg); 54int ITB_ASN_ASN(uint64_t reg); 55}; 56 57namespace MipsISA 58{ 59 typedef uint32_t MachInst; 60// typedef uint64_t Addr; 61 typedef uint8_t RegIndex; 62 63 enum { 64 MemoryEnd = 0xffffffffffffffffULL, 65 66 NumIntRegs = 32, 67 NumFloatRegs = 32, 68 NumMiscRegs = 258, //account for hi,lo regs 69 70 MaxRegsOfAnyType = 32, 71 // Static instruction parameters 72 MaxInstSrcRegs = 3, 73 MaxInstDestRegs = 2, 74 75 // semantically meaningful register indices 76 ZeroReg = 0, // architecturally meaningful 77 // the rest of these depend on the ABI 78 StackPointerReg = 30, 79 GlobalPointerReg = 29, 80 ProcedureValueReg = 27, 81 ReturnAddressReg = 26, 82 ReturnValueReg = 0, 83 FramePointerReg = 15, 84 ArgumentReg0 = 16, 85 ArgumentReg1 = 17, 86 ArgumentReg2 = 18, 87 ArgumentReg3 = 19, 88 ArgumentReg4 = 20, 89 ArgumentReg5 = 21, 90 91 LogVMPageSize = 13, // 8K bytes 92 VMPageSize = (1 << LogVMPageSize), 93 94 BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned 95 96 WordBytes = 4, 97 HalfwordBytes = 2, 98 ByteBytes = 1, 99 DepNA = 0, 100 }; 101 102 // These enumerate all the registers for dependence tracking. 103 enum DependenceTags { 104 // 0..31 are the integer regs 0..31 105 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 106 FP_Base_DepTag = 32, 107 Ctrl_Base_DepTag = 64, 108 Fpcr_DepTag = 64, // floating point control register 109 Uniq_DepTag = 65, 110 IPR_Base_DepTag = 66, 111 MiscReg_DepTag = 67 112 }; 113 114 typedef uint64_t IntReg; 115 typedef IntReg IntRegFile[NumIntRegs]; 116 117 // floating point register file entry type 118 typedef union { 119 uint64_t q; 120 double d; 121 } FloatReg; 122 123 typedef union { 124 uint64_t q[NumFloatRegs]; // integer qword view 125 double d[NumFloatRegs]; // double-precision floating point view 126 } FloatRegFile; 127 128 // cop-0/cop-1 system control register file 129 typedef uint64_t MiscReg; 130//typedef MiscReg MiscRegFile[NumMiscRegs]; 131 class MiscRegFile { 132 public: 133 MiscReg 134 protected: 135 uint64_t fpcr; // floating point condition codes 136 uint64_t uniq; // process-unique register 137 bool lock_flag; // lock flag for LL/SC 138 Addr lock_addr; // lock address for LL/SC 139 140 MiscReg miscRegFile[NumMiscRegs]; 141 142 public: 143 //These functions should be removed once the simplescalar cpu model 144 //has been replaced. 145 int getInstAsid(); 146 int getDataAsid(); 147 148 MiscReg readReg(int misc_reg) 149 { return miscRegFile[misc_reg]; } 150 151 MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc) 152 { return miscRegFile[misc_reg];} 153 154 Fault setReg(int misc_reg, const MiscReg &val) 155 { miscRegFile[misc_reg] = val; return NoFault; } 156 157 Fault setRegWithEffect(int misc_reg, const MiscReg &val, 158 ExecContext *xc) 159 { miscRegFile[misc_reg] = val; return NoFault; } 160 161#if FULL_SYSTEM 162 void clearIprs() { }; 163 164 protected: 165 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs 166 167 private: 168 MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { } 169 170 Fault setIpr(int idx, uint64_t val, ExecContext *xc) { } 171#endif 172 friend class RegFile; 173 }; 174 175 enum MiscRegTags { 176 //Coprocessor 0 Registers 177 //Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 178 //(Register Number-Register Select) Summary of Register 179 //------------------------------------------------------ 180 Index = 0, //0-0 Index into the TLB array 181 182 MVPControl = 1, //0-1 Per-processor register containing global 183 //MIPS� MT configuration data 184 185 MVPConf0 = 2, //0-2 Per-processor register containing global 186 //MIPS� MT configuration data 187 188 MVPConf1 = 3, //0-3 Per-processor register containing global 189 //MIPS� MT configuration data 190 191 Random = 8, //1-0 Randomly generated index into the TLB array 192 193 VPEControl = 9, //1-1 Per-VPE register containing relatively volatile 194 //thread configuration data 195 196 VPEConf0 = 10, //1-2 Per-VPE multi-thread configuration 197 //information 198 199 200 VPEConf1 = 11, //1-2 Per-VPE multi-thread configuration 201 //information 202 203 YQMask = 12, //Per-VPE register defining which YIELD 204 //qualifier bits may be used without generating 205 //an exception 206 207 VPESchedule = 13, 208 VPEScheFBack = 14, 209 VPEOpt = 15, 210 EntryLo0 = 16, // Bank 3: 16 - 23 211 TCStatus = 17, 212 TCBind = 18, 213 TCRestart = 19, 214 TCHalt = 20, 215 TCContext = 21, 216 TCSchedule = 22, 217 TCScheFBack = 23, 218 219 EntryLo1 = 24,// Bank 4: 24 - 31 220 221 Context = 32, // Bank 5: 32 - 39 222 ContextConfig = 33, 223 224 //PageMask = 40, //Bank 6: 40 - 47 225 PageGrain = 41, 226 227 Wired = 48, //Bank 7:48 - 55 228 SRSConf0 = 49, 229 SRSConf1 = 50, 230 SRSConf2 = 51, 231 SRSConf3 = 52, 232 SRSConf4 = 53, 233 BadVAddr = 54, 234 235 HWRena = 56,//Bank 8:56 - 63 236 237 Count = 64, //Bank 9:64 - 71 238 239 EntryHi = 72,//Bank 10:72 - 79 240 241 Compare = 80,//Bank 11:80 - 87 242 243 Status = 88,//Bank 12:88 - 96 //12-0 Processor status and control 244 IntCtl = 89, //12-1 Interrupt system status and control 245 SRSCtl = 90, //12-2 Shadow register set status and control 246 SRSMap = 91, //12-3 Shadow set IPL mapping 247 248 Cause = 97,//97-104 //13-0 Cause of last general exception 249 250 EPC = 105,//105-112 //14-0 Program counter at last exception 251 252 PRId = 113//113-120, //15-0 Processor identification and revision 253 EBase = 114, //15-1 Exception vector base register 254 255 Config = 121,//Bank 16: 121-128 256 Config1 = 122, 257 Config2 = 123, 258 Config3 = 124, 259 Config6 = 127, 260 Config7 = 128, 261 262 263 LLAddr = 129,//Bank 17: 129-136 264 265 WatchLo0 = 137,//Bank 18: 137-144 266 WatchLo1 = 138, 267 WatchLo2 = 139, 268 WatchLo3 = 140, 269 WatchLo4 = 141, 270 WatchLo5 = 142, 271 WatchLo6 = 143, 272 WatchLo7 = 144, 273 274 WatchHi0 = 145,//Bank 19: 145-152 275 WatchHi1 = 146, 276 WatchHi2 = 147, 277 WatchHi3 = 148, 278 WatchHi4 = 149, 279 WatchHi5 = 150, 280 WatchHi6 = 151, 281 WatchHi7 = 152, 282 283 XCContext64 = 153,//Bank 20: 153-160 284 285 //Bank 21: 161-168 286 287 //Bank 22: 169-176 288 289 Debug = 177, //Bank 23: 177-184 290 TraceControl1 = 178, 291 TraceControl2 = 179, 292 UserTraceData = 180, 293 TraceBPC = 181, 294 295 DEPC = 185,//Bank 24: 185-192 296 297 PerfCnt0 = 193,//Bank 25: 193 - 200 298 PerfCnt1 = 194, 299 PerfCnt2 = 195, 300 PerfCnt3 = 196, 301 PerfCnt4 = 197, 302 PerfCnt5 = 198, 303 PerfCnt6 = 199, 304 PerfCnt7 = 200, 305 306 ErrCtl = 201, //Bank 26: 201 - 208 307 308 CacheErr0 = 209, //Bank 27: 209 - 216 309 CacheErr1 = 210, 310 CacheErr2 = 211, 311 CacheErr3 = 212, 312 313 TagLo0 = 217,//Bank 28: 217 - 224 314 DataLo1 = 218, 315 TagLo2 = 219, 316 DataLo3 = 220, 317 TagLo4 = 221, 318 DataLo5 = 222, 319 TagLo6 = 223, 320 DataLo7 = 234, 321 322 TagHi0 = 233,//Bank 29: 233 - 240 323 DataHi1 = 234, 324 TagHi2 = 235, 325 DataHi3 = 236, 326 TagHi4 = 237, 327 DataHi5 = 238, 328 TagHi6 = 239, 329 DataHi7 = 240, 330 331 332 ErrorEPC = 249,//Bank 30: 241 - 248 333 334 DESAVE = 257,//Bank 31: 249-256 335 336 //More Misc. Regs 337 Hi, 338 Lo, 339 FCSR, 340 FPCR, 341 342 //Alpha Regs, but here now, for 343 //compiling sake 344 UNIQ, 345 LockAddr, 346 LockFlag 347 }; 348 349extern const Addr PageShift; 350extern const Addr PageBytes; 351extern const Addr PageMask; 352extern const Addr PageOffset; 353 354#if FULL_SYSTEM 355 356 typedef uint64_t InternalProcReg; 357 358#include "arch/mips/isa_fullsys_traits.hh" 359 360#else 361 enum { 362 NumInternalProcRegs = 0 363 }; 364#endif 365 366 enum { 367 TotalNumRegs = 368 NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs 369 }; 370 371 enum { 372 TotalDataRegs = NumIntRegs + NumFloatRegs 373 }; 374 375 typedef union { 376 IntReg intreg; 377 FloatReg fpreg; 378 MiscReg ctrlreg; 379 } AnyReg; 380 381 struct RegFile { 382 IntRegFile intRegFile; // (signed) integer register file 383 FloatRegFile floatRegFile; // floating point register file 384 MiscRegFile miscRegs; // control register file 385 386 387 Addr pc; // program counter 388 Addr npc; // next-cycle program counter 389 Addr nnpc; // next-next-cycle program counter 390 // used to implement branch delay slot 391 // not real register 392 393 MiscReg hi; // MIPS HI Register 394 MiscReg lo; // MIPS LO Register 395 396 397#if FULL_SYSTEM 398 IntReg palregs[NumIntRegs]; // PAL shadow registers 399 InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs 400 int intrflag; // interrupt flag 401 bool pal_shadow; // using pal_shadow registers 402 inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); } 403 inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); } 404#endif // FULL_SYSTEM 405 406 //void initCP0Regs(); 407 void serialize(std::ostream &os); 408 void unserialize(Checkpoint *cp, const std::string §ion); 409 410 void createCP0Regs(); 411 void coldReset(); 412 }; 413 414 StaticInstPtr decodeInst(MachInst); 415 416 // return a no-op instruction... used for instruction fetch faults 417 extern const MachInst NoopMachInst; 418 419 enum annotes { 420 ANNOTE_NONE = 0, 421 // An impossible number for instruction annotations 422 ITOUCH_ANNOTE = 0xffffffff, 423 }; 424 425 void getMiscRegIdx(int reg_name,int &idx, int &sel); 426 427 428 static inline bool isCallerSaveIntegerRegister(unsigned int reg) { 429 panic("register classification not implemented"); 430 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 431 } 432 433 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 434 panic("register classification not implemented"); 435 return (reg >= 9 && reg <= 15); 436 } 437 438 static inline bool isCallerSaveFloatRegister(unsigned int reg) { 439 panic("register classification not implemented"); 440 return false; 441 } 442 443 static inline bool isCalleeSaveFloatRegister(unsigned int reg) { 444 panic("register classification not implemented"); 445 return false; 446 } 447 448 static inline Addr alignAddress(const Addr &addr, 449 unsigned int nbytes) { 450 return (addr & ~(nbytes - 1)); 451 } 452 453 // Instruction address compression hooks 454 static inline Addr realPCToFetchPC(const Addr &addr) { 455 return addr; 456 } 457 458 static inline Addr fetchPCToRealPC(const Addr &addr) { 459 return addr; 460 } 461 462 // the size of "fetched" instructions (not necessarily the size 463 // of real instructions for PISA) 464 static inline size_t fetchInstSize() { 465 return sizeof(MachInst); 466 } 467 468 static inline MachInst makeRegisterCopy(int dest, int src) { 469 panic("makeRegisterCopy not implemented"); 470 return 0; 471 } 472 473 // Machine operations 474 475 void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 476 int regnum); 477 478 void restoreMachineReg(RegFile ®s, const AnyReg ®, 479 int regnum); 480 481#if 0 482 static void serializeSpecialRegs(const Serializable::Proxy &proxy, 483 const RegFile ®s); 484 485 static void unserializeSpecialRegs(const IniFile *db, 486 const std::string &category, 487 ConfigNode *node, 488 RegFile ®s); 489#endif 490 491 /** 492 * Function to insure ISA semantics about 0 registers. 493 * @param xc The execution context. 494 */ 495 template <class XC> 496 void zeroRegisters(XC *xc); 497 498 const Addr MaxAddr = (Addr)-1; 499}; 500 501#if !FULL_SYSTEM 502class SyscallReturn { 503 public: 504 template <class T> 505 SyscallReturn(T v, bool s) 506 { 507 retval = (uint64_t)v; 508 success = s; 509 } 510 511 template <class T> 512 SyscallReturn(T v) 513 { 514 success = (v >= 0); 515 retval = (uint64_t)v; 516 } 517 518 ~SyscallReturn() {} 519 520 SyscallReturn& operator=(const SyscallReturn& s) { 521 retval = s.retval; 522 success = s.success; 523 return *this; 524 } 525 526 bool successful() { return success; } 527 uint64_t value() { return retval; } 528 529 530 private: 531 uint64_t retval; 532 bool success; 533}; 534 535#endif 536 537 538#if FULL_SYSTEM 539//typedef TheISA::InternalProcReg InternalProcReg; 540//const int NumInternalProcRegs = TheISA::NumInternalProcRegs; 541//const int NumInterruptLevels = TheISA::NumInterruptLevels; 542 543#include "arch/mips/mips34k.hh" 544#endif 545 546#endif // __ARCH_MIPS_ISA_TRAITS_HH__ 547