isa_traits.hh revision 8902
12023SN/A/* 25268Sksewell@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 35254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 45254Sksewell@umich.edu * All rights reserved. 52023SN/A * 65254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 75254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 85254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 95254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 105254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 115254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 125254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 135254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 145254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 155254Sksewell@umich.edu * this software without specific prior written permission. 162023SN/A * 175254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 295254Sksewell@umich.edu * Authors: Gabe Black 305254Sksewell@umich.edu * Korey Sewell 315222Sksewell@umich.edu * Jaidev Patwardhan 322023SN/A */ 332023SN/A 342028SN/A#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 352028SN/A#define __ARCH_MIPS_ISA_TRAITS_HH__ 362023SN/A 372597SN/A#include "arch/mips/types.hh" 386216Snate@binkert.org#include "base/types.hh" 398542Sgblack@eecs.umich.edu#include "cpu/static_inst_fwd.hh" 402023SN/A 417811Ssteve.reinhardt@amd.comnamespace LittleEndianGuest {} 422239SN/A 432131SN/Anamespace MipsISA 442023SN/A{ 452525SN/A 466378Sgblack@eecs.umich.eduusing namespace LittleEndianGuest; 472023SN/A 486378Sgblack@eecs.umich.eduStaticInstPtr decodeInst(ExtMachInst); 493093Sksewell@umich.edu 506378Sgblack@eecs.umich.edu// MIPS DOES have a delay slot 516378Sgblack@eecs.umich.edu#define ISA_HAS_DELAY_SLOT 1 522239SN/A 536378Sgblack@eecs.umich.educonst Addr PageShift = 13; 546378Sgblack@eecs.umich.educonst Addr PageBytes = ULL(1) << PageShift; 556378Sgblack@eecs.umich.educonst Addr Page_Mask = ~(PageBytes - 1); 566378Sgblack@eecs.umich.educonst Addr PageOffset = PageBytes - 1; 575222Sksewell@umich.edu 585222Sksewell@umich.edu 596378Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////////// 606378Sgblack@eecs.umich.edu// 616378Sgblack@eecs.umich.edu// Translation stuff 626378Sgblack@eecs.umich.edu// 635222Sksewell@umich.edu 646378Sgblack@eecs.umich.educonst Addr PteShift = 3; 656378Sgblack@eecs.umich.educonst Addr NPtePageShift = PageShift - PteShift; 666378Sgblack@eecs.umich.educonst Addr NPtePage = ULL(1) << NPtePageShift; 676378Sgblack@eecs.umich.educonst Addr PteMask = NPtePage - 1; 685222Sksewell@umich.edu 696378Sgblack@eecs.umich.edu//// All 'Mapped' segments go through the TLB 706378Sgblack@eecs.umich.edu//// All other segments are translated by dropping the MSB, to give 716378Sgblack@eecs.umich.edu//// the corresponding physical address 726378Sgblack@eecs.umich.edu// User Segment - Mapped 736378Sgblack@eecs.umich.educonst Addr USegBase = ULL(0x0); 746378Sgblack@eecs.umich.educonst Addr USegEnd = ULL(0x7FFFFFFF); 755222Sksewell@umich.edu 766378Sgblack@eecs.umich.edu// Kernel Segment 0 - Unmapped 776378Sgblack@eecs.umich.educonst Addr KSeg0End = ULL(0x9FFFFFFF); 786378Sgblack@eecs.umich.educonst Addr KSeg0Base = ULL(0x80000000); 796378Sgblack@eecs.umich.educonst Addr KSeg0Mask = ULL(0x1FFFFFFF); 805222Sksewell@umich.edu 816378Sgblack@eecs.umich.edu// Kernel Segment 1 - Unmapped, Uncached 826378Sgblack@eecs.umich.educonst Addr KSeg1End = ULL(0xBFFFFFFF); 836378Sgblack@eecs.umich.educonst Addr KSeg1Base = ULL(0xA0000000); 846378Sgblack@eecs.umich.educonst Addr KSeg1Mask = ULL(0x1FFFFFFF); 855222Sksewell@umich.edu 866378Sgblack@eecs.umich.edu// Kernel/Supervisor Segment - Mapped 876378Sgblack@eecs.umich.educonst Addr KSSegEnd = ULL(0xDFFFFFFF); 886378Sgblack@eecs.umich.educonst Addr KSSegBase = ULL(0xC0000000); 895222Sksewell@umich.edu 906378Sgblack@eecs.umich.edu// Kernel Segment 3 - Mapped 916378Sgblack@eecs.umich.educonst Addr KSeg3End = ULL(0xFFFFFFFF); 926378Sgblack@eecs.umich.educonst Addr KSeg3Base = ULL(0xE0000000); 935222Sksewell@umich.edu 945222Sksewell@umich.edu 956378Sgblack@eecs.umich.eduinline Addr Phys2K0Seg(Addr addr) 966378Sgblack@eecs.umich.edu{ 976378Sgblack@eecs.umich.edu return addr | KSeg0Base; 986378Sgblack@eecs.umich.edu} 995254Sksewell@umich.edu 1005254Sksewell@umich.edu 1016378Sgblack@eecs.umich.educonst unsigned VABits = 32; 1026378Sgblack@eecs.umich.educonst unsigned PABits = 32; // Is this correct? 1036378Sgblack@eecs.umich.educonst Addr VAddrImplMask = (ULL(1) << VABits) - 1; 1046378Sgblack@eecs.umich.educonst Addr VAddrUnImplMask = ~VAddrImplMask; 1056378Sgblack@eecs.umich.eduinline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 1066378Sgblack@eecs.umich.eduinline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; } 1076378Sgblack@eecs.umich.eduinline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; } 1085254Sksewell@umich.edu 1096378Sgblack@eecs.umich.educonst Addr PAddrImplMask = (ULL(1) << PABits) - 1; 1105222Sksewell@umich.edu 1116378Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////////// 1126378Sgblack@eecs.umich.edu// 1136378Sgblack@eecs.umich.edu// Interrupt levels 1146378Sgblack@eecs.umich.edu// 1156378Sgblack@eecs.umich.eduenum InterruptLevels 1166378Sgblack@eecs.umich.edu{ 1176378Sgblack@eecs.umich.edu INTLEVEL_SOFTWARE_MIN = 4, 1186378Sgblack@eecs.umich.edu INTLEVEL_SOFTWARE_MAX = 19, 1195222Sksewell@umich.edu 1206378Sgblack@eecs.umich.edu INTLEVEL_EXTERNAL_MIN = 20, 1216378Sgblack@eecs.umich.edu INTLEVEL_EXTERNAL_MAX = 34, 1225222Sksewell@umich.edu 1236378Sgblack@eecs.umich.edu INTLEVEL_IRQ0 = 20, 1246378Sgblack@eecs.umich.edu INTLEVEL_IRQ1 = 21, 1256378Sgblack@eecs.umich.edu INTINDEX_ETHERNET = 0, 1266378Sgblack@eecs.umich.edu INTINDEX_SCSI = 1, 1276378Sgblack@eecs.umich.edu INTLEVEL_IRQ2 = 22, 1286378Sgblack@eecs.umich.edu INTLEVEL_IRQ3 = 23, 1295222Sksewell@umich.edu 1306378Sgblack@eecs.umich.edu INTLEVEL_SERIAL = 33, 1315222Sksewell@umich.edu 1326378Sgblack@eecs.umich.edu NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 1336378Sgblack@eecs.umich.edu}; 1345222Sksewell@umich.edu 1356378Sgblack@eecs.umich.edu// MIPS modes 1366378Sgblack@eecs.umich.eduenum mode_type 1376378Sgblack@eecs.umich.edu{ 1386378Sgblack@eecs.umich.edu mode_kernel = 0, // kernel 1396378Sgblack@eecs.umich.edu mode_supervisor = 1, // supervisor 1406378Sgblack@eecs.umich.edu mode_user = 2, // user mode 1416378Sgblack@eecs.umich.edu mode_debug = 3, // debug mode 1426378Sgblack@eecs.umich.edu mode_number // number of modes 1436378Sgblack@eecs.umich.edu}; 1442131SN/A 1456378Sgblack@eecs.umich.edu// return a no-op instruction... used for instruction fetch faults 1466378Sgblack@eecs.umich.educonst ExtMachInst NoopMachInst = 0x00000000; 1472131SN/A 1486378Sgblack@eecs.umich.educonst int LogVMPageSize = 13; // 8K bytes 1496378Sgblack@eecs.umich.educonst int VMPageSize = (1 << LogVMPageSize); 1502131SN/A 1516378Sgblack@eecs.umich.educonst int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 1522131SN/A 1536378Sgblack@eecs.umich.educonst int MachineBytes = 4; 1546378Sgblack@eecs.umich.educonst int WordBytes = 4; 1556378Sgblack@eecs.umich.educonst int HalfwordBytes = 2; 1566378Sgblack@eecs.umich.educonst int ByteBytes = 1; 1576378Sgblack@eecs.umich.edu 1586378Sgblack@eecs.umich.educonst int ANNOTE_NONE = 0; 1596378Sgblack@eecs.umich.educonst uint32_t ITOUCH_ANNOTE = 0xffffffff; 1606378Sgblack@eecs.umich.edu 1618412Sksewell@umich.educonst bool HasUnalignedMemAcc = true; 1626974Stjones1@inf.ed.ac.uk 1637811Ssteve.reinhardt@amd.com} // namespace MipsISA 1642023SN/A 1652028SN/A#endif // __ARCH_MIPS_ISA_TRAITS_HH__ 166