isa_traits.hh revision 5569
12023SN/A/* 25268Sksewell@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 35254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 45254Sksewell@umich.edu * All rights reserved. 52023SN/A * 65254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 75254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 85254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 95254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 105254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 115254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 125254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 135254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 145254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 155254Sksewell@umich.edu * this software without specific prior written permission. 162023SN/A * 175254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 295254Sksewell@umich.edu * Authors: Gabe Black 305254Sksewell@umich.edu * Korey Sewell 315222Sksewell@umich.edu * Jaidev Patwardhan 322023SN/A */ 332023SN/A 342028SN/A#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 352028SN/A#define __ARCH_MIPS_ISA_TRAITS_HH__ 362023SN/A 372597SN/A#include "arch/mips/types.hh" 385254Sksewell@umich.edu#include "arch/mips/mips_core_specific.hh" 395222Sksewell@umich.edu#include "config/full_system.hh" 402023SN/A#include "sim/host.hh" 412023SN/A 422239SN/Anamespace LittleEndianGuest {}; 432239SN/A 442028SN/A#define TARGET_MIPS 452023SN/A 462131SN/Aclass StaticInstPtr; 472023SN/A 482131SN/Anamespace MipsISA 492023SN/A{ 502525SN/A using namespace LittleEndianGuest; 512525SN/A 522447SN/A StaticInstPtr decodeInst(ExtMachInst); 532023SN/A 545222Sksewell@umich.edu // MIPS DOES have a delay slot 553093Sksewell@umich.edu #define ISA_HAS_DELAY_SLOT 1 563093Sksewell@umich.edu 572972Sgblack@eecs.umich.edu const Addr PageShift = 13; 582972Sgblack@eecs.umich.edu const Addr PageBytes = ULL(1) << PageShift; 595222Sksewell@umich.edu const Addr Page_Mask = ~(PageBytes - 1); 602972Sgblack@eecs.umich.edu const Addr PageOffset = PageBytes - 1; 612239SN/A 625222Sksewell@umich.edu 635222Sksewell@umich.edu //////////////////////////////////////////////////////////////////////// 645222Sksewell@umich.edu // 655222Sksewell@umich.edu // Translation stuff 665222Sksewell@umich.edu // 675222Sksewell@umich.edu 685222Sksewell@umich.edu const Addr PteShift = 3; 695222Sksewell@umich.edu const Addr NPtePageShift = PageShift - PteShift; 705222Sksewell@umich.edu const Addr NPtePage = ULL(1) << NPtePageShift; 715222Sksewell@umich.edu const Addr PteMask = NPtePage - 1; 725222Sksewell@umich.edu 735222Sksewell@umich.edu //// All 'Mapped' segments go through the TLB 745222Sksewell@umich.edu //// All other segments are translated by dropping the MSB, to give 755222Sksewell@umich.edu //// the corresponding physical address 765222Sksewell@umich.edu // User Segment - Mapped 775222Sksewell@umich.edu const Addr USegBase = ULL(0x0); 785222Sksewell@umich.edu const Addr USegEnd = ULL(0x7FFFFFFF); 795222Sksewell@umich.edu 805222Sksewell@umich.edu // Kernel Segment 0 - Unmapped 815222Sksewell@umich.edu const Addr KSeg0End = ULL(0x9FFFFFFF); 825222Sksewell@umich.edu const Addr KSeg0Base = ULL(0x80000000); 835222Sksewell@umich.edu const Addr KSeg0Mask = ULL(0x1FFFFFFF); 845222Sksewell@umich.edu 855222Sksewell@umich.edu // Kernel Segment 1 - Unmapped, Uncached 865222Sksewell@umich.edu const Addr KSeg1End = ULL(0xBFFFFFFF); 875222Sksewell@umich.edu const Addr KSeg1Base = ULL(0xA0000000); 885222Sksewell@umich.edu const Addr KSeg1Mask = ULL(0x1FFFFFFF); 895222Sksewell@umich.edu 905222Sksewell@umich.edu // Kernel/Supervisor Segment - Mapped 915222Sksewell@umich.edu const Addr KSSegEnd = ULL(0xDFFFFFFF); 925222Sksewell@umich.edu const Addr KSSegBase = ULL(0xC0000000); 935222Sksewell@umich.edu 945222Sksewell@umich.edu // Kernel Segment 3 - Mapped 955222Sksewell@umich.edu const Addr KSeg3End = ULL(0xFFFFFFFF); 965222Sksewell@umich.edu const Addr KSeg3Base = ULL(0xE0000000); 975222Sksewell@umich.edu 985222Sksewell@umich.edu 995222Sksewell@umich.edu // For loading... XXX This maybe could be USegEnd?? --ali 1005222Sksewell@umich.edu const Addr LoadAddrMask = ULL(0xffffffffff); 1015222Sksewell@umich.edu 1025222Sksewell@umich.edu inline Addr Phys2K0Seg(Addr addr) 1035222Sksewell@umich.edu { 1045222Sksewell@umich.edu // if (addr & PAddrUncachedBit43) { 1055222Sksewell@umich.edu// addr &= PAddrUncachedMask; 1065222Sksewell@umich.edu// addr |= PAddrUncachedBit40; 1075222Sksewell@umich.edu// } 1085222Sksewell@umich.edu return addr | KSeg0Base; 1095222Sksewell@umich.edu } 1105222Sksewell@umich.edu 1115254Sksewell@umich.edu 1125254Sksewell@umich.edu const unsigned VABits = 32; 1135254Sksewell@umich.edu const unsigned PABits = 32; // Is this correct? 1145254Sksewell@umich.edu const Addr VAddrImplMask = (ULL(1) << VABits) - 1; 1155254Sksewell@umich.edu const Addr VAddrUnImplMask = ~VAddrImplMask; 1165254Sksewell@umich.edu inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } 1175254Sksewell@umich.edu inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; } 1185254Sksewell@umich.edu inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; } 1195254Sksewell@umich.edu 1205254Sksewell@umich.edu const Addr PAddrImplMask = (ULL(1) << PABits) - 1; 1215254Sksewell@umich.edu 1225222Sksewell@umich.edu //////////////////////////////////////////////////////////////////////// 1235222Sksewell@umich.edu // 1245222Sksewell@umich.edu // Interrupt levels 1255222Sksewell@umich.edu // 1265222Sksewell@umich.edu enum InterruptLevels 1275222Sksewell@umich.edu { 1285222Sksewell@umich.edu INTLEVEL_SOFTWARE_MIN = 4, 1295222Sksewell@umich.edu INTLEVEL_SOFTWARE_MAX = 19, 1305222Sksewell@umich.edu 1315222Sksewell@umich.edu INTLEVEL_EXTERNAL_MIN = 20, 1325222Sksewell@umich.edu INTLEVEL_EXTERNAL_MAX = 34, 1335222Sksewell@umich.edu 1345222Sksewell@umich.edu INTLEVEL_IRQ0 = 20, 1355222Sksewell@umich.edu INTLEVEL_IRQ1 = 21, 1365222Sksewell@umich.edu INTINDEX_ETHERNET = 0, 1375222Sksewell@umich.edu INTINDEX_SCSI = 1, 1385222Sksewell@umich.edu INTLEVEL_IRQ2 = 22, 1395222Sksewell@umich.edu INTLEVEL_IRQ3 = 23, 1405222Sksewell@umich.edu 1415222Sksewell@umich.edu INTLEVEL_SERIAL = 33, 1425222Sksewell@umich.edu 1435222Sksewell@umich.edu NumInterruptLevels = INTLEVEL_EXTERNAL_MAX 1445222Sksewell@umich.edu }; 1455222Sksewell@umich.edu 1465222Sksewell@umich.edu 1475222Sksewell@umich.edu // MIPS modes 1485222Sksewell@umich.edu enum mode_type 1495222Sksewell@umich.edu { 1505543Ssaidi@eecs.umich.edu mode_kernel = 0, // kernel 1515543Ssaidi@eecs.umich.edu mode_supervisor = 1, // supervisor 1525543Ssaidi@eecs.umich.edu mode_user = 2, // user mode 1535222Sksewell@umich.edu mode_debug = 3, // debug mode 1545543Ssaidi@eecs.umich.edu mode_number // number of modes 1555222Sksewell@umich.edu }; 1565222Sksewell@umich.edu 1575222Sksewell@umich.edu inline mode_type getOperatingMode(MiscReg Stat) 1585222Sksewell@umich.edu { 1595222Sksewell@umich.edu if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0) 1605222Sksewell@umich.edu return mode_kernel; 1615222Sksewell@umich.edu else{ 1625222Sksewell@umich.edu if((Stat & 0x18) == 0x8) 1635222Sksewell@umich.edu return mode_supervisor; 1645222Sksewell@umich.edu else if((Stat & 0x18) == 0x10) 1655222Sksewell@umich.edu return mode_user; 1665222Sksewell@umich.edu else return mode_number; 1675222Sksewell@umich.edu } 1685222Sksewell@umich.edu } 1695222Sksewell@umich.edu 1705222Sksewell@umich.edu 1712972Sgblack@eecs.umich.edu // return a no-op instruction... used for instruction fetch faults 1722972Sgblack@eecs.umich.edu const ExtMachInst NoopMachInst = 0x00000000; 1732131SN/A 1742972Sgblack@eecs.umich.edu // Constants Related to the number of registers 1752972Sgblack@eecs.umich.edu const int NumIntArchRegs = 32; 1764661Sksewell@umich.edu const int NumIntSpecialRegs = 9; 1772972Sgblack@eecs.umich.edu const int NumFloatArchRegs = 32; 1782972Sgblack@eecs.umich.edu const int NumFloatSpecialRegs = 5; 1792597SN/A 1805222Sksewell@umich.edu const int NumShadowRegSets = 16; // Maximum number of shadow register sets 1815222Sksewell@umich.edu const int NumIntRegs = NumIntArchRegs*NumShadowRegSets + NumIntSpecialRegs; //HI & LO Regs 1825222Sksewell@umich.edu const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// 1835222Sksewell@umich.edu 1844772Sgblack@eecs.umich.edu // Static instruction parameters 1855222Sksewell@umich.edu const int MaxInstSrcRegs = 10; 1865222Sksewell@umich.edu const int MaxInstDestRegs = 8; 1874772Sgblack@eecs.umich.edu 1882972Sgblack@eecs.umich.edu // semantically meaningful register indices 1892972Sgblack@eecs.umich.edu const int ZeroReg = 0; 1902972Sgblack@eecs.umich.edu const int AssemblerReg = 1; 1912972Sgblack@eecs.umich.edu const int ReturnValueReg = 2; 1922972Sgblack@eecs.umich.edu const int ReturnValueReg1 = 2; 1932972Sgblack@eecs.umich.edu const int ReturnValueReg2 = 3; 1945222Sksewell@umich.edu const int ArgumentReg0 = 4; 1955222Sksewell@umich.edu const int ArgumentReg1 = 5; 1965222Sksewell@umich.edu const int ArgumentReg2 = 6; 1975222Sksewell@umich.edu const int ArgumentReg3 = 7; 1982972Sgblack@eecs.umich.edu const int KernelReg0 = 26; 1992972Sgblack@eecs.umich.edu const int KernelReg1 = 27; 2002972Sgblack@eecs.umich.edu const int GlobalPointerReg = 28; 2012972Sgblack@eecs.umich.edu const int StackPointerReg = 29; 2022972Sgblack@eecs.umich.edu const int FramePointerReg = 30; 2032972Sgblack@eecs.umich.edu const int ReturnAddressReg = 31; 2042597SN/A 2055222Sksewell@umich.edu const int ArgumentReg[] = {4, 5, 6, 7}; 2065222Sksewell@umich.edu const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); 2075222Sksewell@umich.edu 2082972Sgblack@eecs.umich.edu const int SyscallNumReg = ReturnValueReg1; 2094661Sksewell@umich.edu const int SyscallPseudoReturnReg = ReturnValueReg2; 2105222Sksewell@umich.edu const int SyscallSuccessReg = ArgumentReg3; 2112131SN/A 2125543Ssaidi@eecs.umich.edu const int LogVMPageSize = 13; // 8K bytes 2132972Sgblack@eecs.umich.edu const int VMPageSize = (1 << LogVMPageSize); 2142131SN/A 2152972Sgblack@eecs.umich.edu const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 2162131SN/A 2172972Sgblack@eecs.umich.edu const int MachineBytes = 4; 2182972Sgblack@eecs.umich.edu const int WordBytes = 4; 2192972Sgblack@eecs.umich.edu const int HalfwordBytes = 2; 2202972Sgblack@eecs.umich.edu const int ByteBytes = 1; 2212131SN/A 2222972Sgblack@eecs.umich.edu const int ANNOTE_NONE = 0; 2232972Sgblack@eecs.umich.edu const uint32_t ITOUCH_ANNOTE = 0xffffffff; 2242131SN/A 2255222Sksewell@umich.edu // These help enumerate all the registers for dependence tracking. 2265222Sksewell@umich.edu const int FP_Base_DepTag = NumIntRegs; 2275222Sksewell@umich.edu const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; 2285222Sksewell@umich.edu 2294661Sksewell@umich.edu // Enumerate names for 'Control' Registers in the CPU 2304661Sksewell@umich.edu // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 2314661Sksewell@umich.edu // (Register Number-Register Select) Summary of Register 2324661Sksewell@umich.edu //------------------------------------------------------ 2334661Sksewell@umich.edu // The first set of names classify the CP0 names as Register Banks 2344661Sksewell@umich.edu // for easy indexing when using the 'RD + SEL' index combination 2354661Sksewell@umich.edu // in CP0 instructions. 2364661Sksewell@umich.edu enum MiscRegTags { 2375222Sksewell@umich.edu Index = Ctrl_Base_DepTag + 0, //Bank 0: 0 - 3 2384661Sksewell@umich.edu MVPControl, 2394661Sksewell@umich.edu MVPConf0, 2404661Sksewell@umich.edu MVPConf1, 2414661Sksewell@umich.edu 2425222Sksewell@umich.edu CP0_Random = Ctrl_Base_DepTag + 8, //Bank 1: 8 - 15 2434661Sksewell@umich.edu VPEControl, 2444661Sksewell@umich.edu VPEConf0, 2454661Sksewell@umich.edu VPEConf1, 2464661Sksewell@umich.edu YQMask, 2474661Sksewell@umich.edu VPESchedule, 2484661Sksewell@umich.edu VPEScheFBack, 2494661Sksewell@umich.edu VPEOpt, 2504661Sksewell@umich.edu 2515222Sksewell@umich.edu EntryLo0 = Ctrl_Base_DepTag + 16, //Bank 2: 16 - 23 2524661Sksewell@umich.edu TCStatus, 2534661Sksewell@umich.edu TCBind, 2544661Sksewell@umich.edu TCRestart, 2554661Sksewell@umich.edu TCHalt, 2564661Sksewell@umich.edu TCContext, 2574661Sksewell@umich.edu TCSchedule, 2584661Sksewell@umich.edu TCScheFBack, 2594661Sksewell@umich.edu 2605222Sksewell@umich.edu EntryLo1 = Ctrl_Base_DepTag + 24, // Bank 3: 24 2614661Sksewell@umich.edu 2625222Sksewell@umich.edu Context = Ctrl_Base_DepTag + 32, // Bank 4: 32 - 33 2634661Sksewell@umich.edu ContextConfig, 2644661Sksewell@umich.edu 2655222Sksewell@umich.edu PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41 2665222Sksewell@umich.edu PageGrain = Ctrl_Base_DepTag + 41, 2674661Sksewell@umich.edu 2685222Sksewell@umich.edu Wired = Ctrl_Base_DepTag + 48, //Bank 6:48-55 2694661Sksewell@umich.edu SRSConf0, 2704661Sksewell@umich.edu SRSConf1, 2714661Sksewell@umich.edu SRSConf2, 2724661Sksewell@umich.edu SRSConf3, 2734661Sksewell@umich.edu SRSConf4, 2744661Sksewell@umich.edu 2755222Sksewell@umich.edu HWRena = Ctrl_Base_DepTag + 56, //Bank 7: 56-63 2764661Sksewell@umich.edu 2775222Sksewell@umich.edu BadVAddr = Ctrl_Base_DepTag + 64, //Bank 8: 64-71 2784661Sksewell@umich.edu 2795222Sksewell@umich.edu Count = Ctrl_Base_DepTag + 72, //Bank 9: 72-79 2804661Sksewell@umich.edu 2815222Sksewell@umich.edu EntryHi = Ctrl_Base_DepTag + 80, //Bank 10: 80-87 2824661Sksewell@umich.edu 2835222Sksewell@umich.edu Compare = Ctrl_Base_DepTag + 88, //Bank 11: 88-95 2844661Sksewell@umich.edu 2855222Sksewell@umich.edu Status = Ctrl_Base_DepTag + 96, //Bank 12: 96-103 2864661Sksewell@umich.edu IntCtl, 2874661Sksewell@umich.edu SRSCtl, 2884661Sksewell@umich.edu SRSMap, 2894661Sksewell@umich.edu 2905222Sksewell@umich.edu Cause = Ctrl_Base_DepTag + 104, //Bank 13: 104-111 2914661Sksewell@umich.edu 2925222Sksewell@umich.edu EPC = Ctrl_Base_DepTag + 112, //Bank 14: 112-119 2934661Sksewell@umich.edu 2945222Sksewell@umich.edu PRId = Ctrl_Base_DepTag + 120, //Bank 15: 120-127, 2954661Sksewell@umich.edu EBase, 2964661Sksewell@umich.edu 2975222Sksewell@umich.edu Config = Ctrl_Base_DepTag + 128, //Bank 16: 128-135 2984661Sksewell@umich.edu Config1, 2994661Sksewell@umich.edu Config2, 3004661Sksewell@umich.edu Config3, 3014661Sksewell@umich.edu Config4, 3024661Sksewell@umich.edu Config5, 3034661Sksewell@umich.edu Config6, 3044661Sksewell@umich.edu Config7, 3054661Sksewell@umich.edu 3064661Sksewell@umich.edu 3075222Sksewell@umich.edu LLAddr = Ctrl_Base_DepTag + 136, //Bank 17: 136-143 3084661Sksewell@umich.edu 3095222Sksewell@umich.edu WatchLo0 = Ctrl_Base_DepTag + 144, //Bank 18: 144-151 3104661Sksewell@umich.edu WatchLo1, 3114661Sksewell@umich.edu WatchLo2, 3124661Sksewell@umich.edu WatchLo3, 3134661Sksewell@umich.edu WatchLo4, 3144661Sksewell@umich.edu WatchLo5, 3154661Sksewell@umich.edu WatchLo6, 3164661Sksewell@umich.edu WatchLo7, 3174661Sksewell@umich.edu 3185222Sksewell@umich.edu WatchHi0 = Ctrl_Base_DepTag + 152, //Bank 19: 152-159 3194661Sksewell@umich.edu WatchHi1, 3204661Sksewell@umich.edu WatchHi2, 3214661Sksewell@umich.edu WatchHi3, 3224661Sksewell@umich.edu WatchHi4, 3234661Sksewell@umich.edu WatchHi5, 3244661Sksewell@umich.edu WatchHi6, 3254661Sksewell@umich.edu WatchHi7, 3264661Sksewell@umich.edu 3275222Sksewell@umich.edu XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167 3284661Sksewell@umich.edu 3294661Sksewell@umich.edu //Bank 21: 168-175 3304661Sksewell@umich.edu 3314661Sksewell@umich.edu //Bank 22: 176-183 3324661Sksewell@umich.edu 3335222Sksewell@umich.edu Debug = Ctrl_Base_DepTag + 184, //Bank 23: 184-191 3344661Sksewell@umich.edu TraceControl1, 3354661Sksewell@umich.edu TraceControl2, 3364661Sksewell@umich.edu UserTraceData, 3374661Sksewell@umich.edu TraceBPC, 3384661Sksewell@umich.edu 3395222Sksewell@umich.edu DEPC = Ctrl_Base_DepTag + 192, //Bank 24: 192-199 3404661Sksewell@umich.edu 3415222Sksewell@umich.edu PerfCnt0 = Ctrl_Base_DepTag + 200, //Bank 25: 200-207 3424661Sksewell@umich.edu PerfCnt1, 3434661Sksewell@umich.edu PerfCnt2, 3444661Sksewell@umich.edu PerfCnt3, 3454661Sksewell@umich.edu PerfCnt4, 3464661Sksewell@umich.edu PerfCnt5, 3474661Sksewell@umich.edu PerfCnt6, 3484661Sksewell@umich.edu PerfCnt7, 3494661Sksewell@umich.edu 3505222Sksewell@umich.edu ErrCtl = Ctrl_Base_DepTag + 208, //Bank 26: 208-215 3514661Sksewell@umich.edu 3525222Sksewell@umich.edu CacheErr0 = Ctrl_Base_DepTag + 216, //Bank 27: 216-223 3534661Sksewell@umich.edu CacheErr1, 3544661Sksewell@umich.edu CacheErr2, 3554661Sksewell@umich.edu CacheErr3, 3564661Sksewell@umich.edu 3575222Sksewell@umich.edu TagLo0 = Ctrl_Base_DepTag + 224, //Bank 28: 224-231 3584661Sksewell@umich.edu DataLo1, 3594661Sksewell@umich.edu TagLo2, 3604661Sksewell@umich.edu DataLo3, 3614661Sksewell@umich.edu TagLo4, 3624661Sksewell@umich.edu DataLo5, 3634661Sksewell@umich.edu TagLo6, 3644661Sksewell@umich.edu DataLo7, 3654661Sksewell@umich.edu 3665222Sksewell@umich.edu TagHi0 = Ctrl_Base_DepTag + 232, //Bank 29: 232-239 3674661Sksewell@umich.edu DataHi1, 3684661Sksewell@umich.edu TagHi2, 3694661Sksewell@umich.edu DataHi3, 3704661Sksewell@umich.edu TagHi4, 3714661Sksewell@umich.edu DataHi5, 3724661Sksewell@umich.edu TagHi6, 3734661Sksewell@umich.edu DataHi7, 3744661Sksewell@umich.edu 3754661Sksewell@umich.edu 3765222Sksewell@umich.edu ErrorEPC = Ctrl_Base_DepTag + 240, //Bank 30: 240-247 3774661Sksewell@umich.edu 3785222Sksewell@umich.edu DESAVE = Ctrl_Base_DepTag + 248, //Bank 31: 248-256 3794661Sksewell@umich.edu 3805222Sksewell@umich.edu LLFlag = Ctrl_Base_DepTag + 257, 3814661Sksewell@umich.edu 3824661Sksewell@umich.edu NumControlRegs 3834661Sksewell@umich.edu }; 3844661Sksewell@umich.edu 3855222Sksewell@umich.edu const int TotalDataRegs = NumIntRegs + NumFloatRegs; 3865222Sksewell@umich.edu 3874661Sksewell@umich.edu const int NumMiscRegs = NumControlRegs; 3884661Sksewell@umich.edu 3894661Sksewell@umich.edu const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 3904661Sksewell@umich.edu 3914661Sksewell@umich.edu 3922023SN/A}; 3932023SN/A 3942447SN/Ausing namespace MipsISA; 3952447SN/A 3962028SN/A#endif // __ARCH_MIPS_ISA_TRAITS_HH__ 397