isa_traits.hh revision 5228
12023SN/A/* 22023SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32023SN/A * All rights reserved. 42023SN/A * 52023SN/A * Redistribution and use in source and binary forms, with or without 62023SN/A * modification, are permitted provided that the following conditions are 72023SN/A * met: redistributions of source code must retain the above copyright 82023SN/A * notice, this list of conditions and the following disclaimer; 92023SN/A * redistributions in binary form must reproduce the above copyright 102023SN/A * notice, this list of conditions and the following disclaimer in the 112023SN/A * documentation and/or other materials provided with the distribution; 122023SN/A * neither the name of the copyright holders nor the names of its 132023SN/A * contributors may be used to endorse or promote products derived from 142023SN/A * this software without specific prior written permission. 152023SN/A * 162023SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172023SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182023SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192023SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202023SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212023SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222023SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232023SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242023SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252023SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262023SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Korey Sewell 302023SN/A */ 312023SN/A 322028SN/A#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 332028SN/A#define __ARCH_MIPS_ISA_TRAITS_HH__ 342023SN/A 355228Sgblack@eecs.umich.edu#include "arch/mips/max_inst_regs.hh" 362597SN/A#include "arch/mips/types.hh" 372023SN/A#include "sim/host.hh" 382023SN/A 392239SN/Anamespace LittleEndianGuest {}; 402239SN/A 412028SN/A#define TARGET_MIPS 422023SN/A 432131SN/Aclass StaticInstPtr; 442023SN/A 452131SN/Anamespace MipsISA 462023SN/A{ 472525SN/A using namespace LittleEndianGuest; 485228Sgblack@eecs.umich.edu using MipsISAInst::MaxInstSrcRegs; 495228Sgblack@eecs.umich.edu using MipsISAInst::MaxInstDestRegs; 502525SN/A 512447SN/A StaticInstPtr decodeInst(ExtMachInst); 522023SN/A 533093Sksewell@umich.edu // MIPS DOES a delay slot 543093Sksewell@umich.edu #define ISA_HAS_DELAY_SLOT 1 553093Sksewell@umich.edu 562972Sgblack@eecs.umich.edu const Addr PageShift = 13; 572972Sgblack@eecs.umich.edu const Addr PageBytes = ULL(1) << PageShift; 582972Sgblack@eecs.umich.edu const Addr PageMask = ~(PageBytes - 1); 592972Sgblack@eecs.umich.edu const Addr PageOffset = PageBytes - 1; 602239SN/A 612972Sgblack@eecs.umich.edu // return a no-op instruction... used for instruction fetch faults 622972Sgblack@eecs.umich.edu const ExtMachInst NoopMachInst = 0x00000000; 632131SN/A 642972Sgblack@eecs.umich.edu // Constants Related to the number of registers 652972Sgblack@eecs.umich.edu const int NumIntArchRegs = 32; 664661Sksewell@umich.edu const int NumIntSpecialRegs = 9; 672972Sgblack@eecs.umich.edu const int NumFloatArchRegs = 32; 682972Sgblack@eecs.umich.edu const int NumFloatSpecialRegs = 5; 692597SN/A 702972Sgblack@eecs.umich.edu // semantically meaningful register indices 712972Sgblack@eecs.umich.edu const int ZeroReg = 0; 722972Sgblack@eecs.umich.edu const int AssemblerReg = 1; 732972Sgblack@eecs.umich.edu const int ReturnValueReg = 2; 742972Sgblack@eecs.umich.edu const int ReturnValueReg1 = 2; 752972Sgblack@eecs.umich.edu const int ReturnValueReg2 = 3; 764772Sgblack@eecs.umich.edu 774772Sgblack@eecs.umich.edu const int ArgumentReg[] = {4, 5, 6, 7}; 784772Sgblack@eecs.umich.edu const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); 794772Sgblack@eecs.umich.edu 802972Sgblack@eecs.umich.edu const int KernelReg0 = 26; 812972Sgblack@eecs.umich.edu const int KernelReg1 = 27; 822972Sgblack@eecs.umich.edu const int GlobalPointerReg = 28; 832972Sgblack@eecs.umich.edu const int StackPointerReg = 29; 842972Sgblack@eecs.umich.edu const int FramePointerReg = 30; 852972Sgblack@eecs.umich.edu const int ReturnAddressReg = 31; 862597SN/A 872972Sgblack@eecs.umich.edu const int SyscallNumReg = ReturnValueReg1; 884661Sksewell@umich.edu const int SyscallPseudoReturnReg = ReturnValueReg2; 894772Sgblack@eecs.umich.edu const int SyscallSuccessReg = ArgumentReg[3]; 902131SN/A 912972Sgblack@eecs.umich.edu const int LogVMPageSize = 13; // 8K bytes 922972Sgblack@eecs.umich.edu const int VMPageSize = (1 << LogVMPageSize); 932131SN/A 942972Sgblack@eecs.umich.edu const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 952131SN/A 962972Sgblack@eecs.umich.edu const int MachineBytes = 4; 972972Sgblack@eecs.umich.edu const int WordBytes = 4; 982972Sgblack@eecs.umich.edu const int HalfwordBytes = 2; 992972Sgblack@eecs.umich.edu const int ByteBytes = 1; 1002131SN/A 1012972Sgblack@eecs.umich.edu const int ANNOTE_NONE = 0; 1022972Sgblack@eecs.umich.edu const uint32_t ITOUCH_ANNOTE = 0xffffffff; 1032131SN/A 1044661Sksewell@umich.edu // Enumerate names for 'Control' Registers in the CPU 1054661Sksewell@umich.edu // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 1064661Sksewell@umich.edu // (Register Number-Register Select) Summary of Register 1074661Sksewell@umich.edu //------------------------------------------------------ 1084661Sksewell@umich.edu // The first set of names classify the CP0 names as Register Banks 1094661Sksewell@umich.edu // for easy indexing when using the 'RD + SEL' index combination 1104661Sksewell@umich.edu // in CP0 instructions. 1114661Sksewell@umich.edu enum MiscRegTags { 1124661Sksewell@umich.edu Index = 0, //Bank 0: 0 - 3 1134661Sksewell@umich.edu MVPControl, 1144661Sksewell@umich.edu MVPConf0, 1154661Sksewell@umich.edu MVPConf1, 1164661Sksewell@umich.edu 1174661Sksewell@umich.edu Random = 8, //Bank 1: 8 - 15 1184661Sksewell@umich.edu VPEControl, 1194661Sksewell@umich.edu VPEConf0, 1204661Sksewell@umich.edu VPEConf1, 1214661Sksewell@umich.edu YQMask, 1224661Sksewell@umich.edu VPESchedule, 1234661Sksewell@umich.edu VPEScheFBack, 1244661Sksewell@umich.edu VPEOpt, 1254661Sksewell@umich.edu 1264661Sksewell@umich.edu EntryLo0 = 16, //Bank 2: 16 - 23 1274661Sksewell@umich.edu TCStatus, 1284661Sksewell@umich.edu TCBind, 1294661Sksewell@umich.edu TCRestart, 1304661Sksewell@umich.edu TCHalt, 1314661Sksewell@umich.edu TCContext, 1324661Sksewell@umich.edu TCSchedule, 1334661Sksewell@umich.edu TCScheFBack, 1344661Sksewell@umich.edu 1354661Sksewell@umich.edu EntryLo1 = 24, // Bank 3: 24 1364661Sksewell@umich.edu 1374661Sksewell@umich.edu Context = 32, // Bank 4: 32 - 33 1384661Sksewell@umich.edu ContextConfig, 1394661Sksewell@umich.edu 1404661Sksewell@umich.edu //PageMask = 40, //Bank 5: 40 - 41 1414661Sksewell@umich.edu PageGrain = 41, 1424661Sksewell@umich.edu 1434661Sksewell@umich.edu Wired = 48, //Bank 6:48-55 1444661Sksewell@umich.edu SRSConf0, 1454661Sksewell@umich.edu SRSConf1, 1464661Sksewell@umich.edu SRSConf2, 1474661Sksewell@umich.edu SRSConf3, 1484661Sksewell@umich.edu SRSConf4, 1494661Sksewell@umich.edu 1504661Sksewell@umich.edu HWRena = 56, //Bank 7: 56-63 1514661Sksewell@umich.edu 1524661Sksewell@umich.edu BadVAddr = 64, //Bank 8: 64-71 1534661Sksewell@umich.edu 1544661Sksewell@umich.edu Count = 72, //Bank 9: 72-79 1554661Sksewell@umich.edu 1564661Sksewell@umich.edu EntryHi = 80, //Bank 10: 80-87 1574661Sksewell@umich.edu 1584661Sksewell@umich.edu Compare = 88, //Bank 11: 88-95 1594661Sksewell@umich.edu 1604661Sksewell@umich.edu Status = 96, //Bank 12: 96-103 1614661Sksewell@umich.edu IntCtl, 1624661Sksewell@umich.edu SRSCtl, 1634661Sksewell@umich.edu SRSMap, 1644661Sksewell@umich.edu 1654661Sksewell@umich.edu Cause = 104, //Bank 13: 104-111 1664661Sksewell@umich.edu 1674661Sksewell@umich.edu EPC = 112, //Bank 14: 112-119 1684661Sksewell@umich.edu 1694661Sksewell@umich.edu PRId = 120, //Bank 15: 120-127, 1704661Sksewell@umich.edu EBase, 1714661Sksewell@umich.edu 1724661Sksewell@umich.edu Config = 128, //Bank 16: 128-135 1734661Sksewell@umich.edu Config1, 1744661Sksewell@umich.edu Config2, 1754661Sksewell@umich.edu Config3, 1764661Sksewell@umich.edu Config4, 1774661Sksewell@umich.edu Config5, 1784661Sksewell@umich.edu Config6, 1794661Sksewell@umich.edu Config7, 1804661Sksewell@umich.edu 1814661Sksewell@umich.edu 1824661Sksewell@umich.edu LLAddr = 136, //Bank 17: 136-143 1834661Sksewell@umich.edu 1844661Sksewell@umich.edu WatchLo0 = 144, //Bank 18: 144-151 1854661Sksewell@umich.edu WatchLo1, 1864661Sksewell@umich.edu WatchLo2, 1874661Sksewell@umich.edu WatchLo3, 1884661Sksewell@umich.edu WatchLo4, 1894661Sksewell@umich.edu WatchLo5, 1904661Sksewell@umich.edu WatchLo6, 1914661Sksewell@umich.edu WatchLo7, 1924661Sksewell@umich.edu 1934661Sksewell@umich.edu WatchHi0 = 152, //Bank 19: 152-159 1944661Sksewell@umich.edu WatchHi1, 1954661Sksewell@umich.edu WatchHi2, 1964661Sksewell@umich.edu WatchHi3, 1974661Sksewell@umich.edu WatchHi4, 1984661Sksewell@umich.edu WatchHi5, 1994661Sksewell@umich.edu WatchHi6, 2004661Sksewell@umich.edu WatchHi7, 2014661Sksewell@umich.edu 2024661Sksewell@umich.edu XCContext64 = 160, //Bank 20: 160-167 2034661Sksewell@umich.edu 2044661Sksewell@umich.edu //Bank 21: 168-175 2054661Sksewell@umich.edu 2064661Sksewell@umich.edu //Bank 22: 176-183 2074661Sksewell@umich.edu 2084661Sksewell@umich.edu Debug = 184, //Bank 23: 184-191 2094661Sksewell@umich.edu TraceControl1, 2104661Sksewell@umich.edu TraceControl2, 2114661Sksewell@umich.edu UserTraceData, 2124661Sksewell@umich.edu TraceBPC, 2134661Sksewell@umich.edu 2144661Sksewell@umich.edu DEPC = 192, //Bank 24: 192-199 2154661Sksewell@umich.edu 2164661Sksewell@umich.edu PerfCnt0 = 200, //Bank 25: 200-207 2174661Sksewell@umich.edu PerfCnt1, 2184661Sksewell@umich.edu PerfCnt2, 2194661Sksewell@umich.edu PerfCnt3, 2204661Sksewell@umich.edu PerfCnt4, 2214661Sksewell@umich.edu PerfCnt5, 2224661Sksewell@umich.edu PerfCnt6, 2234661Sksewell@umich.edu PerfCnt7, 2244661Sksewell@umich.edu 2254661Sksewell@umich.edu ErrCtl = 208, //Bank 26: 208-215 2264661Sksewell@umich.edu 2274661Sksewell@umich.edu CacheErr0 = 216, //Bank 27: 216-223 2284661Sksewell@umich.edu CacheErr1, 2294661Sksewell@umich.edu CacheErr2, 2304661Sksewell@umich.edu CacheErr3, 2314661Sksewell@umich.edu 2324661Sksewell@umich.edu TagLo0 = 224, //Bank 28: 224-231 2334661Sksewell@umich.edu DataLo1, 2344661Sksewell@umich.edu TagLo2, 2354661Sksewell@umich.edu DataLo3, 2364661Sksewell@umich.edu TagLo4, 2374661Sksewell@umich.edu DataLo5, 2384661Sksewell@umich.edu TagLo6, 2394661Sksewell@umich.edu DataLo7, 2404661Sksewell@umich.edu 2414661Sksewell@umich.edu TagHi0 = 232, //Bank 29: 232-239 2424661Sksewell@umich.edu DataHi1, 2434661Sksewell@umich.edu TagHi2, 2444661Sksewell@umich.edu DataHi3, 2454661Sksewell@umich.edu TagHi4, 2464661Sksewell@umich.edu DataHi5, 2474661Sksewell@umich.edu TagHi6, 2484661Sksewell@umich.edu DataHi7, 2494661Sksewell@umich.edu 2504661Sksewell@umich.edu 2514661Sksewell@umich.edu ErrorEPC = 240, //Bank 30: 240-247 2524661Sksewell@umich.edu 2534661Sksewell@umich.edu DESAVE = 248, //Bank 31: 248-256 2544661Sksewell@umich.edu 2554661Sksewell@umich.edu LLFlag = 257, 2564661Sksewell@umich.edu 2574661Sksewell@umich.edu NumControlRegs 2584661Sksewell@umich.edu }; 2594661Sksewell@umich.edu 2604661Sksewell@umich.edu const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs 2614661Sksewell@umich.edu const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// 2624661Sksewell@umich.edu const int NumMiscRegs = NumControlRegs; 2634661Sksewell@umich.edu 2644661Sksewell@umich.edu const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 2654661Sksewell@umich.edu 2664661Sksewell@umich.edu const int TotalDataRegs = NumIntRegs + NumFloatRegs; 2674661Sksewell@umich.edu 2684661Sksewell@umich.edu // These help enumerate all the registers for dependence tracking. 2694661Sksewell@umich.edu const int FP_Base_DepTag = NumIntRegs; 2704661Sksewell@umich.edu const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; 2712023SN/A}; 2722023SN/A 2732447SN/Ausing namespace MipsISA; 2742447SN/A 2752028SN/A#endif // __ARCH_MIPS_ISA_TRAITS_HH__ 276