isa_traits.hh revision 2597
12207SN/A/* 25254Sksewell@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 35254Sksewell@umich.edu * All rights reserved. 42207SN/A * 55254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145254Sksewell@umich.edu * this software without specific prior written permission. 152207SN/A * 165254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 285254Sksewell@umich.edu 295254Sksewell@umich.edu#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 305254Sksewell@umich.edu#define __ARCH_MIPS_ISA_TRAITS_HH__ 312207SN/A 322207SN/A#include "arch/mips/constants.hh" 332474SN/A#include "arch/mips/types.hh" 342207SN/A#include "arch/mips/regfile.hh" 358229Snate@binkert.org#include "arch/mips/faults.hh" 362454SN/A#include "arch/mips/utility.hh" 372454SN/A#include "base/misc.hh" 382680Sktlim@umich.edu#include "config/full_system.hh" 398232Snate@binkert.org#include "sim/byteswap.hh" 406650Sksewell@umich.edu#include "sim/host.hh" 416650Sksewell@umich.edu#include "sim/faults.hh" 426650Sksewell@umich.edu 432474SN/A#include <vector> 442207SN/A 452447SN/Aclass FastCPU; 462474SN/Aclass FullCPU; 472447SN/Aclass Checkpoint; 485154Sgblack@eecs.umich.educlass ExecContext; 495154Sgblack@eecs.umich.edu 505154Sgblack@eecs.umich.edunamespace LittleEndianGuest {}; 512474SN/A 522686Sksewell@umich.edu#define TARGET_MIPS 532686Sksewell@umich.edu 542935Sksewell@umich.educlass StaticInst; 552474SN/Aclass StaticInstPtr; 562474SN/A 572474SN/Anamespace MIPS34K { 582474SN/Aint DTB_ASN_ASN(uint64_t reg); 592686Sksewell@umich.eduint ITB_ASN_ASN(uint64_t reg); 602686Sksewell@umich.edu}; 6110318Sandreas.hansson@arm.com 622686Sksewell@umich.edu#if !FULL_SYSTEM 636811SMatt DeVuystclass SyscallReturn { 6411386Ssteve.reinhardt@amd.com public: 652474SN/A template <class T> 662474SN/A SyscallReturn(T v, bool s) 672474SN/A { 687532Ssteve.reinhardt@amd.com retval = (uint32_t)v; 692474SN/A success = s; 707532Ssteve.reinhardt@amd.com } 716650Sksewell@umich.edu 7210318Sandreas.hansson@arm.com template <class T> 732474SN/A SyscallReturn(T v) 745958Sgblack@eecs.umich.edu { 756811SMatt DeVuyst success = (v >= 0); 766650Sksewell@umich.edu retval = (uint32_t)v; 776811SMatt DeVuyst } 786650Sksewell@umich.edu 796811SMatt DeVuyst ~SyscallReturn() {} 806811SMatt DeVuyst 8111389Sbrandon.potter@amd.com SyscallReturn& operator=(const SyscallReturn& s) { 8211389Sbrandon.potter@amd.com retval = s.retval; 8311389Sbrandon.potter@amd.com success = s.success; 846650Sksewell@umich.edu return *this; 856650Sksewell@umich.edu } 866650Sksewell@umich.edu 876811SMatt DeVuyst bool successful() { return success; } 886811SMatt DeVuyst uint64_t value() { return retval; } 896811SMatt DeVuyst 906811SMatt DeVuyst 916811SMatt DeVuyst private: 926811SMatt DeVuyst uint64_t retval; 936811SMatt DeVuyst bool success; 9410318Sandreas.hansson@arm.com}; 956811SMatt DeVuyst#endif 966811SMatt DeVuyst 976811SMatt DeVuystnamespace MipsISA 986811SMatt DeVuyst{ 996811SMatt DeVuyst using namespace LittleEndianGuest; 1006811SMatt DeVuyst 1016811SMatt DeVuyst static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs) 1026811SMatt DeVuyst { 1036811SMatt DeVuyst if (return_value.successful()) { 1046811SMatt DeVuyst // no error 1056811SMatt DeVuyst regs->setIntReg(SyscallSuccessReg, 0); 10611389Sbrandon.potter@amd.com regs->setIntReg(ReturnValueReg1, return_value.value()); 10711389Sbrandon.potter@amd.com } else { 10811389Sbrandon.potter@amd.com // got an error, return details 10911389Sbrandon.potter@amd.com regs->setIntReg(SyscallSuccessReg, (IntReg) -1); 1106811SMatt DeVuyst regs->setIntReg(ReturnValueReg1, -return_value.value()); 1116811SMatt DeVuyst } 1126811SMatt DeVuyst } 1136811SMatt DeVuyst 1146811SMatt DeVuyst StaticInstPtr decodeInst(ExtMachInst); 1156811SMatt DeVuyst 1166811SMatt DeVuyst static inline ExtMachInst 1176811SMatt DeVuyst makeExtMI(MachInst inst, const uint64_t &pc) { 1186811SMatt DeVuyst#if FULL_SYSTEM 1196811SMatt DeVuyst ExtMachInst ext_inst = inst; 1206650Sksewell@umich.edu if (pc && 0x1) 1216650Sksewell@umich.edu return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32); 1226811SMatt DeVuyst else 1236811SMatt DeVuyst return ext_inst; 1246650Sksewell@umich.edu#else 1256650Sksewell@umich.edu return ExtMachInst(inst); 1266650Sksewell@umich.edu#endif 1276650Sksewell@umich.edu } 1286650Sksewell@umich.edu 1296650Sksewell@umich.edu /** 1306650Sksewell@umich.edu * Function to insure ISA semantics about 0 registers. 1316650Sksewell@umich.edu * @param xc The execution context. 1326650Sksewell@umich.edu */ 1336650Sksewell@umich.edu template <class XC> 1346811SMatt DeVuyst void zeroRegisters(XC *xc); 1356811SMatt DeVuyst 1366811SMatt DeVuyst const Addr MaxAddr = (Addr)-1; 1376811SMatt DeVuyst 1386811SMatt DeVuyst void copyRegs(ExecContext *src, ExecContext *dest); 1396650Sksewell@umich.edu 1406650Sksewell@umich.edu uint64_t convert_and_round(uint32_t fp_val, ConvertType cvt_type, int rnd_mode = 0); 1416650Sksewell@umich.edu uint64_t convert_and_round(uint64_t fp_val, ConvertType cvt_type, int rnd_mode = 0); 1426650Sksewell@umich.edu uint64_t convert_and_round(double fp_val, ConvertType cvt_type, int rnd_mode = 0); 1436650Sksewell@umich.edu 1446650Sksewell@umich.edu // Machine operations 1456650Sksewell@umich.edu 1468601Ssteve.reinhardt@amd.com void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 1476650Sksewell@umich.edu int regnum); 1486650Sksewell@umich.edu 1496811SMatt DeVuyst void restoreMachineReg(RegFile ®s, const AnyReg ®, 1506811SMatt DeVuyst int regnum); 1516811SMatt DeVuyst 1526811SMatt DeVuyst#if 0 1536811SMatt DeVuyst static void serializeSpecialRegs(const Serializable::Proxy &proxy, 1546650Sksewell@umich.edu const RegFile ®s); 1556650Sksewell@umich.edu 1566811SMatt DeVuyst static void unserializeSpecialRegs(const IniFile *db, 1576650Sksewell@umich.edu const std::string &category, 1586811SMatt DeVuyst ConfigNode *node, 1596650Sksewell@umich.edu RegFile ®s); 1608852Sandreas.hansson@arm.com#endif 1616650Sksewell@umich.edu 1626650Sksewell@umich.edu static inline Addr alignAddress(const Addr &addr, 1636650Sksewell@umich.edu unsigned int nbytes) { 1646650Sksewell@umich.edu return (addr & ~(nbytes - 1)); 1656650Sksewell@umich.edu } 1666811SMatt DeVuyst 1676811SMatt DeVuyst // Instruction address compression hooks 1688852Sandreas.hansson@arm.com static inline Addr realPCToFetchPC(const Addr &addr) { 1696811SMatt DeVuyst return addr; 1708852Sandreas.hansson@arm.com } 1716811SMatt DeVuyst 1726811SMatt DeVuyst static inline Addr fetchPCToRealPC(const Addr &addr) { 1736811SMatt DeVuyst return addr; 1746811SMatt DeVuyst } 1756811SMatt DeVuyst 1766811SMatt DeVuyst // the size of "fetched" instructions (not necessarily the size 1776811SMatt DeVuyst // of real instructions for PISA) 1788852Sandreas.hansson@arm.com static inline size_t fetchInstSize() { 1796811SMatt DeVuyst return sizeof(MachInst); 1806811SMatt DeVuyst } 1816650Sksewell@umich.edu 1826650Sksewell@umich.edu static inline MachInst makeRegisterCopy(int dest, int src) { 1836650Sksewell@umich.edu panic("makeRegisterCopy not implemented"); 1846650Sksewell@umich.edu return 0; 1856650Sksewell@umich.edu } 1866650Sksewell@umich.edu 18711389Sbrandon.potter@amd.com}; 1886650Sksewell@umich.edu 1896650Sksewell@umich.edu#if FULL_SYSTEM 1906650Sksewell@umich.edu 1915958Sgblack@eecs.umich.edu#include "arch/mips/mips34k.hh" 1926701Sgblack@eecs.umich.edu 1935958Sgblack@eecs.umich.edu#endif 1945958Sgblack@eecs.umich.edu 1956701Sgblack@eecs.umich.eduusing namespace MipsISA; 1965958Sgblack@eecs.umich.edu 1975958Sgblack@eecs.umich.edu#endif // __ARCH_MIPS_ISA_TRAITS_HH__ 1985958Sgblack@eecs.umich.edu