isa_traits.hh revision 2472
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 30#define __ARCH_MIPS_ISA_TRAITS_HH__ 31 32//#include "arch/mips/misc_regfile.hh" 33#include "base/misc.hh" 34#include "config/full_system.hh" 35#include "sim/host.hh" 36#include "sim/faults.hh" 37 38#include <vector> 39 40class FastCPU; 41class FullCPU; 42class Checkpoint; 43class ExecContext; 44 45namespace LittleEndianGuest {}; 46using namespace LittleEndianGuest; 47 48#define TARGET_MIPS 49 50class StaticInst; 51class StaticInstPtr; 52 53namespace MIPS34K { 54int DTB_ASN_ASN(uint64_t reg); 55int ITB_ASN_ASN(uint64_t reg); 56}; 57 58#if !FULL_SYSTEM 59class SyscallReturn { 60 public: 61 template <class T> 62 SyscallReturn(T v, bool s) 63 { 64 retval = (uint64_t)v; 65 success = s; 66 } 67 68 template <class T> 69 SyscallReturn(T v) 70 { 71 success = (v >= 0); 72 retval = (uint64_t)v; 73 } 74 75 ~SyscallReturn() {} 76 77 SyscallReturn& operator=(const SyscallReturn& s) { 78 retval = s.retval; 79 success = s.success; 80 return *this; 81 } 82 83 bool successful() { return success; } 84 uint64_t value() { return retval; } 85 86 87 private: 88 uint64_t retval; 89 bool success; 90}; 91#endif 92 93namespace MipsISA 94{ 95 typedef uint32_t MachInst; 96 typedef uint32_t MachInst; 97 typedef uint64_t ExtMachInst; 98 typedef uint8_t RegIndex; 99// typedef uint64_t Addr; 100 101 // Constants Related to the number of registers 102 103 const int NumIntArchRegs = 32; 104 const int NumPALShadowRegs = 8; 105 const int NumFloatArchRegs = 32; 106 // @todo: Figure out what this number really should be. 107 const int NumMiscArchRegs = 32; 108 109 const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 110 const int NumFloatRegs = NumFloatArchRegs; 111 const int NumMiscRegs = NumMiscArchRegs; 112 113 const int TotalNumRegs = NumIntRegs + NumFloatRegs + 114 NumMiscRegs + 0/*NumInternalProcRegs*/; 115 116 const int TotalDataRegs = NumIntRegs + NumFloatRegs; 117 118 // Static instruction parameters 119 const int MaxInstSrcRegs = 3; 120 const int MaxInstDestRegs = 2; 121 122 // semantically meaningful register indices 123 const int ZeroReg = 0; 124 const int AssemblerReg = 1; 125 const int ReturnValueReg1 = 2; 126 const int ReturnValueReg2 = 3; 127 const int ArgumentReg0 = 4; 128 const int ArgumentReg1 = 5; 129 const int ArgumentReg2 = 6; 130 const int ArgumentReg3 = 7; 131 const int KernelReg0 = 26; 132 const int KernelReg1 = 27; 133 const int GlobalPointerReg = 28; 134 const int StackPointerReg = 29; 135 const int FramePointerReg = 30; 136 const int ReturnAddressReg = 31; 137 138 const int SyscallNumReg = ReturnValueReg1; 139 const int SyscallPseudoReturnReg = ArgumentReg3; 140 const int SyscallSuccessReg = 19; 141 142 const int LogVMPageSize = 13; // 8K bytes 143 const int VMPageSize = (1 << LogVMPageSize); 144 145 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 146 147 const int WordBytes = 4; 148 const int HalfwordBytes = 2; 149 const int ByteBytes = 1; 150 151 152 // These enumerate all the registers for dependence tracking. 153 enum DependenceTags { 154 // 0..31 are the integer regs 0..31 155 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 156 FP_Base_DepTag = 32, 157 Ctrl_Base_DepTag = 64, 158 Fpcr_DepTag = 64, // floating point control register 159 Uniq_DepTag = 65, 160 IPR_Base_DepTag = 66, 161 MiscReg_DepTag = 67 162 }; 163 164 typedef uint64_t IntReg; 165 typedef IntReg IntRegFile[NumIntRegs]; 166 167/* floating point register file entry type 168 typedef union { 169 uint64_t q; 170 double d; 171 } FloatReg;*/ 172 173 typedef double FloatReg; 174 typedef uint64_t FloatRegBits; 175 176/*typedef union { 177 uint64_t q[NumFloatRegs]; // integer qword view 178 double d[NumFloatRegs]; // double-precision floating point view 179 } FloatRegFile;*/ 180 181 class FloatRegFile 182 { 183 protected: 184 185 FloatRegBits q[NumFloatRegs]; // integer qword view 186 double d[NumFloatRegs]; // double-precision floating point view 187 188 public: 189 190 FloatReg readReg(int floatReg) 191 { 192 return d[floatReg]; 193 } 194 195 FloatReg readReg(int floatReg, int width) 196 { 197 return readReg(floatReg); 198 } 199 200 FloatRegBits readRegBits(int floatReg) 201 { 202 return q[floatReg]; 203 } 204 205 FloatRegBits readRegBits(int floatReg, int width) 206 { 207 return readRegBits(floatReg); 208 } 209 210 Fault setReg(int floatReg, const FloatReg &val) 211 { 212 d[floatReg] = val; 213 return NoFault; 214 } 215 216 Fault setReg(int floatReg, const FloatReg &val, int width) 217 { 218 return setReg(floatReg, val); 219 } 220 221 Fault setRegBits(int floatReg, const FloatRegBits &val) 222 { 223 q[floatReg] = val; 224 return NoFault; 225 } 226 227 Fault setRegBits(int floatReg, const FloatRegBits &val, int width) 228 { 229 return setRegBits(floatReg, val); 230 } 231 232 void serialize(std::ostream &os); 233 234 void unserialize(Checkpoint *cp, const std::string §ion); 235 236 }; 237 238 void copyRegs(ExecContext *src, ExecContext *dest); 239 240 // cop-0/cop-1 system control register file 241 typedef uint64_t MiscReg; 242//typedef MiscReg MiscRegFile[NumMiscRegs]; 243 class MiscRegFile { 244 245 protected: 246 uint64_t fpcr; // floating point condition codes 247 uint64_t uniq; // process-unique register 248 bool lock_flag; // lock flag for LL/SC 249 Addr lock_addr; // lock address for LL/SC 250 251 MiscReg miscRegFile[NumMiscRegs]; 252 253 public: 254 //These functions should be removed once the simplescalar cpu model 255 //has been replaced. 256 int getInstAsid(); 257 int getDataAsid(); 258 259 void copyMiscRegs(ExecContext *xc); 260 261 MiscReg readReg(int misc_reg) 262 { return miscRegFile[misc_reg]; } 263 264 MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc) 265 { return miscRegFile[misc_reg];} 266 267 Fault setReg(int misc_reg, const MiscReg &val) 268 { miscRegFile[misc_reg] = val; return NoFault; } 269 270 Fault setRegWithEffect(int misc_reg, const MiscReg &val, 271 ExecContext *xc) 272 { miscRegFile[misc_reg] = val; return NoFault; } 273 274#if FULL_SYSTEM 275 void clearIprs() { } 276 277 protected: 278 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs 279 280 private: 281 MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { } 282 283 Fault setIpr(int idx, uint64_t val, ExecContext *xc) { } 284#endif 285 friend class RegFile; 286 }; 287 288 enum MiscRegTags { 289 //Coprocessor 0 Registers 290 //Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 291 //(Register Number-Register Select) Summary of Register 292 //------------------------------------------------------ 293 Index = 0, //0-0 Index into the TLB array 294 295 MVPControl = 1, //0-1 Per-processor register containing global 296 //MIPS� MT configuration data 297 298 MVPConf0 = 2, //0-2 Per-processor register containing global 299 //MIPS� MT configuration data 300 301 MVPConf1 = 3, //0-3 Per-processor register containing global 302 //MIPS� MT configuration data 303 304 Random = 8, //1-0 Randomly generated index into the TLB array 305 306 VPEControl = 9, //1-1 Per-VPE register containing relatively volatile 307 //thread configuration data 308 309 VPEConf0 = 10, //1-2 Per-VPE multi-thread configuration 310 //information 311 312 313 VPEConf1 = 11, //1-2 Per-VPE multi-thread configuration 314 //information 315 316 YQMask = 12, //Per-VPE register defining which YIELD 317 //qualifier bits may be used without generating 318 //an exception 319 320 VPESchedule = 13, 321 VPEScheFBack = 14, 322 VPEOpt = 15, 323 EntryLo0 = 16, // Bank 3: 16 - 23 324 TCStatus = 17, 325 TCBind = 18, 326 TCRestart = 19, 327 TCHalt = 20, 328 TCContext = 21, 329 TCSchedule = 22, 330 TCScheFBack = 23, 331 332 EntryLo1 = 24,// Bank 4: 24 - 31 333 334 Context = 32, // Bank 5: 32 - 39 335 ContextConfig = 33, 336 337 //PageMask = 40, //Bank 6: 40 - 47 338 PageGrain = 41, 339 340 Wired = 48, //Bank 7:48 - 55 341 SRSConf0 = 49, 342 SRSConf1 = 50, 343 SRSConf2 = 51, 344 SRSConf3 = 52, 345 SRSConf4 = 53, 346 BadVAddr = 54, 347 348 HWRena = 56,//Bank 8:56 - 63 349 350 Count = 64, //Bank 9:64 - 71 351 352 EntryHi = 72,//Bank 10:72 - 79 353 354 Compare = 80,//Bank 11:80 - 87 355 356 Status = 88,//Bank 12:88 - 96 //12-0 Processor status and control 357 IntCtl = 89, //12-1 Interrupt system status and control 358 SRSCtl = 90, //12-2 Shadow register set status and control 359 SRSMap = 91, //12-3 Shadow set IPL mapping 360 361 Cause = 97,//97-104 //13-0 Cause of last general exception 362 363 EPC = 105,//105-112 //14-0 Program counter at last exception 364 365 PRId = 113,//113-120, //15-0 Processor identification and revision 366 EBase = 114, //15-1 Exception vector base register 367 368 Config = 121,//Bank 16: 121-128 369 Config1 = 122, 370 Config2 = 123, 371 Config3 = 124, 372 Config6 = 127, 373 Config7 = 128, 374 375 376 LLAddr = 129,//Bank 17: 129-136 377 378 WatchLo0 = 137,//Bank 18: 137-144 379 WatchLo1 = 138, 380 WatchLo2 = 139, 381 WatchLo3 = 140, 382 WatchLo4 = 141, 383 WatchLo5 = 142, 384 WatchLo6 = 143, 385 WatchLo7 = 144, 386 387 WatchHi0 = 145,//Bank 19: 145-152 388 WatchHi1 = 146, 389 WatchHi2 = 147, 390 WatchHi3 = 148, 391 WatchHi4 = 149, 392 WatchHi5 = 150, 393 WatchHi6 = 151, 394 WatchHi7 = 152, 395 396 XCContext64 = 153,//Bank 20: 153-160 397 398 //Bank 21: 161-168 399 400 //Bank 22: 169-176 401 402 Debug = 177, //Bank 23: 177-184 403 TraceControl1 = 178, 404 TraceControl2 = 179, 405 UserTraceData = 180, 406 TraceBPC = 181, 407 408 DEPC = 185,//Bank 24: 185-192 409 410 PerfCnt0 = 193,//Bank 25: 193 - 200 411 PerfCnt1 = 194, 412 PerfCnt2 = 195, 413 PerfCnt3 = 196, 414 PerfCnt4 = 197, 415 PerfCnt5 = 198, 416 PerfCnt6 = 199, 417 PerfCnt7 = 200, 418 419 ErrCtl = 201, //Bank 26: 201 - 208 420 421 CacheErr0 = 209, //Bank 27: 209 - 216 422 CacheErr1 = 210, 423 CacheErr2 = 211, 424 CacheErr3 = 212, 425 426 TagLo0 = 217,//Bank 28: 217 - 224 427 DataLo1 = 218, 428 TagLo2 = 219, 429 DataLo3 = 220, 430 TagLo4 = 221, 431 DataLo5 = 222, 432 TagLo6 = 223, 433 DataLo7 = 234, 434 435 TagHi0 = 233,//Bank 29: 233 - 240 436 DataHi1 = 234, 437 TagHi2 = 235, 438 DataHi3 = 236, 439 TagHi4 = 237, 440 DataHi5 = 238, 441 TagHi6 = 239, 442 DataHi7 = 240, 443 444 445 ErrorEPC = 249,//Bank 30: 241 - 248 446 447 DESAVE = 257,//Bank 31: 249-256 448 449 //More Misc. Regs 450 Hi, 451 Lo, 452 FCSR, 453 FPCR, 454 455 //Alpha Regs, but here now, for 456 //compiling sake 457 UNIQ, 458 LockAddr, 459 LockFlag 460 }; 461 462extern const Addr PageShift; 463extern const Addr PageBytes; 464extern const Addr PageMask; 465extern const Addr PageOffset; 466 467#if FULL_SYSTEM 468 469 typedef uint64_t InternalProcReg; 470 471#include "arch/mips/isa_fullsys_traits.hh" 472 473#else 474 enum { 475 NumInternalProcRegs = 0 476 }; 477#endif 478 479 typedef union { 480 IntReg intreg; 481 FloatReg fpreg; 482 MiscReg ctrlreg; 483 } AnyReg; 484 485 struct RegFile { 486 IntRegFile intRegFile; // (signed) integer register file 487 FloatRegFile floatRegFile; // floating point register file 488 MiscRegFile miscRegs; // control register file 489 490 491 Addr pc; // program counter 492 Addr npc; // next-cycle program counter 493 Addr nnpc; // next-next-cycle program counter 494 // used to implement branch delay slot 495 // not real register 496 497 MiscReg hi; // MIPS HI Register 498 MiscReg lo; // MIPS LO Register 499 500 501#if FULL_SYSTEM 502 IntReg palregs[NumIntRegs]; // PAL shadow registers 503 InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs 504 int intrflag; // interrupt flag 505 bool pal_shadow; // using pal_shadow registers 506 inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); } 507 inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); } 508#endif // FULL_SYSTEM 509 510 //void initCP0Regs(); 511 void serialize(std::ostream &os); 512 void unserialize(Checkpoint *cp, const std::string §ion); 513 514 void createCP0Regs(); 515 void coldReset(); 516 }; 517 518 StaticInstPtr decodeInst(ExtMachInst); 519 520 // return a no-op instruction... used for instruction fetch faults 521 extern const MachInst NoopMachInst; 522 523 enum annotes { 524 ANNOTE_NONE = 0, 525 // An impossible number for instruction annotations 526 ITOUCH_ANNOTE = 0xffffffff, 527 }; 528 529//void getMiscRegIdx(int reg_name,int &idx, int &sel); 530 531 static inline ExtMachInst 532 makeExtMI(MachInst inst, const uint64_t &pc) { 533#if FULL_SYSTEM 534 ExtMachInst ext_inst = inst; 535 if (pc && 0x1) 536 return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32); 537 else 538 return ext_inst; 539#else 540 return ExtMachInst(inst); 541#endif 542 } 543 544 static inline bool isCallerSaveIntegerRegister(unsigned int reg) { 545 panic("register classification not implemented"); 546 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 547 } 548 549 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 550 panic("register classification not implemented"); 551 return (reg >= 9 && reg <= 15); 552 } 553 554 static inline bool isCallerSaveFloatRegister(unsigned int reg) { 555 panic("register classification not implemented"); 556 return false; 557 } 558 559 static inline bool isCalleeSaveFloatRegister(unsigned int reg) { 560 panic("register classification not implemented"); 561 return false; 562 } 563 564 static inline Addr alignAddress(const Addr &addr, 565 unsigned int nbytes) { 566 return (addr & ~(nbytes - 1)); 567 } 568 569 // Instruction address compression hooks 570 static inline Addr realPCToFetchPC(const Addr &addr) { 571 return addr; 572 } 573 574 static inline Addr fetchPCToRealPC(const Addr &addr) { 575 return addr; 576 } 577 578 // the size of "fetched" instructions (not necessarily the size 579 // of real instructions for PISA) 580 static inline size_t fetchInstSize() { 581 return sizeof(MachInst); 582 } 583 584 static inline MachInst makeRegisterCopy(int dest, int src) { 585 panic("makeRegisterCopy not implemented"); 586 return 0; 587 } 588 589 static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs) 590 { 591 panic("Returning from syscall\n"); 592 } 593 594 // Machine operations 595 596 void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 597 int regnum); 598 599 void restoreMachineReg(RegFile ®s, const AnyReg ®, 600 int regnum); 601 602#if 0 603 static void serializeSpecialRegs(const Serializable::Proxy &proxy, 604 const RegFile ®s); 605 606 static void unserializeSpecialRegs(const IniFile *db, 607 const std::string &category, 608 ConfigNode *node, 609 RegFile ®s); 610#endif 611 612 /** 613 * Function to insure ISA semantics about 0 registers. 614 * @param xc The execution context. 615 */ 616 template <class XC> 617 void zeroRegisters(XC *xc); 618 619 const Addr MaxAddr = (Addr)-1; 620}; 621 622#if FULL_SYSTEM 623//typedef TheISA::InternalProcReg InternalProcReg; 624//const int NumInternalProcRegs = TheISA::NumInternalProcRegs; 625//const int NumInterruptLevels = TheISA::NumInterruptLevels; 626 627#include "arch/mips/mips34k.hh" 628#endif 629 630using namespace MipsISA; 631 632#endif // __ARCH_MIPS_ISA_TRAITS_HH__ 633