isa_traits.hh revision 2239 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
30#define __ARCH_MIPS_ISA_TRAITS_HH__
31
32//#include "arch/mips/misc_regfile.hh"
33#include "base/misc.hh"
34#include "config/full_system.hh"
35#include "sim/host.hh"
36#include "sim/faults.hh"
37
38#include <vector>
39
40class FastCPU;
41class FullCPU;
42class Checkpoint;
43
44namespace LittleEndianGuest {};
45using namespace LittleEndianGuest;
46
47#define TARGET_MIPS
48
49class StaticInst;
50class StaticInstPtr;
51
52namespace MIPS34K {
53int DTB_ASN_ASN(uint64_t reg);
54int ITB_ASN_ASN(uint64_t reg);
55};
56
57namespace MipsISA
58{
59    typedef uint32_t MachInst;
60//  typedef uint64_t Addr;
61    typedef uint8_t  RegIndex;
62
63    enum {
64        MemoryEnd = 0xffffffffffffffffULL,
65
66        NumIntRegs = 32,
67        NumFloatRegs = 32,
68        NumMiscRegs = 256,
69
70        MaxRegsOfAnyType = 32,
71        // Static instruction parameters
72        MaxInstSrcRegs = 3,
73        MaxInstDestRegs = 2,
74
75        // semantically meaningful register indices
76        ZeroReg = 0,	// architecturally meaningful
77        // the rest of these depend on the ABI
78        StackPointerReg = 30,
79        GlobalPointerReg = 29,
80        ProcedureValueReg = 27,
81        ReturnAddressReg = 26,
82        ReturnValueReg = 0,
83        FramePointerReg = 15,
84        ArgumentReg0 = 16,
85        ArgumentReg1 = 17,
86        ArgumentReg2 = 18,
87        ArgumentReg3 = 19,
88        ArgumentReg4 = 20,
89        ArgumentReg5 = 21,
90
91        LogVMPageSize = 13,	// 8K bytes
92        VMPageSize = (1 << LogVMPageSize),
93
94        BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
95
96        WordBytes = 4,
97        HalfwordBytes = 2,
98        ByteBytes = 1,
99        DepNA = 0,
100    };
101
102    // These enumerate all the registers for dependence tracking.
103    enum DependenceTags {
104        // 0..31 are the integer regs 0..31
105        // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
106        FP_Base_DepTag = 32,
107        Ctrl_Base_DepTag = 64,
108        Fpcr_DepTag = 64,		// floating point control register
109        Uniq_DepTag = 65,
110        IPR_Base_DepTag = 66,
111        MiscReg_DepTag = 67
112    };
113
114    typedef uint64_t IntReg;
115    typedef IntReg IntRegFile[NumIntRegs];
116
117    // floating point register file entry type
118    typedef union {
119        uint64_t q;
120        double d;
121    } FloatReg;
122
123    typedef union {
124        uint64_t q[NumFloatRegs];	// integer qword view
125        double d[NumFloatRegs];		// double-precision floating point view
126    } FloatRegFile;
127
128    // cop-0/cop-1 system control register file
129    typedef uint64_t MiscReg;
130//typedef MiscReg MiscRegFile[NumMiscRegs];
131
132    typedef std::vector<MiscReg> MiscRegFile[NumMiscRegs];
133//    typedef MiscRegBank MiscRegBanks[NumMiscRegs];
134
135
136    enum MiscRegTags {
137        //Coprocessor 0 Registers
138        //Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
139        //(Register Number-Register Select) Summary of Register
140        //------------------------------------------------------
141        Index,       //0-0 Index into the TLB array
142
143        MVPControl,  //0-1 Per-processor register containing global
144                     //MIPS� MT configuration data
145
146        MVPConf0,    //0-2 Per-processor register containing global
147                     //MIPS� MT configuration data
148
149        MVPConf1,    //0-3 Per-processor register containing global
150                     //MIPS� MT configuration data
151
152        Random,      //1-0 Randomly generated index into the TLB array
153
154        VPEControl,  //1-1 Per-VPE register containing relatively volatile
155                     //thread configuration data
156
157        VPEConf0,    //1-2 Per-VPE multi-thread configuration
158                     //information
159
160
161        VPEConf1,    //1-2 Per-VPE multi-thread configuration
162                     //information
163
164        YQMask,      //Per-VPE register defining which YIELD
165                     //qualifier bits may be used without generating
166                     //an exception
167
168        VPESchedule,
169        VPEScheFBack,
170        VPEOpt,
171        EntryLo0,
172        TCStatus,
173        TCBind,
174        TCRestart,
175        TCHalt,
176        TCContext,
177        TCSchedule,
178        TCScheFBack,
179        EntryLo1,
180        Context,
181        ContextConfig,
182        //PageMask,
183        PageGrain,
184        Wired,
185        SRSConf0,
186        SRSConf1,
187        SRSConf2,
188        SRSConf3,
189        SRSConf4,
190        BadVAddr,
191        Count,
192        EntryHi,
193        Compare,
194        Status,     //12-0 Processor status and control
195        IntCtl,     //12-1 Interrupt system status and control
196        SRSCtl,     //12-2 Shadow register set status and control
197        SRSMap,     //12-3 Shadow set IPL mapping
198        Cause,      //13-0 Cause of last general exception
199        EPC,        //14-0 Program counter at last exception
200        PRId,       //15-0 Processor identification and revision
201        EBase,      //15-1 Exception vector base register
202        Config,
203        Config1,
204        Config2,
205        Config3,
206        LLAddr,
207        WatchLo,
208        WatchHi,
209        Debug,
210        TraceControl1,
211        TraceControl2,
212        UserTraceData,
213        TraceBPC,
214
215        DEPC,
216
217        PerfCnt,
218
219        ErrCtl,
220
221        CacheErr0,
222        CacheErr1,
223        CacheErr2,
224        CacheErr3,
225
226        TagLo,
227        DataLo,
228        TagHi,
229        DataHi,
230        ErrorEPC,
231        DESAVE,
232
233        //More Misc. Regs
234        Hi,
235        Lo,
236        FCSR,
237        FPCR,
238        LockAddr,
239        LockFlag,
240
241        //Alpha Regs, but here now, for
242        //compiling sake
243        UNIQ
244    };
245
246extern const Addr PageShift;
247extern const Addr PageBytes;
248extern const Addr PageMask;
249extern const Addr PageOffset;
250
251#if FULL_SYSTEM
252
253    typedef uint64_t InternalProcReg;
254
255#include "arch/mips/isa_fullsys_traits.hh"
256
257#else
258    enum {
259        NumInternalProcRegs = 0
260    };
261#endif
262
263    enum {
264        TotalNumRegs =
265        NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
266    };
267
268    enum {
269        TotalDataRegs = NumIntRegs + NumFloatRegs
270    };
271
272    typedef union {
273        IntReg  intreg;
274        FloatReg   fpreg;
275        MiscReg ctrlreg;
276    } AnyReg;
277
278    struct RegFile {
279        IntRegFile intRegFile;		// (signed) integer register file
280        FloatRegFile floatRegFile;	// floating point register file
281        MiscRegFile miscRegs;		// control register file
282
283
284        Addr pc;			// program counter
285        Addr npc;			// next-cycle program counter
286        Addr nnpc;			// next-next-cycle program counter
287                                        // used to implement branch delay slot
288                                        // not real register
289
290        MiscReg hi;                     // MIPS HI Register
291        MiscReg lo;                     // MIPS LO Register
292
293
294#if FULL_SYSTEM
295        IntReg palregs[NumIntRegs];	// PAL shadow registers
296        InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
297        int intrflag;			// interrupt flag
298        bool pal_shadow;		// using pal_shadow registers
299        inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
300        inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
301#endif // FULL_SYSTEM
302
303        //void initCP0Regs();
304        void serialize(std::ostream &os);
305        void unserialize(Checkpoint *cp, const std::string &section);
306
307        void createCP0Regs();
308        void coldReset();
309    };
310
311    StaticInstPtr decodeInst(MachInst);
312
313    // return a no-op instruction... used for instruction fetch faults
314    extern const MachInst NoopMachInst;
315
316    enum annotes {
317        ANNOTE_NONE = 0,
318        // An impossible number for instruction annotations
319        ITOUCH_ANNOTE = 0xffffffff,
320    };
321
322   void getMiscRegIdx(int reg_name,int &idx, int &sel);
323
324
325    static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
326        panic("register classification not implemented");
327        return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
328    }
329
330    static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
331        panic("register classification not implemented");
332        return (reg >= 9 && reg <= 15);
333    }
334
335    static inline bool isCallerSaveFloatRegister(unsigned int reg) {
336        panic("register classification not implemented");
337        return false;
338    }
339
340    static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
341        panic("register classification not implemented");
342        return false;
343    }
344
345    static inline Addr alignAddress(const Addr &addr,
346                                         unsigned int nbytes) {
347        return (addr & ~(nbytes - 1));
348    }
349
350    // Instruction address compression hooks
351    static inline Addr realPCToFetchPC(const Addr &addr) {
352        return addr;
353    }
354
355    static inline Addr fetchPCToRealPC(const Addr &addr) {
356        return addr;
357    }
358
359    // the size of "fetched" instructions (not necessarily the size
360    // of real instructions for PISA)
361    static inline size_t fetchInstSize() {
362        return sizeof(MachInst);
363    }
364
365    static inline MachInst makeRegisterCopy(int dest, int src) {
366        panic("makeRegisterCopy not implemented");
367        return 0;
368    }
369
370    // Machine operations
371
372    void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
373                               int regnum);
374
375    void restoreMachineReg(RegFile &regs, const AnyReg &reg,
376                                  int regnum);
377
378#if 0
379    static void serializeSpecialRegs(const Serializable::Proxy &proxy,
380                                     const RegFile &regs);
381
382    static void unserializeSpecialRegs(const IniFile *db,
383                                       const std::string &category,
384                                       ConfigNode *node,
385                                       RegFile &regs);
386#endif
387
388    /**
389     * Function to insure ISA semantics about 0 registers.
390     * @param xc The execution context.
391     */
392    template <class XC>
393    void zeroRegisters(XC *xc);
394
395    const Addr MaxAddr = (Addr)-1;
396};
397
398#if !FULL_SYSTEM
399class SyscallReturn {
400        public:
401           template <class T>
402           SyscallReturn(T v, bool s)
403           {
404               retval = (uint64_t)v;
405               success = s;
406           }
407
408           template <class T>
409           SyscallReturn(T v)
410           {
411               success = (v >= 0);
412               retval = (uint64_t)v;
413           }
414
415           ~SyscallReturn() {}
416
417           SyscallReturn& operator=(const SyscallReturn& s) {
418               retval = s.retval;
419               success = s.success;
420               return *this;
421           }
422
423           bool successful() { return success; }
424           uint64_t value() { return retval; }
425
426
427       private:
428           uint64_t retval;
429           bool success;
430};
431
432#endif
433
434
435#if FULL_SYSTEM
436//typedef TheISA::InternalProcReg InternalProcReg;
437//const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
438//const int NumInterruptLevels = TheISA::NumInterruptLevels;
439
440#include "arch/mips/mips34k.hh"
441#endif
442
443#endif // __ARCH_MIPS_ISA_TRAITS_HH__
444