isa_traits.hh revision 2131
18889Sgeoffrey.blake@arm.com/* 28889Sgeoffrey.blake@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 38889Sgeoffrey.blake@arm.com * All rights reserved. 48889Sgeoffrey.blake@arm.com * 58889Sgeoffrey.blake@arm.com * Redistribution and use in source and binary forms, with or without 68889Sgeoffrey.blake@arm.com * modification, are permitted provided that the following conditions are 78889Sgeoffrey.blake@arm.com * met: redistributions of source code must retain the above copyright 88889Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer; 98889Sgeoffrey.blake@arm.com * redistributions in binary form must reproduce the above copyright 108889Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer in the 118889Sgeoffrey.blake@arm.com * documentation and/or other materials provided with the distribution; 128889Sgeoffrey.blake@arm.com * neither the name of the copyright holders nor the names of its 139348SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 148889Sgeoffrey.blake@arm.com * this software without specific prior written permission. 158889Sgeoffrey.blake@arm.com * 168889Sgeoffrey.blake@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 178889Sgeoffrey.blake@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 188889Sgeoffrey.blake@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 198889Sgeoffrey.blake@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208889Sgeoffrey.blake@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218889Sgeoffrey.blake@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 228889Sgeoffrey.blake@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 238889Sgeoffrey.blake@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 248889Sgeoffrey.blake@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 258889Sgeoffrey.blake@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 268889Sgeoffrey.blake@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 278889Sgeoffrey.blake@arm.com */ 288889Sgeoffrey.blake@arm.com 298889Sgeoffrey.blake@arm.com#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 308889Sgeoffrey.blake@arm.com#define __ARCH_MIPS_ISA_TRAITS_HH__ 318889Sgeoffrey.blake@arm.com 328889Sgeoffrey.blake@arm.comnamespace LittleEndianGuest {} 338889Sgeoffrey.blake@arm.comusing namespace LittleEndianGuest; 348889Sgeoffrey.blake@arm.com 358889Sgeoffrey.blake@arm.com//#include "arch/mips/faults.hh" 368889Sgeoffrey.blake@arm.com#include "base/misc.hh" 378889Sgeoffrey.blake@arm.com#include "config/full_system.hh" 388889Sgeoffrey.blake@arm.com#include "sim/host.hh" 398889Sgeoffrey.blake@arm.com#include "sim/faults.hh" 408889Sgeoffrey.blake@arm.com 418889Sgeoffrey.blake@arm.comclass FastCPU; 428983Snate@binkert.orgclass FullCPU; 438889Sgeoffrey.blake@arm.comclass Checkpoint; 448889Sgeoffrey.blake@arm.com 458889Sgeoffrey.blake@arm.com#define TARGET_MIPS 468889Sgeoffrey.blake@arm.com 478889Sgeoffrey.blake@arm.comclass StaticInst; 488889Sgeoffrey.blake@arm.comclass StaticInstPtr; 498889Sgeoffrey.blake@arm.com 508889Sgeoffrey.blake@arm.comnamespace MIPS34K { 518889Sgeoffrey.blake@arm.comint DTB_ASN_ASN(uint64_t reg); 528889Sgeoffrey.blake@arm.comint ITB_ASN_ASN(uint64_t reg); 538889Sgeoffrey.blake@arm.com} 548889Sgeoffrey.blake@arm.com 558889Sgeoffrey.blake@arm.comnamespace MipsISA 568889Sgeoffrey.blake@arm.com{ 578889Sgeoffrey.blake@arm.com 588889Sgeoffrey.blake@arm.com typedef uint32_t MachInst; 598889Sgeoffrey.blake@arm.com// typedef uint64_t Addr; 608889Sgeoffrey.blake@arm.com typedef uint8_t RegIndex; 618889Sgeoffrey.blake@arm.com 628889Sgeoffrey.blake@arm.com enum { 638889Sgeoffrey.blake@arm.com MemoryEnd = 0xffffffffffffffffULL, 648889Sgeoffrey.blake@arm.com 658889Sgeoffrey.blake@arm.com NumIntRegs = 32, 668889Sgeoffrey.blake@arm.com NumFloatRegs = 32, 679348SAli.Saidi@ARM.com NumMiscRegs = 32, 688889Sgeoffrey.blake@arm.com 698889Sgeoffrey.blake@arm.com MaxRegsOfAnyType = 32, 708889Sgeoffrey.blake@arm.com // Static instruction parameters 718889Sgeoffrey.blake@arm.com MaxInstSrcRegs = 3, 728889Sgeoffrey.blake@arm.com MaxInstDestRegs = 2, 738889Sgeoffrey.blake@arm.com 748889Sgeoffrey.blake@arm.com // semantically meaningful register indices 758889Sgeoffrey.blake@arm.com ZeroReg = 31, // architecturally meaningful 768889Sgeoffrey.blake@arm.com // the rest of these depend on the ABI 778889Sgeoffrey.blake@arm.com StackPointerReg = 30, 788889Sgeoffrey.blake@arm.com GlobalPointerReg = 29, 798889Sgeoffrey.blake@arm.com ProcedureValueReg = 27, 808889Sgeoffrey.blake@arm.com ReturnAddressReg = 26, 818889Sgeoffrey.blake@arm.com ReturnValueReg = 0, 828889Sgeoffrey.blake@arm.com FramePointerReg = 15, 838889Sgeoffrey.blake@arm.com ArgumentReg0 = 16, 848889Sgeoffrey.blake@arm.com ArgumentReg1 = 17, 858889Sgeoffrey.blake@arm.com ArgumentReg2 = 18, 868889Sgeoffrey.blake@arm.com ArgumentReg3 = 19, 878889Sgeoffrey.blake@arm.com ArgumentReg4 = 20, 888889Sgeoffrey.blake@arm.com ArgumentReg5 = 21, 898889Sgeoffrey.blake@arm.com 908889Sgeoffrey.blake@arm.com LogVMPageSize = 13, // 8K bytes 918889Sgeoffrey.blake@arm.com VMPageSize = (1 << LogVMPageSize), 928889Sgeoffrey.blake@arm.com 938889Sgeoffrey.blake@arm.com BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned 948889Sgeoffrey.blake@arm.com 958889Sgeoffrey.blake@arm.com WordBytes = 4, 968889Sgeoffrey.blake@arm.com HalfwordBytes = 2, 979348SAli.Saidi@ARM.com ByteBytes = 1, 989265SAli.Saidi@ARM.com DepNA = 0, 998889Sgeoffrey.blake@arm.com }; 1008889Sgeoffrey.blake@arm.com 1018889Sgeoffrey.blake@arm.com // These enumerate all the registers for dependence tracking. 1028889Sgeoffrey.blake@arm.com enum DependenceTags { 1038889Sgeoffrey.blake@arm.com // 0..31 are the integer regs 0..31 1048889Sgeoffrey.blake@arm.com // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 1058889Sgeoffrey.blake@arm.com FP_Base_DepTag = 32, 1068889Sgeoffrey.blake@arm.com Ctrl_Base_DepTag = 64, 1078889Sgeoffrey.blake@arm.com Fpcr_DepTag = 64, // floating point control register 1088889Sgeoffrey.blake@arm.com Uniq_DepTag = 65, 1099348SAli.Saidi@ARM.com IPR_Base_DepTag = 66 1109265SAli.Saidi@ARM.com }; 1118889Sgeoffrey.blake@arm.com 1128889Sgeoffrey.blake@arm.com typedef uint64_t IntReg; 1138889Sgeoffrey.blake@arm.com typedef IntReg IntRegFile[NumIntRegs]; 1148889Sgeoffrey.blake@arm.com 1158889Sgeoffrey.blake@arm.com // floating point register file entry type 1168889Sgeoffrey.blake@arm.com typedef union { 1178889Sgeoffrey.blake@arm.com uint64_t q; 1188889Sgeoffrey.blake@arm.com double d; 1198889Sgeoffrey.blake@arm.com } FloatReg; 1208889Sgeoffrey.blake@arm.com 1218889Sgeoffrey.blake@arm.com typedef union { 1228889Sgeoffrey.blake@arm.com uint64_t q[NumFloatRegs]; // integer qword view 1238889Sgeoffrey.blake@arm.com double d[NumFloatRegs]; // double-precision floating point view 1249348SAli.Saidi@ARM.com } FloatRegFile; 1259265SAli.Saidi@ARM.com 1268889Sgeoffrey.blake@arm.com // control register file contents 1278889Sgeoffrey.blake@arm.com typedef uint64_t MiscReg; 1288889Sgeoffrey.blake@arm.com typedef struct { 1298889Sgeoffrey.blake@arm.com uint64_t fpcr; // floating point condition codes 1308889Sgeoffrey.blake@arm.com uint64_t uniq; // process-unique register 1318889Sgeoffrey.blake@arm.com bool lock_flag; // lock flag for LL/SC 1328889Sgeoffrey.blake@arm.com Addr lock_addr; // lock address for LL/SC 1338889Sgeoffrey.blake@arm.com } MiscRegFile; 1348889Sgeoffrey.blake@arm.com 1358889Sgeoffrey.blake@arm.comextern const Addr PageShift; 1368889Sgeoffrey.blake@arm.comextern const Addr PageBytes; 1378889Sgeoffrey.blake@arm.comextern const Addr PageMask; 1388889Sgeoffrey.blake@arm.comextern const Addr PageOffset; 1398889Sgeoffrey.blake@arm.com 1409348SAli.Saidi@ARM.com#if FULL_SYSTEM 1419265SAli.Saidi@ARM.com 1428889Sgeoffrey.blake@arm.com typedef uint64_t InternalProcReg; 1438889Sgeoffrey.blake@arm.com 1448889Sgeoffrey.blake@arm.com#include "arch/mips/isa_fullsys_traits.hh" 1458889Sgeoffrey.blake@arm.com 1468889Sgeoffrey.blake@arm.com#else 1478889Sgeoffrey.blake@arm.com enum { 1488889Sgeoffrey.blake@arm.com NumInternalProcRegs = 0 1498889Sgeoffrey.blake@arm.com }; 1508889Sgeoffrey.blake@arm.com#endif 1518889Sgeoffrey.blake@arm.com 1528889Sgeoffrey.blake@arm.com enum { 1538889Sgeoffrey.blake@arm.com TotalNumRegs = 1548889Sgeoffrey.blake@arm.com NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs 1558889Sgeoffrey.blake@arm.com }; 1569265SAli.Saidi@ARM.com 1578889Sgeoffrey.blake@arm.com enum { 1588889Sgeoffrey.blake@arm.com TotalDataRegs = NumIntRegs + NumFloatRegs 1598889Sgeoffrey.blake@arm.com }; 1608889Sgeoffrey.blake@arm.com 1618889Sgeoffrey.blake@arm.com typedef union { 1628889Sgeoffrey.blake@arm.com IntReg intreg; 1638889Sgeoffrey.blake@arm.com FloatReg fpreg; 1648889Sgeoffrey.blake@arm.com MiscReg ctrlreg; 1658889Sgeoffrey.blake@arm.com } AnyReg; 1668889Sgeoffrey.blake@arm.com 1678889Sgeoffrey.blake@arm.com struct RegFile { 1689055Ssaidi@eecs.umich.edu IntRegFile intRegFile; // (signed) integer register file 1698889Sgeoffrey.blake@arm.com FloatRegFile floatRegFile; // floating point register file 1708889Sgeoffrey.blake@arm.com MiscRegFile miscRegs; // control register file 1718889Sgeoffrey.blake@arm.com Addr pc; // program counter 1728889Sgeoffrey.blake@arm.com Addr npc; // next-cycle program counter 1739265SAli.Saidi@ARM.com#if FULL_SYSTEM 1749265SAli.Saidi@ARM.com IntReg palregs[NumIntRegs]; // PAL shadow registers 1758889Sgeoffrey.blake@arm.com InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs 1768889Sgeoffrey.blake@arm.com int intrflag; // interrupt flag 1778889Sgeoffrey.blake@arm.com bool pal_shadow; // using pal_shadow registers 1788983Snate@binkert.org inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); } 1799265SAli.Saidi@ARM.com inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); } 1809348SAli.Saidi@ARM.com#endif // FULL_SYSTEM 1818983Snate@binkert.org 1828983Snate@binkert.org void serialize(std::ostream &os); 1838889Sgeoffrey.blake@arm.com void unserialize(Checkpoint *cp, const std::string §ion); 1848889Sgeoffrey.blake@arm.com }; 1858889Sgeoffrey.blake@arm.com 1868889Sgeoffrey.blake@arm.com StaticInstPtr decodeInst(MachInst); 1878889Sgeoffrey.blake@arm.com 1888889Sgeoffrey.blake@arm.com // return a no-op instruction... used for instruction fetch faults 1898889Sgeoffrey.blake@arm.com extern const MachInst NoopMachInst; 190 191 enum annotes { 192 ANNOTE_NONE = 0, 193 // An impossible number for instruction annotations 194 ITOUCH_ANNOTE = 0xffffffff, 195 }; 196 197 static inline bool isCallerSaveIntegerRegister(unsigned int reg) { 198 panic("register classification not implemented"); 199 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 200 } 201 202 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 203 panic("register classification not implemented"); 204 return (reg >= 9 && reg <= 15); 205 } 206 207 static inline bool isCallerSaveFloatRegister(unsigned int reg) { 208 panic("register classification not implemented"); 209 return false; 210 } 211 212 static inline bool isCalleeSaveFloatRegister(unsigned int reg) { 213 panic("register classification not implemented"); 214 return false; 215 } 216 217 static inline Addr alignAddress(const Addr &addr, 218 unsigned int nbytes) { 219 return (addr & ~(nbytes - 1)); 220 } 221 222 // Instruction address compression hooks 223 static inline Addr realPCToFetchPC(const Addr &addr) { 224 return addr; 225 } 226 227 static inline Addr fetchPCToRealPC(const Addr &addr) { 228 return addr; 229 } 230 231 // the size of "fetched" instructions (not necessarily the size 232 // of real instructions for PISA) 233 static inline size_t fetchInstSize() { 234 return sizeof(MachInst); 235 } 236 237 static inline MachInst makeRegisterCopy(int dest, int src) { 238 panic("makeRegisterCopy not implemented"); 239 return 0; 240 } 241 242 // Machine operations 243 244 void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 245 int regnum); 246 247 void restoreMachineReg(RegFile ®s, const AnyReg ®, 248 int regnum); 249 250#if 0 251 static void serializeSpecialRegs(const Serializable::Proxy &proxy, 252 const RegFile ®s); 253 254 static void unserializeSpecialRegs(const IniFile *db, 255 const std::string &category, 256 ConfigNode *node, 257 RegFile ®s); 258#endif 259 260 /** 261 * Function to insure ISA semantics about 0 registers. 262 * @param xc The execution context. 263 */ 264 template <class XC> 265 void zeroRegisters(XC *xc); 266 267 268//typedef MipsISA TheISA; 269 270//typedef TheISA::MachInst MachInst; 271//typedef TheISA::Addr Addr; 272//typedef TheISA::RegIndex RegIndex; 273//typedef TheISA::IntReg IntReg; 274//typedef TheISA::IntRegFile IntRegFile; 275//typedef TheISA::FloatReg FloatReg; 276//typedef TheISA::FloatRegFile FloatRegFile; 277//typedef TheISA::MiscReg MiscReg; 278//typedef TheISA::MiscRegFile MiscRegFile; 279//typedef TheISA::AnyReg AnyReg; 280//typedef TheISA::RegFile RegFile; 281 282//const int NumIntRegs = TheISA::NumIntRegs; 283//const int NumFloatRegs = TheISA::NumFloatRegs; 284//const int NumMiscRegs = TheISA::NumMiscRegs; 285//const int TotalNumRegs = TheISA::TotalNumRegs; 286//const int VMPageSize = TheISA::VMPageSize; 287//const int LogVMPageSize = TheISA::LogVMPageSize; 288//const int ZeroReg = TheISA::ZeroReg; 289//const int StackPointerReg = TheISA::StackPointerReg; 290//const int GlobalPointerReg = TheISA::GlobalPointerReg; 291//const int ReturnAddressReg = TheISA::ReturnAddressReg; 292//const int ReturnValueReg = TheISA::ReturnValueReg; 293//const int ArgumentReg0 = TheISA::ArgumentReg0; 294//const int ArgumentReg1 = TheISA::ArgumentReg1; 295//const int ArgumentReg2 = TheISA::ArgumentReg2; 296//const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt; 297const Addr MaxAddr = (Addr)-1; 298}; 299 300#if !FULL_SYSTEM 301class SyscallReturn { 302 public: 303 template <class T> 304 SyscallReturn(T v, bool s) 305 { 306 retval = (uint64_t)v; 307 success = s; 308 } 309 310 template <class T> 311 SyscallReturn(T v) 312 { 313 success = (v >= 0); 314 retval = (uint64_t)v; 315 } 316 317 ~SyscallReturn() {} 318 319 SyscallReturn& operator=(const SyscallReturn& s) { 320 retval = s.retval; 321 success = s.success; 322 return *this; 323 } 324 325 bool successful() { return success; } 326 uint64_t value() { return retval; } 327 328 329 private: 330 uint64_t retval; 331 bool success; 332}; 333 334#endif 335 336 337#if FULL_SYSTEM 338//typedef TheISA::InternalProcReg InternalProcReg; 339//const int NumInternalProcRegs = TheISA::NumInternalProcRegs; 340//const int NumInterruptLevels = TheISA::NumInterruptLevels; 341 342#include "arch/mips/mips34k.hh" 343#endif 344 345#endif // __ARCH_MIPS_ISA_TRAITS_HH__ 346