isa_traits.hh revision 2125
17860SN/A/* 27860SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 37860SN/A * All rights reserved. 48825Snilay@cs.wisc.edu * 57935SN/A * Redistribution and use in source and binary forms, with or without 67935SN/A * modification, are permitted provided that the following conditions are 77935SN/A * met: redistributions of source code must retain the above copyright 87860SN/A * notice, this list of conditions and the following disclaimer; 97860SN/A * redistributions in binary form must reproduce the above copyright 107860SN/A * notice, this list of conditions and the following disclaimer in the 117860SN/A * documentation and/or other materials provided with the distribution; 128825Snilay@cs.wisc.edu * neither the name of the copyright holders nor the names of its 138825Snilay@cs.wisc.edu * contributors may be used to endorse or promote products derived from 148825Snilay@cs.wisc.edu * this software without specific prior written permission. 158825Snilay@cs.wisc.edu * 167860SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 178464SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 188721SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197860SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 208825Snilay@cs.wisc.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 218825Snilay@cs.wisc.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227935SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237935SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247935SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257935SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267935SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277935SN/A */ 287935SN/A 298721SN/A#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 307860SN/A#define __ARCH_MIPS_ISA_TRAITS_HH__ 317860SN/A 327860SN/A//This makes sure the big endian versions of certain functions are used. 338825Snilay@cs.wisc.edunamespace LittleEndianGuest {} 347860SN/Ausing namespace LittleEndianGuest 357860SN/A 367860SN/A#include "arch/mips/faults.hh" 377860SN/A#include "base/misc.hh" 388210SN/A#include "sim/host.hh" 398210SN/A 407860SN/Aclass FastCPU; 417860SN/Aclass FullCPU; 427860SN/Aclass Checkpoint; 437860SN/A 447860SN/A#define TARGET_MIPS 457860SN/A 467860SN/Atemplate <class ISA> class StaticInst; 477860SN/Atemplate <class ISA> class StaticInstPtr; 487860SN/A 497860SN/A//namespace MIPS34K 507860SN/A//{ 517860SN/A// int DTB_ASN_ASN(uint64_t reg); 527860SN/A// int ITB_ASN_ASN(uint64_t reg); 537860SN/A//} 547860SN/A 557860SN/Aclass MipsISA 567860SN/A{ 577860SN/A public: 587860SN/A 597860SN/A typedef uint32_t MachInst; 607860SN/A typedef uint64_t Addr; 617860SN/A typedef uint8_t RegIndex; 628825Snilay@cs.wisc.edu 637860SN/A enum 647860SN/A { 657860SN/A MemoryEnd = 0xffffffffffffffffULL, 667860SN/A 677860SN/A NumFloatRegs = 32, 687860SN/A NumMiscRegs = 32, 697860SN/A 707860SN/A MaxRegsOfAnyType = 32, 717860SN/A // Static instruction parameters 727860SN/A MaxInstSrcRegs = 3, 737860SN/A MaxInstDestRegs = 2, 747860SN/A 757860SN/A // Maximum trap level 767860SN/A MaxTL = 4 777860SN/A 787860SN/A // semantically meaningful register indices 797860SN/A ZeroReg = 0, // architecturally meaningful 808825Snilay@cs.wisc.edu // the rest of these depend on the ABI 817860SN/A } 827860SN/A typedef uint64_t IntReg; 837860SN/A 847860SN/A class IntRegFile 857860SN/A { 867860SN/A private: 877860SN/A //For right now, let's pretend the register file is static 887860SN/A IntReg regs[32]; 897860SN/A public: 907860SN/A IntReg & operator [] (RegIndex index) 917860SN/A { 928825Snilay@cs.wisc.edu //Don't allow indexes outside of the 32 registers 937860SN/A index &= 0x1F 947860SN/A return regs[index]; 957860SN/A } 967860SN/A }; 977860SN/A 987860SN/A void inline serialize(std::ostream & os) 997860SN/A { 1007860SN/A SERIALIZE_ARRAY(regs, 32); 1018825Snilay@cs.wisc.edu } 1027860SN/A 1037860SN/A void inline unserialize(Checkpoint &*cp, const std::string §ion) 1047860SN/A { 1057860SN/A UNSERIALIZE_ARRAY(regs, 32); 1067860SN/A } 1077860SN/A 1087860SN/A class FloatRegFile 1097860SN/A { 1107860SN/A private: 1117860SN/A //By using the largest data type, we ensure everything 1127860SN/A //is aligned correctly in memory 1137860SN/A union 1147860SN/A { 1157860SN/A double double rawRegs[16]; 1167860SN/A uint64_t regDump[32]; 1177860SN/A }; 1188521SN/A class QuadRegs 1197860SN/A { 1207860SN/A private: 1217860SN/A FloatRegFile * parent; 1227860SN/A public: 1237860SN/A QuadRegs(FloatRegFile * p) : parent(p) {;} 1247860SN/A double double & operator [] (RegIndex index) 1257860SN/A { 1267860SN/A //Quad floats are index by the single 1277860SN/A //precision register the start on, 1287860SN/A //and only 16 should be accessed 1297860SN/A index = (index >> 2) & 0xF; 1307860SN/A return parent->rawRegs[index]; 1317860SN/A } 1327860SN/A }; 1337860SN/A class DoubleRegs 1347860SN/A { 1358150SN/A private: 1367860SN/A FloatRegFile * parent; 1377860SN/A public: 1387860SN/A DoubleRegs(FloatRegFile * p) : parent(p) {;} 1397860SN/A double & operator [] (RegIndex index) 1408835SAli.Saidi@ARM.com { 1417860SN/A //Double floats are index by the single 1427860SN/A //precision register the start on, 1437860SN/A //and only 32 should be accessed 1447860SN/A index = (index >> 1) & 0x1F 1458835SAli.Saidi@ARM.com return ((double [])parent->rawRegs)[index]; 1467860SN/A } 1477860SN/A } 1487860SN/A class SingleRegs 1497860SN/A { 1507860SN/A private: 1517860SN/A FloatRegFile * parent; 1527860SN/A public: 1537860SN/A SingleRegs(FloatRegFile * p) : parent(p) {;} 1547860SN/A double & operator [] (RegFile index) 1558825Snilay@cs.wisc.edu { 1567860SN/A //Only 32 single floats should be accessed 1578825Snilay@cs.wisc.edu index &= 0x1F 1588825Snilay@cs.wisc.edu return ((float [])parent->rawRegs)[index]; 1598825Snilay@cs.wisc.edu } 1608825Snilay@cs.wisc.edu } 1618825Snilay@cs.wisc.edu public: 1628825Snilay@cs.wisc.edu void inline serialize(std::ostream & os) 1638825Snilay@cs.wisc.edu { 1648825Snilay@cs.wisc.edu SERIALIZE_ARRAY(regDump, 32); 1657860SN/A } 1667860SN/A 1677860SN/A void inline unserialize(Checkpoint &* cp, std::string & section) 1687860SN/A { 1697860SN/A UNSERIALIZE_ARRAY(regDump, 32); 1707860SN/A } 1717860SN/A 1727860SN/A QuadRegs quadRegs; 1737860SN/A DoubleRegs doubleRegs; 1747860SN/A SingleRegs singleRegs; 1757860SN/A FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this) 1767860SN/A {;} 1777860SN/A }; 1787860SN/A 1797860SN/A // control register file contents 1807860SN/A typedef uint64_t MiscReg; 1817860SN/A // The control registers, broken out into fields 1827860SN/A class MiscRegFile 1837860SN/A { 1847860SN/A public: 1857860SN/A union 1867860SN/A { 1877860SN/A uint16_t pstate; // Process State Register 1887860SN/A struct 1897860SN/A { 1907860SN/A uint16_t ag:1; // Alternate Globals 1917860SN/A uint16_t ie:1; // Interrupt enable 1927860SN/A uint16_t priv:1; // Privelege mode 1937860SN/A uint16_t am:1; // Address mask 1947860SN/A uint16_t pef:1; // PSTATE enable floating-point 1957860SN/A uint16_t red:1; // RED (reset, error, debug) state 1967860SN/A uint16_t mm:2; // Memory Model 1977860SN/A uint16_t tle:1; // Trap little-endian 1987860SN/A uint16_t cle:1; // Current little-endian 1997860SN/A } pstateFields; 2007860SN/A } 2017860SN/A uint64_t tba; // Trap Base Address 2027860SN/A union 2037860SN/A { 2047860SN/A uint64_t y; // Y (used in obsolete multiplication) 2057860SN/A struct 2067860SN/A { 2077860SN/A uint64_t value:32; // The actual value stored in y 2087860SN/A const uint64_t :32; // reserved bits 2097860SN/A } yFields; 2107860SN/A } 2117860SN/A uint8_t pil; // Process Interrupt Register 2127860SN/A uint8_t cwp; // Current Window Pointer 2137860SN/A uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured on the previous level) 2147860SN/A union 2157860SN/A { 2167860SN/A uint8_t ccr; // Condition Code Register 2177860SN/A struct 2187860SN/A { 2197860SN/A union 2207860SN/A { 2217860SN/A uint8_t icc:4; // 32-bit condition codes 2227860SN/A struct 2237860SN/A { 2247860SN/A uint8_t c:1; // Carry 2257860SN/A uint8_t v:1; // Overflow 2267860SN/A uint8_t z:1; // Zero 2277860SN/A uint8_t n:1; // Negative 2287860SN/A } iccFields:4; 2297860SN/A } :4; 2307860SN/A union 2317860SN/A { 2327860SN/A uint8_t xcc:4; // 64-bit condition codes 2337860SN/A struct 2347860SN/A { 2357860SN/A uint8_t c:1; // Carry 2367860SN/A uint8_t v:1; // Overflow 2377860SN/A uint8_t z:1; // Zero 2387860SN/A uint8_t n:1; // Negative 2397860SN/A } xccFields:4; 2407860SN/A } :4; 2417860SN/A } ccrFields; 2427860SN/A } 2437860SN/A uint8_t asi; // Address Space Identifier 2447860SN/A uint8_t tl; // Trap Level 2457860SN/A uint64_t tpc[MaxTL]; // Trap Program Counter (value from previous trap level) 2467860SN/A uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from previous trap level) 2477860SN/A union 2487860SN/A { 2497860SN/A uint64_t tstate[MaxTL]; // Trap State 2507860SN/A struct 2517860SN/A { 2527860SN/A //Values are from previous trap level 2537860SN/A uint64_t cwp:5; // Current Window Pointer 2547860SN/A const uint64_t :2; // Reserved bits 2557860SN/A uint64_t pstate:10; // Process State 2567860SN/A const uint64_t :6; // Reserved bits 2577860SN/A uint64_t asi:8; // Address Space Identifier 2587860SN/A uint64_t ccr:8; // Condition Code Register 2597860SN/A } tstateFields[MaxTL]; 2607860SN/A } 2617860SN/A union 2627860SN/A { 2637860SN/A uint64_t tick; // Hardware clock-tick counter 2647860SN/A struct 2657860SN/A { 2667860SN/A uint64_t counter:63; // Clock-tick count 2677860SN/A uint64_t npt:1; // Non-priveleged trap 2687860SN/A } tickFields; 2697860SN/A } 2707860SN/A uint8_t cansave; // Savable windows 2717860SN/A uint8_t canrestore; // Restorable windows 2727860SN/A uint8_t otherwin; // Other windows 2737860SN/A uint8_t cleanwin; // Clean windows 2747860SN/A union 2757860SN/A { 2767860SN/A uint8_t wstate; // Window State 2777860SN/A struct 2787860SN/A { 2797860SN/A uint8_t normal:3; // Bits TT<4:2> are set to on a normal 2807860SN/A // register window trap 2817860SN/A uint8_t other:3; // Bits TT<4:2> are set to on an "otherwin" 2827860SN/A // register window trap 2837860SN/A } wstateFields; 2847860SN/A } 2857860SN/A union 2867860SN/A { 2877860SN/A uint64_t ver; // Version 2887860SN/A struct 2897860SN/A { 2907860SN/A uint64_t maxwin:5; // Max CWP value 2917860SN/A const uint64_t :2; // Reserved bits 2927860SN/A uint64_t maxtl:8; // Maximum trap level 2937860SN/A const uint64_t :8; // Reserved bits 2947860SN/A uint64_t mask:8; // Processor mask set revision number 2957860SN/A uint64_t impl:16; // Implementation identification number 2967860SN/A uint64_t manuf:16; // Manufacturer code 2977860SN/A } verFields; 2987860SN/A } 2997860SN/A union 3007860SN/A { 3017860SN/A uint64_t fsr; // Floating-Point State Register 3027860SN/A struct 3037860SN/A { 3047860SN/A union 3057860SN/A { 3067860SN/A uint64_t cexc:5; // Current excpetion 3077860SN/A struct 3087860SN/A { 3097860SN/A uint64_t nxc:1; // Inexact 3107860SN/A uint64_t dzc:1; // Divide by zero 3117860SN/A uint64_t ufc:1; // Underflow 3127860SN/A uint64_t ofc:1; // Overflow 3137860SN/A uint64_t nvc:1; // Invalid operand 3147860SN/A } cexecFields:5; 3157860SN/A } :5; 3167860SN/A union 3177860SN/A { 3187860SN/A uint64_t aexc:5; // Accrued exception 3197860SN/A struct 3207860SN/A { 3217860SN/A uint64_t nxc:1; // Inexact 3227860SN/A uint64_t dzc:1; // Divide by zero 3237860SN/A uint64_t ufc:1; // Underflow 3247860SN/A uint64_t ofc:1; // Overflow 3257860SN/A uint64_t nvc:1; // Invalid operand 3267860SN/A } aexecFields:5; 3277860SN/A } :5; 3287860SN/A uint64_t fcc0:2; // Floating-Point condtion codes 3297860SN/A const uint64_t :1; // Reserved bits 3307860SN/A uint64_t qne:1; // Deferred trap queue not empty 3317860SN/A // with no queue, it should read 0 3327860SN/A uint64_t ftt:3; // Floating-Point trap type 3337860SN/A uint64_t ver:3; // Version (of the FPU) 3347860SN/A const uint64_t :2; // Reserved bits 3357860SN/A uint64_t ns:1; // Nonstandard floating point 3367860SN/A union 3377860SN/A { 3387860SN/A uint64_t tem:5; // Trap Enable Mask 3397860SN/A struct 3407860SN/A { 3417860SN/A uint64_t nxm:1; // Inexact 3427860SN/A uint64_t dzm:1; // Divide by zero 3437860SN/A uint64_t ufm:1; // Underflow 3447860SN/A uint64_t ofm:1; // Overflow 3457860SN/A uint64_t nvm:1; // Invalid operand 3467860SN/A } temFields:5; 3477860SN/A } :5; 3487860SN/A const uint64_t :2; // Reserved bits 3497860SN/A uint64_t rd:2; // Rounding direction 3507860SN/A uint64_t fcc1:2; // Floating-Point condition codes 3517860SN/A uint64_t fcc2:2; // Floating-Point condition codes 3527860SN/A uint64_t fcc3:2; // Floating-Point condition codes 3537860SN/A const uint64_t :26; // Reserved bits 3547860SN/A } fsrFields; 3557860SN/A } 3567860SN/A union 3577860SN/A { 3587860SN/A uint8_t fprs; // Floating-Point Register State 3597860SN/A struct 3607860SN/A { 3617860SN/A dl:1; // Dirty lower 3627860SN/A du:1; // Dirty upper 3637860SN/A fef:1; // FPRS enable floating-Point 3647860SN/A } fprsFields; 3657860SN/A }; 3667860SN/A 3677860SN/A void serialize(std::ostream & os) 3687860SN/A { 3697860SN/A SERIALIZE_SCALAR(pstate); 3707860SN/A SERIAlIZE_SCALAR(tba); 3717860SN/A SERIALIZE_SCALAR(y); 3727860SN/A SERIALIZE_SCALAR(pil); 3737860SN/A SERIALIZE_SCALAR(cwp); 3747860SN/A SERIALIZE_ARRAY(tt, MaxTL); 3757860SN/A SERIALIZE_SCALAR(ccr); 3767860SN/A SERIALIZE_SCALAR(asi); 3777860SN/A SERIALIZE_SCALAR(tl); 3787860SN/A SERIALIZE_SCALAR(tpc); 3797860SN/A SERIALIZE_SCALAR(tnpc); 3807860SN/A SERIALIZE_ARRAY(tstate, MaxTL); 3817860SN/A SERIALIZE_SCALAR(tick); 3827860SN/A SERIALIZE_SCALAR(cansave); 3837860SN/A SERIALIZE_SCALAR(canrestore); 3847860SN/A SERIALIZE_SCALAR(otherwin); 3857860SN/A SERIALIZE_SCALAR(cleanwin); 3867860SN/A SERIALIZE_SCALAR(wstate); 3877860SN/A SERIALIZE_SCALAR(ver); 3887860SN/A SERIALIZE_SCALAR(fsr); 3897860SN/A SERIALIZE_SCALAR(fprs); 3907860SN/A } 3917860SN/A 3927860SN/A void unserialize(Checkpoint &* cp, std::string & section) 3937860SN/A { 3947860SN/A UNSERIALIZE_SCALAR(pstate); 3957860SN/A UNSERIAlIZE_SCALAR(tba); 3967860SN/A UNSERIALIZE_SCALAR(y); 3977860SN/A UNSERIALIZE_SCALAR(pil); 3987860SN/A UNSERIALIZE_SCALAR(cwp); 3997860SN/A UNSERIALIZE_ARRAY(tt, MaxTL); 4007860SN/A UNSERIALIZE_SCALAR(ccr); 4017860SN/A UNSERIALIZE_SCALAR(asi); 4027860SN/A UNSERIALIZE_SCALAR(tl); 4037860SN/A UNSERIALIZE_SCALAR(tpc); 4047860SN/A UNSERIALIZE_SCALAR(tnpc); 4057860SN/A UNSERIALIZE_ARRAY(tstate, MaxTL); 4067860SN/A UNSERIALIZE_SCALAR(tick); 4077860SN/A UNSERIALIZE_SCALAR(cansave); 4087860SN/A UNSERIALIZE_SCALAR(canrestore); 4097860SN/A UNSERIALIZE_SCALAR(otherwin); 4107860SN/A UNSERIALIZE_SCALAR(cleanwin); 4117860SN/A UNSERIALIZE_SCALAR(wstate); 4127860SN/A UNSERIALIZE_SCALAR(ver); 4137860SN/A UNSERIALIZE_SCALAR(fsr); 4147860SN/A UNSERIALIZE_SCALAR(fprs); 4157860SN/A } 4167860SN/A }; 4177860SN/A 4187860SN/A typedef union 4197860SN/A { 4207860SN/A IntReg intreg; 4217860SN/A FloatReg fpreg; 4227860SN/A MiscReg ctrlreg; 4237860SN/A } AnyReg; 4247860SN/A 4257860SN/A struct RegFile 4267860SN/A { 4277860SN/A IntRegFile intRegFile; // (signed) integer register file 4287860SN/A FloatRegFile floatRegFile; // floating point register file 4297860SN/A MiscRegFile miscRegFile; // control register file 4307860SN/A 4317860SN/A Addr pc; // Program Counter 4327860SN/A Addr npc; // Next Program Counter 4337860SN/A Addr nnpc; // Next next program Counter 4347860SN/A 4357860SN/A 4368150SN/A void serialize(std::ostream &os); 4377860SN/A void unserialize(Checkpoint *cp, const std::string §ion); 4387860SN/A }; 4397860SN/A 4407860SN/A static StaticInstPtr<MipsISA> decodeInst(MachInst); 4418835SAli.Saidi@ARM.com 4427860SN/A // return a no-op instruction... used for instruction fetch faults 4437860SN/A static const MachInst NoopMachInst; 4447860SN/A 4457860SN/A // Instruction address compression hooks 4468835SAli.Saidi@ARM.com static inline Addr realPCToFetchPC(const Addr &addr) 4477860SN/A { 4487860SN/A return addr; 4497860SN/A } 4507860SN/A 4517860SN/A static inline Addr fetchPCToRealPC(const Addr &addr) 4527860SN/A { 4537860SN/A return addr; 4548825Snilay@cs.wisc.edu } 4558825Snilay@cs.wisc.edu 4568825Snilay@cs.wisc.edu // the size of "fetched" instructions (not necessarily the size 4577860SN/A // of real instructions for PISA) 4587860SN/A static inline size_t fetchInstSize() 4598825Snilay@cs.wisc.edu { 4607860SN/A return sizeof(MachInst); 4618825Snilay@cs.wisc.edu } 4628825Snilay@cs.wisc.edu 4638825Snilay@cs.wisc.edu /** 4648825Snilay@cs.wisc.edu * Function to insure ISA semantics about 0 registers. 4658825Snilay@cs.wisc.edu * @param xc The execution context. 4668825Snilay@cs.wisc.edu */ 4678825Snilay@cs.wisc.edu template <class XC> 4688825Snilay@cs.wisc.edu static void zeroRegisters(XC *xc); 4697860SN/A}; 4707860SN/A 4717860SN/A 4727860SN/Atypedef MIPSISA TheISA; 4737860SN/A 4747860SN/Atypedef TheISA::MachInst MachInst; 4757860SN/Atypedef TheISA::Addr Addr; 4767860SN/Atypedef TheISA::RegIndex RegIndex; 4778150SN/Atypedef TheISA::IntReg IntReg; 4787860SN/Atypedef TheISA::IntRegFile IntRegFile; 4797860SN/Atypedef TheISA::FloatReg FloatReg; 4807860SN/Atypedef TheISA::FloatRegFile FloatRegFile; 4817860SN/Atypedef TheISA::MiscReg MiscReg; 4828835SAli.Saidi@ARM.comtypedef TheISA::MiscRegFile MiscRegFile; 4837860SN/Atypedef TheISA::AnyReg AnyReg; 4847860SN/Atypedef TheISA::RegFile RegFile; 4857860SN/A 4867860SN/Aconst int VMPageSize = TheISA::VMPageSize; 4878835SAli.Saidi@ARM.comconst int LogVMPageSize = TheISA::LogVMPageSize; 4887860SN/Aconst int ZeroReg = TheISA::ZeroReg; 4897860SN/Aconst int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt; 4907860SN/Aconst int MaxAddr = (Addr)-1; 4917860SN/A 4928825Snilay@cs.wisc.edu#ifndef FULL_SYSTEM 4938721SN/Aclass SyscallReturn { 4947860SN/A public: 4957860SN/A template <class T> 4967860SN/A SyscallReturn(T v, bool s) 4977860SN/A { 4987860SN/A retval = (uint64_t)v; 4997860SN/A success = s; 5007860SN/A } 5017860SN/A 5027860SN/A template <class T> 5038825Snilay@cs.wisc.edu SyscallReturn(T v) 5047860SN/A { 5057860SN/A success = (v >= 0); 5067860SN/A retval = (uint64_t)v; 5077860SN/A } 5087860SN/A 5097860SN/A ~SyscallReturn() {} 5107860SN/A 5118835SAli.Saidi@ARM.com SyscallReturn& operator=(const SyscallReturn& s) { 5127860SN/A retval = s.retval; 5137860SN/A success = s.success; 5147860SN/A return *this; 5157860SN/A } 5168835SAli.Saidi@ARM.com 5177860SN/A bool successful() { return success; } 5187860SN/A uint64_t value() { return retval; } 5197860SN/A 5207860SN/A 5217860SN/A private: 5227860SN/A uint64_t retval; 5237860SN/A bool success; 5247860SN/A}; 5257860SN/A 5267860SN/A#endif 5277860SN/A 5287860SN/A 5297860SN/A#ifdef FULL_SYSTEM 5307860SN/A 5317860SN/A#include "arch/mips/mips34k.hh" 5327860SN/A#endif 5337860SN/A 5347860SN/A#endif // __ARCH_MIPS_ISA_TRAITS_HH__ 5358721SN/A