util.isa revision 5222
12100SN/A// -*- mode:c++ -*- 22100SN/A 35222Sksewell@umich.edu// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved 45222Sksewell@umich.edu 55222Sksewell@umich.edu// This software is part of the M5 simulator. 65222Sksewell@umich.edu 75222Sksewell@umich.edu// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING 85222Sksewell@umich.edu// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING 95222Sksewell@umich.edu// TO THESE TERMS AND CONDITIONS. 105222Sksewell@umich.edu 115222Sksewell@umich.edu// Permission is granted to use, copy, create derivative works and 125222Sksewell@umich.edu// distribute this software and such derivative works for any purpose, 135222Sksewell@umich.edu// so long as (1) the copyright notice above, this grant of permission, 145222Sksewell@umich.edu// and the disclaimer below appear in all copies and derivative works 155222Sksewell@umich.edu// made, (2) the copyright notice above is augmented as appropriate to 165222Sksewell@umich.edu// reflect the addition of any new copyrightable work in a derivative 175222Sksewell@umich.edu// work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3) 185222Sksewell@umich.edu// the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any 195222Sksewell@umich.edu// advertising or publicity pertaining to the use or distribution of 205222Sksewell@umich.edu// this software without specific, written prior authorization. 215222Sksewell@umich.edu 225222Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND 235222Sksewell@umich.edu// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 245222Sksewell@umich.edu// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 255222Sksewell@umich.edu// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 265222Sksewell@umich.edu// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 275222Sksewell@umich.edu// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 285222Sksewell@umich.edu// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 295222Sksewell@umich.edu// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 305222Sksewell@umich.edu// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 315222Sksewell@umich.edu// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 325222Sksewell@umich.edu// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 335222Sksewell@umich.edu// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 345222Sksewell@umich.edu 355222Sksewell@umich.edu//Authors: Steven K. Reinhardt 365222Sksewell@umich.edu// Korey L. Sewell 372706Sksewell@umich.edu 382100SN/Alet {{ 392124SN/Adef LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 402124SN/A postacc_code = '', base_class = 'Memory', 412124SN/A decode_template = BasicDecode, exec_template_base = ''): 422124SN/A # Make sure flags are in lists (convert to lists if not). 432124SN/A mem_flags = makeList(mem_flags) 442124SN/A inst_flags = makeList(inst_flags) 452124SN/A 462124SN/A # add hook to get effective addresses into execution trace output. 472124SN/A ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n' 482124SN/A 492124SN/A # Some CPU models execute the memory operation as an atomic unit, 502124SN/A # while others want to separate them into an effective address 512124SN/A # computation and a memory access operation. As a result, we need 522124SN/A # to generate three StaticInst objects. Note that the latter two 532124SN/A # are nested inside the larger "atomic" one. 542124SN/A 553953Sstever@eecs.umich.edu # Generate InstObjParams for each of the three objects. Note that 563953Sstever@eecs.umich.edu # they differ only in the set of code objects contained (which in 573953Sstever@eecs.umich.edu # turn affects the object's overall operand list). 583953Sstever@eecs.umich.edu iop = InstObjParams(name, Name, base_class, 593953Sstever@eecs.umich.edu { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code }, 603953Sstever@eecs.umich.edu inst_flags) 613953Sstever@eecs.umich.edu ea_iop = InstObjParams(name, Name, base_class, 623953Sstever@eecs.umich.edu { 'ea_code':ea_code }, 633953Sstever@eecs.umich.edu inst_flags) 643953Sstever@eecs.umich.edu memacc_iop = InstObjParams(name, Name, base_class, 653953Sstever@eecs.umich.edu { 'memacc_code':memacc_code, 'postacc_code':postacc_code }, 663953Sstever@eecs.umich.edu inst_flags) 672124SN/A 682124SN/A if mem_flags: 692124SN/A s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' 702124SN/A iop.constructor += s 712124SN/A memacc_iop.constructor += s 722124SN/A 732124SN/A # select templates 742935Sksewell@umich.edu 754056Sstever@eecs.umich.edu # The InitiateAcc template is the same for StoreCond templates as the 764056Sstever@eecs.umich.edu # corresponding Store template.. 772935Sksewell@umich.edu StoreCondInitiateAcc = StoreInitiateAcc 782935Sksewell@umich.edu 792124SN/A memAccExecTemplate = eval(exec_template_base + 'MemAccExecute') 802124SN/A fullExecTemplate = eval(exec_template_base + 'Execute') 812124SN/A initiateAccTemplate = eval(exec_template_base + 'InitiateAcc') 822124SN/A completeAccTemplate = eval(exec_template_base + 'CompleteAcc') 835222Sksewell@umich.edu eaCompExecuteTemplate = eval('EACompExecute') 845222Sksewell@umich.edu 855222Sksewell@umich.edu if (exec_template_base == 'Load' or exec_template_base == 'Store'): 865222Sksewell@umich.edu memAccSizeTemplate = eval('LoadStoreMemAccSize') 875222Sksewell@umich.edu else: 885222Sksewell@umich.edu memAccSizeTemplate = eval('MiscMemAccSize') 892124SN/A 902124SN/A # (header_output, decoder_output, decode_block, exec_output) 913953Sstever@eecs.umich.edu return (LoadStoreDeclare.subst(iop), 923953Sstever@eecs.umich.edu EACompConstructor.subst(ea_iop) 933953Sstever@eecs.umich.edu + MemAccConstructor.subst(memacc_iop) 943953Sstever@eecs.umich.edu + LoadStoreConstructor.subst(iop), 952124SN/A decode_template.subst(iop), 965222Sksewell@umich.edu eaCompExecuteTemplate.subst(ea_iop) 972124SN/A + memAccExecTemplate.subst(memacc_iop) 982124SN/A + fullExecTemplate.subst(iop) 993953Sstever@eecs.umich.edu + initiateAccTemplate.subst(iop) 1005222Sksewell@umich.edu + completeAccTemplate.subst(iop) 1015222Sksewell@umich.edu + memAccSizeTemplate.subst(memacc_iop)) 1022100SN/A}}; 1033953Sstever@eecs.umich.edu 1042686Sksewell@umich.eduoutput header {{ 1052686Sksewell@umich.edu std::string inst2string(MachInst machInst); 1062686Sksewell@umich.edu}}; 1072124SN/A 1082686Sksewell@umich.eduoutput decoder {{ 1092686Sksewell@umich.edu 1102686Sksewell@umich.edustd::string inst2string(MachInst machInst) 1112686Sksewell@umich.edu{ 1124661Sksewell@umich.edu string str = ""; 1132686Sksewell@umich.edu uint32_t mask = 0x80000000; 1142686Sksewell@umich.edu 1152686Sksewell@umich.edu for(int i=0; i < 32; i++) { 1162686Sksewell@umich.edu if ((machInst & mask) == 0) { 1172686Sksewell@umich.edu str += "0"; 1182686Sksewell@umich.edu } else { 1192686Sksewell@umich.edu str += "1"; 1202686Sksewell@umich.edu } 1212686Sksewell@umich.edu 1222686Sksewell@umich.edu mask = mask >> 1; 1232686Sksewell@umich.edu } 1242686Sksewell@umich.edu 1252686Sksewell@umich.edu return str; 1262686Sksewell@umich.edu} 1272686Sksewell@umich.edu 1282686Sksewell@umich.edu}}; 129