util.isa revision 5222
15361Srstrong@cs.ucsd.edu// -*- mode:c++ -*- 23671Sbinkertn@umich.edu 33671Sbinkertn@umich.edu// Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved 43671Sbinkertn@umich.edu 53671Sbinkertn@umich.edu// This software is part of the M5 simulator. 63671Sbinkertn@umich.edu 73671Sbinkertn@umich.edu// THIS IS A LEGAL AGREEMENT. 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($B!H(BMIPS$B!I(B) is not used in any 193671Sbinkertn@umich.edu// advertising or publicity pertaining to the use or distribution of 203671Sbinkertn@umich.edu// this software without specific, written prior authorization. 213671Sbinkertn@umich.edu 223671Sbinkertn@umich.edu// THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND 233671Sbinkertn@umich.edu// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 243671Sbinkertn@umich.edu// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 253671Sbinkertn@umich.edu// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 263671Sbinkertn@umich.edu// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 273671Sbinkertn@umich.edu// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 283671Sbinkertn@umich.edu// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 293671Sbinkertn@umich.edu// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 303671Sbinkertn@umich.edu// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 313671Sbinkertn@umich.edu// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 323671Sbinkertn@umich.edu// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 333671Sbinkertn@umich.edu// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 346028Ssteve.reinhardt@amd.com 353671Sbinkertn@umich.edu//Authors: Steven K. Reinhardt 363671Sbinkertn@umich.edu// Korey L. Sewell 373671Sbinkertn@umich.edu 383671Sbinkertn@umich.edulet {{ 393671Sbinkertn@umich.edudef LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 403671Sbinkertn@umich.edu postacc_code = '', base_class = 'Memory', 413671Sbinkertn@umich.edu decode_template = BasicDecode, exec_template_base = ''): 423671Sbinkertn@umich.edu # Make sure flags are in lists (convert to lists if not). 433671Sbinkertn@umich.edu mem_flags = makeList(mem_flags) 443671Sbinkertn@umich.edu inst_flags = makeList(inst_flags) 453671Sbinkertn@umich.edu 463671Sbinkertn@umich.edu # add hook to get effective addresses into execution trace output. 473671Sbinkertn@umich.edu ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n' 483671Sbinkertn@umich.edu 493671Sbinkertn@umich.edu # Some CPU models execute the memory operation as an atomic unit, 503671Sbinkertn@umich.edu # while others want to separate them into an effective address 513671Sbinkertn@umich.edu # computation and a memory access operation. As a result, we need 523671Sbinkertn@umich.edu # to generate three StaticInst objects. Note that the latter two 533671Sbinkertn@umich.edu # are nested inside the larger "atomic" one. 543671Sbinkertn@umich.edu 553671Sbinkertn@umich.edu # Generate InstObjParams for each of the three objects. Note that 563671Sbinkertn@umich.edu # they differ only in the set of code objects contained (which in 573671Sbinkertn@umich.edu # turn affects the object's overall operand list). 583671Sbinkertn@umich.edu iop = InstObjParams(name, Name, base_class, 593671Sbinkertn@umich.edu { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code }, 603671Sbinkertn@umich.edu inst_flags) 613671Sbinkertn@umich.edu ea_iop = InstObjParams(name, Name, base_class, 623671Sbinkertn@umich.edu { 'ea_code':ea_code }, 633671Sbinkertn@umich.edu inst_flags) 643671Sbinkertn@umich.edu memacc_iop = InstObjParams(name, Name, base_class, 653671Sbinkertn@umich.edu { 'memacc_code':memacc_code, 'postacc_code':postacc_code }, 663671Sbinkertn@umich.edu inst_flags) 673671Sbinkertn@umich.edu 683671Sbinkertn@umich.edu if mem_flags: 693671Sbinkertn@umich.edu s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' 703671Sbinkertn@umich.edu iop.constructor += s 713671Sbinkertn@umich.edu memacc_iop.constructor += s 723671Sbinkertn@umich.edu 733671Sbinkertn@umich.edu # select templates 743671Sbinkertn@umich.edu 753671Sbinkertn@umich.edu # The InitiateAcc template is the same for StoreCond templates as the 763671Sbinkertn@umich.edu # corresponding Store template.. 773671Sbinkertn@umich.edu StoreCondInitiateAcc = StoreInitiateAcc 783671Sbinkertn@umich.edu 793671Sbinkertn@umich.edu memAccExecTemplate = eval(exec_template_base + 'MemAccExecute') 803671Sbinkertn@umich.edu fullExecTemplate = eval(exec_template_base + 'Execute') 813671Sbinkertn@umich.edu initiateAccTemplate = eval(exec_template_base + 'InitiateAcc') 823671Sbinkertn@umich.edu completeAccTemplate = eval(exec_template_base + 'CompleteAcc') 833671Sbinkertn@umich.edu eaCompExecuteTemplate = eval('EACompExecute') 843671Sbinkertn@umich.edu 853671Sbinkertn@umich.edu if (exec_template_base == 'Load' or exec_template_base == 'Store'): 863671Sbinkertn@umich.edu memAccSizeTemplate = eval('LoadStoreMemAccSize') 873671Sbinkertn@umich.edu else: 885361Srstrong@cs.ucsd.edu memAccSizeTemplate = eval('MiscMemAccSize') 895361Srstrong@cs.ucsd.edu 905361Srstrong@cs.ucsd.edu # (header_output, decoder_output, decode_block, exec_output) 913671Sbinkertn@umich.edu return (LoadStoreDeclare.subst(iop), 923671Sbinkertn@umich.edu EACompConstructor.subst(ea_iop) 933671Sbinkertn@umich.edu + MemAccConstructor.subst(memacc_iop) 943671Sbinkertn@umich.edu + LoadStoreConstructor.subst(iop), 953671Sbinkertn@umich.edu decode_template.subst(iop), 963671Sbinkertn@umich.edu eaCompExecuteTemplate.subst(ea_iop) 973671Sbinkertn@umich.edu + memAccExecTemplate.subst(memacc_iop) 983671Sbinkertn@umich.edu + fullExecTemplate.subst(iop) 993671Sbinkertn@umich.edu + initiateAccTemplate.subst(iop) 1003671Sbinkertn@umich.edu + completeAccTemplate.subst(iop) 1013671Sbinkertn@umich.edu + memAccSizeTemplate.subst(memacc_iop)) 1023671Sbinkertn@umich.edu}}; 1033671Sbinkertn@umich.edu 1043671Sbinkertn@umich.eduoutput header {{ 1053671Sbinkertn@umich.edu std::string inst2string(MachInst machInst); 1063671Sbinkertn@umich.edu}}; 1073671Sbinkertn@umich.edu 1083671Sbinkertn@umich.eduoutput decoder {{ 1093671Sbinkertn@umich.edu 1104116Sgblack@eecs.umich.edustd::string inst2string(MachInst machInst) 1114116Sgblack@eecs.umich.edu{ 1123671Sbinkertn@umich.edu string str = ""; 1133671Sbinkertn@umich.edu uint32_t mask = 0x80000000; 1143671Sbinkertn@umich.edu 1153671Sbinkertn@umich.edu for(int i=0; i < 32; i++) { 1163671Sbinkertn@umich.edu if ((machInst & mask) == 0) { 1173671Sbinkertn@umich.edu str += "0"; 1183671Sbinkertn@umich.edu } else { 1193671Sbinkertn@umich.edu str += "1"; 1203671Sbinkertn@umich.edu } 1213671Sbinkertn@umich.edu 1223671Sbinkertn@umich.edu mask = mask >> 1; 1233671Sbinkertn@umich.edu } 1243671Sbinkertn@umich.edu 1253671Sbinkertn@umich.edu return str; 1263671Sbinkertn@umich.edu} 1273671Sbinkertn@umich.edu 1283671Sbinkertn@umich.edu}}; 1293671Sbinkertn@umich.edu