decoder.isa revision 2123
11689SN/A// -*- mode:c++ -*- 29783Sandreas.hansson@arm.com 310239Sbinhpham@cs.rutgers.edu//////////////////////////////////////////////////////////////////// 47598Sminkyu.jeong@arm.com// 57598Sminkyu.jeong@arm.com// The actual MIPS32 ISA decoder 67598Sminkyu.jeong@arm.com// ----------------------------- 77598Sminkyu.jeong@arm.com// The following instructions are specified in the MIPS32 ISA 87598Sminkyu.jeong@arm.com// Specification. Decoding closely follows the style specified 97598Sminkyu.jeong@arm.com// in the MIPS32 ISAthe specification document starting with Table 107598Sminkyu.jeong@arm.com// A-2 (document available @ www.mips.com) 117598Sminkyu.jeong@arm.com// 127598Sminkyu.jeong@arm.com//@todo: Distinguish "unknown/future" use insts from "reserved" 137598Sminkyu.jeong@arm.com// ones 147598Sminkyu.jeong@arm.comdecode OPCODE_HI default Unknown::unknown() { 152326SN/A 161689SN/A // Derived From ... Table A-2 MIPS32 ISA Manual 171689SN/A 0x0: decode OPCODE_LO { 181689SN/A 191689SN/A 0x0: decode FUNCTION_HI { 201689SN/A 0x0: decode FUNCTION_LO { 211689SN/A 0x1: decode MOVCI { 221689SN/A format BasicOp { 231689SN/A 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}}); 241689SN/A 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}}); 251689SN/A } 261689SN/A } 271689SN/A 281689SN/A format BasicOp { 291689SN/A 301689SN/A //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields 311689SN/A //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." 321689SN/A 331689SN/A 0x0: sll({{ Rd = Rt.uw << SA; }}); 341689SN/A 351689SN/A 0x2: decode SRL { 361689SN/A 0: srl({{ Rd = Rt.uw >> SA; }}); 371689SN/A 381689SN/A //Hardcoded assuming 32-bit ISA, probably need parameter here 391689SN/A 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 402665Ssaidi@eecs.umich.edu } 412665Ssaidi@eecs.umich.edu 421689SN/A 0x3: sra({{ Rd = Rt.sw >> SA; }}); 431689SN/A 449944Smatt.horsnell@ARM.com 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 459944Smatt.horsnell@ARM.com 469944Smatt.horsnell@ARM.com 0x6: decode SRLV { 471060SN/A 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 481060SN/A 491689SN/A //Hardcoded assuming 32-bit ISA, probably need parameter here 501060SN/A 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 511060SN/A } 521060SN/A 538230Snate@binkert.org 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }}); 546658Snate@binkert.org } 558887Sgeoffrey.blake@arm.com } 562292SN/A 571717SN/A 0x1: decode FUNCTION_LO { 588229Snate@binkert.org 598232Snate@binkert.org //Table A-3 Note: "Specific encodings of the hint field are used 609444SAndreas.Sandberg@ARM.com //to distinguish JR from JR.HB and JALR from JALR.HB" 618232Snate@binkert.org format Jump { 629527SMatt.Horsnell@arm.com 0x0: decode HINT { 635529Snate@binkert.org 0:jr({{ NNPC = Rs; }},IsReturn); 641060SN/A 656221Snate@binkert.org 1:jr_hb({{ NNPC = Rs; clear_exe_inst_hazards(); }},IsReturn); 666221Snate@binkert.org } 671681SN/A 685529Snate@binkert.org 0x1: decode HINT { 692873Sktlim@umich.edu 0: jalr({{ NNPC = Rs; }},IsCall,IsReturn); 704329Sktlim@umich.edu 714329Sktlim@umich.edu 1: jalr_hb({{ NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn); 724329Sktlim@umich.edu } 732292SN/A } 742292SN/A 752292SN/A format BasicOp { 762292SN/A 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 772820Sktlim@umich.edu 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); 782292SN/A } 792820Sktlim@umich.edu 809444SAndreas.Sandberg@ARM.com format WarnUnimpl { 811060SN/A 0x4: syscall();//{{ xc->syscall()}},IsNonSpeculative 8210172Sdam.sunwoo@arm.com 0x5: break(); 8310172Sdam.sunwoo@arm.com 0x7: sync(); 8410172Sdam.sunwoo@arm.com } 8510172Sdam.sunwoo@arm.com } 8610172Sdam.sunwoo@arm.com 8710172Sdam.sunwoo@arm.com 0x2: decode FUNCTION_LO { 8810172Sdam.sunwoo@arm.com format BasicOp { 8910172Sdam.sunwoo@arm.com 0x0: mfhi({{ Rd = xc->miscRegs.hi; }}); 9010172Sdam.sunwoo@arm.com 0x1: mthi({{ xc->miscRegs.hi = Rs; }}); 9110172Sdam.sunwoo@arm.com 0x2: mflo({{ Rd = xc->miscRegs.lo; }}); 9210172Sdam.sunwoo@arm.com 0x3: mtlo({{ xc->miscRegs.lo = Rs; }}); 9310172Sdam.sunwoo@arm.com } 9410172Sdam.sunwoo@arm.com } 952292SN/A 962292SN/A 0x3: decode FUNCTION_LO { 972292SN/A format IntOp { 981060SN/A 0x0: mult({{ 991060SN/A INT64 temp1 = Rs.sw * Rt.sw; 1001060SN/A xc->miscRegs.hi->temp1<63:32>; 1011060SN/A xc->miscRegs.lo->temp1<31:0>; 1021060SN/A }}); 1031060SN/A 1041681SN/A 0x1: multu({{ 1056221Snate@binkert.org INT64 temp1 = Rs.uw * Rt.uw; 1066221Snate@binkert.org xc->miscRegs.hi->temp1<63:32>; 1076221Snate@binkert.org xc->miscRegs.lo->temp1<31:0> 1082292SN/A Rd.sw = Rs.uw * Rt.uw; 1092292SN/A }}); 1102292SN/A 1112292SN/A 0x2: div({{ 11210328Smitch.hayenga@arm.com xc->miscRegs.hi = Rs.sw % Rt.sw; 1132292SN/A xc->miscRegs.lo = Rs.sw / Rt.sw; 1142292SN/A }}); 1152292SN/A 1162292SN/A 0x3: divu({{ 1172292SN/A xc->miscRegs.hi = Rs.uw % Rt.uw; 1182292SN/A xc->miscRegs.lo = Rs.uw / Rt.uw; 1192292SN/A }}); 1201060SN/A } 1211060SN/A } 1221681SN/A 1231062SN/A 0x4: decode FUNCTION_LO { 12410023Smatt.horsnell@ARM.com format IntOp { 12510023Smatt.horsnell@ARM.com 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}}); 12610023Smatt.horsnell@ARM.com 0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}}); 12710023Smatt.horsnell@ARM.com 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}}); 12811246Sradhika.jagtap@ARM.com 0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}}); 12911246Sradhika.jagtap@ARM.com 0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}}); 13011246Sradhika.jagtap@ARM.com 0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}}); 13111246Sradhika.jagtap@ARM.com 0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}}); 13211246Sradhika.jagtap@ARM.com 0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}}); 13311246Sradhika.jagtap@ARM.com } 13411246Sradhika.jagtap@ARM.com } 13511246Sradhika.jagtap@ARM.com 13611246Sradhika.jagtap@ARM.com 0x5: decode FUNCTION_LO { 13711246Sradhika.jagtap@ARM.com format IntOp{ 13811246Sradhika.jagtap@ARM.com 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 13911246Sradhika.jagtap@ARM.com 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 14010023Smatt.horsnell@ARM.com } 14110023Smatt.horsnell@ARM.com } 14210023Smatt.horsnell@ARM.com 14310023Smatt.horsnell@ARM.com 0x6: decode FUNCTION_LO { 1442292SN/A format Trap { 1451062SN/A 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 1462301SN/A 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 1472301SN/A 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 1481062SN/A 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 1492727Sktlim@umich.edu 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 1501062SN/A 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 1511062SN/A } 1521062SN/A } 1531062SN/A } 1541062SN/A 1551062SN/A 0x1: decode REGIMM_HI { 1561062SN/A 0x0: decode REGIMM_LO { 1571062SN/A format Branch { 1581062SN/A 0x0: bltz({{ cond = (Rs.sw < 0); }}); 1591062SN/A 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 1601062SN/A } 1611062SN/A 1621062SN/A format BranchLikely { 1631062SN/A //MIPS obsolete instructions 1641062SN/A 0x2: bltzl({{ cond = (Rs.sw < 0); }}); 1651062SN/A 0x3: bgezl({{ cond = (Rs.sw >= 0); }}); 1661062SN/A } 1671062SN/A } 1681062SN/A 1691062SN/A 0x1: decode REGIMM_LO { 1701062SN/A format Trap { 1711062SN/A 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); 1721062SN/A 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 1731062SN/A 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); 1741062SN/A 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 1751062SN/A 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}}); 1761062SN/A 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}}); 1771062SN/A } 1781062SN/A } 1791062SN/A 1801062SN/A 0x2: decode REGIMM_LO { 1811062SN/A format Branch { 1821062SN/A 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsLink); 1831062SN/A 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsLink); 1841062SN/A } 1851062SN/A 1861062SN/A format BranchLikely { 1871062SN/A //Will be removed in future MIPS releases 1881062SN/A 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsLink); 1891062SN/A 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsLink); 1901062SN/A } 1912292SN/A } 1922292SN/A 1932292SN/A 0x3: decode REGIMM_LO { 1942292SN/A format WarnUnimpl { 1951062SN/A 0x7: synci(); 1961062SN/A } 1971062SN/A } 1981062SN/A } 1991062SN/A 2001062SN/A format Jump { 2011062SN/A 0x2: j({{ NNPC = (NPC & 0xF0000000) & (0x00000000 & JMPTARG << 2);}}); 2022292SN/A 2032292SN/A 0x3: jal({{ NNPC = (NPC & 0xF0000000) & (0x00000000 & JMPTARG << 2);}},IsCall,IsLink); 2042292SN/A } 2052292SN/A 2062292SN/A format Branch { 2072292SN/A 0x4: beq({{ cond = (Rs.sw == 0); }}); 2082292SN/A 0x5: bne({{ cond = (Rs.sw != 0); }}); 2092292SN/A 0x6: blez({{ cond = (Rs.sw <= 0); }}); 2102292SN/A 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 2112292SN/A } 2122301SN/A } 2132727Sktlim@umich.edu 2142353SN/A 0x1: decode OPCODE_LO { 2152727Sktlim@umich.edu format IntOp { 2162727Sktlim@umich.edu 0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }}); 2172727Sktlim@umich.edu 0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}}); 2186221Snate@binkert.org 0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }}); 2192353SN/A 0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }}); 2202727Sktlim@umich.edu 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}}); 2212727Sktlim@umich.edu 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}}); 2222727Sktlim@umich.edu 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}}); 2232727Sktlim@umich.edu 0x7: lui({{ Rt = INTIMM << 16}}); 2242353SN/A } 2252727Sktlim@umich.edu } 2262727Sktlim@umich.edu 2272727Sktlim@umich.edu 0x2: decode OPCODE_LO { 2286221Snate@binkert.org 2298240Snate@binkert.org //Table A-11 MIPS32 COP0 Encoding of rs Field 2302301SN/A 0x0: decode RS_MSB { 2312727Sktlim@umich.edu 0x0: decode RS { 2322301SN/A format BasicOp { 2332727Sktlim@umich.edu 0x0: mfc0({{ 2346221Snate@binkert.org //The contents of the coprocessor 0 register specified by the 2358240Snate@binkert.org //combination of rd and sel are loaded into general register 2362301SN/A //rt. Note that not all coprocessor 0 registers support the 2372727Sktlim@umich.edu //sel field. In those instances, the sel field must be zero. 2382301SN/A 2392727Sktlim@umich.edu if (SEL > 0) 2406221Snate@binkert.org panic("Can't Handle Cop0 with register select yet\n"); 2418240Snate@binkert.org 2422301SN/A uint64_t reg_num = Rd.uw; 2432727Sktlim@umich.edu 2442301SN/A Rt = xc->miscRegs.cop0[reg_num]; 2452727Sktlim@umich.edu }}); 2466221Snate@binkert.org 2478240Snate@binkert.org 0x4: mtc0({{ 2482301SN/A //The contents of the coprocessor 0 register specified by the 2492727Sktlim@umich.edu //combination of rd and sel are loaded into general register 2502301SN/A //rt. Note that not all coprocessor 0 registers support the 2512301SN/A //sel field. In those instances, the sel field must be zero. 2528240Snate@binkert.org 2532301SN/A if (SEL > 0) 2542727Sktlim@umich.edu panic("Can't Handle Cop0 with register select yet\n"); 2552727Sktlim@umich.edu 2562727Sktlim@umich.edu uint64_t reg_num = Rd.uw; 2572727Sktlim@umich.edu 2588240Snate@binkert.org xc->miscRegs.cop0[reg_num] = Rt; 2592727Sktlim@umich.edu }}); 2602727Sktlim@umich.edu 2612727Sktlim@umich.edu 0x8: mftr({{ 2622727Sktlim@umich.edu //The contents of the coprocessor 0 register specified by the 2632301SN/A //combination of rd and sel are loaded into general register 2642301SN/A //rt. Note that not all coprocessor 0 registers support the 2656221Snate@binkert.org //sel field. In those instances, the sel field must be zero. 2668240Snate@binkert.org 2672301SN/A //MT Code Needed Here 2682727Sktlim@umich.edu }}); 2692301SN/A 2702326SN/A 0xC: mttr({{ 2716221Snate@binkert.org //The contents of the coprocessor 0 register specified by the 2728240Snate@binkert.org //combination of rd and sel are loaded into general register 2732301SN/A //rt. Note that not all coprocessor 0 registers support the 2742727Sktlim@umich.edu //sel field. In those instances, the sel field must be zero. 2752301SN/A 2762326SN/A //MT Code Needed Here 2776221Snate@binkert.org }}); 2788240Snate@binkert.org 2792301SN/A 2802727Sktlim@umich.edu 0xA: rdpgpr({{ 2812301SN/A //Accessing Previous Shadow Set Register Number 2822326SN/A uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS]; 2836221Snate@binkert.org uint64_t reg_num = Rt.uw; 2848240Snate@binkert.org 2852301SN/A Rd = xc->shadowIntRegFile[prev][reg_num]; 2862727Sktlim@umich.edu }}); 2872301SN/A 2882326SN/A 0xB: decode RD { 2898240Snate@binkert.org 2902301SN/A 0x0: decode SC { 2912727Sktlim@umich.edu 0x0: dvpe({{ 2922301SN/A Rt.sw = xc->miscRegs.cop0.MVPControl; 2932326SN/A xc->miscRegs.cop0.MVPControl[EVP] = 0; 2942301SN/A }}); 2952326SN/A 2968240Snate@binkert.org 0x1: evpe({{ 2972301SN/A Rt.sw = xc->miscRegs.cop0.MVPControl; 2982727Sktlim@umich.edu xc->miscRegs.cop0.MVPControl[EVP] = 1; 2992326SN/A }}); 3001062SN/A } 3011062SN/A 3021681SN/A 0x1: decode SC { 3031060SN/A 0x0: dmt({{ 3049427SAndreas.Sandberg@ARM.com Rt.sw = xc->miscRegs.cop0.VPEControl; 3051060SN/A xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 0; 3066221Snate@binkert.org }}); 3072292SN/A 3082292SN/A 0x1: emt({{ 3092292SN/A Rt.sw = xc->miscRegs.cop0.VPEControl; 3102292SN/A xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 1; 3112292SN/A }}); 31210239Sbinhpham@cs.rutgers.edu } 31310239Sbinhpham@cs.rutgers.edu 3142292SN/A 0xC: decode SC { 3152292SN/A 0x0: di({{ 3168887Sgeoffrey.blake@arm.com Rt.sw = xc->miscRegs.cop0.Status; 3178733Sgeoffrey.blake@arm.com xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 0; 3188850Sandreas.hansson@arm.com }}); 3198887Sgeoffrey.blake@arm.com 3208733Sgeoffrey.blake@arm.com 0x1: ei({{ 3212733Sktlim@umich.edu Rt.sw = xc->miscRegs.cop0.Status; 3221060SN/A xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 1; 3231060SN/A }}); 3241681SN/A } 3251060SN/A } 3262292SN/A 3271060SN/A 0xE: wrpgpr({{ 3281060SN/A //Accessing Previous Shadow Set Register Number 3291060SN/A uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS]; 3301060SN/A uint64_t reg_num = Rd.uw; 3311060SN/A 3321060SN/A xc->shadowIntRegFile[prev][reg_num] = Rt; 3331060SN/A }}); 3341060SN/A } 3351060SN/A } 3362292SN/A 3372292SN/A //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 3381060SN/A 0x1: decode FUNCTION { 3391060SN/A format Trap { 3401060SN/A 0x01: tlbr({{ }}); 3411060SN/A 0x02: tlbwi({{ }}); 3421681SN/A 0x06: tlbwr({{ }}); 3431060SN/A 0x08: tlbp({{ }}); 3442292SN/A } 3451060SN/A 3461060SN/A format WarnUnimpl { 3471060SN/A 0x18: eret(); 3481060SN/A 0x1F: deret(); 3491060SN/A 0x20: wait(); 3501060SN/A } 3511060SN/A } 3521681SN/A } 3531060SN/A 3542292SN/A //Table A-13 MIPS32 COP1 Encoding of rs Field 3551060SN/A 0x1: decode RS_MSB { 3561060SN/A 3571060SN/A 0x0: decode RS_HI { 3581060SN/A 0x0: decode RS_LO { 3591060SN/A format FloatOp { 3601060SN/A 0x0: mfc1({{ Rt = Fs<31:0>; }}); 3611060SN/A 0x2: cfc1({{ Rt = xc->miscRegs.fpcr[Fs];}}); 3621681SN/A 0x3: mfhc1({{ Rt = Fs<63:32>;}}); 3631060SN/A 0x4: mtc1({{ Fs<31:0> = Rt}}); 3646221Snate@binkert.org 0x6: ctc1({{ xc->miscRegs.fpcr[Fs] = Rt;}}); 3651060SN/A 0x7: mftc1({{ Fs<63:32> = Rt}}); 3662292SN/A } 3672292SN/A } 3682292SN/A 3692292SN/A 0x1: decode ND { 3701060SN/A 0x0: decode TF { 3711060SN/A format Branch { 3721681SN/A 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }}); 3731060SN/A 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }}); 3742292SN/A } 3751060SN/A } 3762292SN/A 3771060SN/A 0x1: decode TF { 3781060SN/A format BranchLikely { 3792307SN/A 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }}); 3802863Sktlim@umich.edu 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }}); 3819444SAndreas.Sandberg@ARM.com } 3822307SN/A } 38310510Smitch.hayenga@arm.com } 3849444SAndreas.Sandberg@ARM.com } 3859444SAndreas.Sandberg@ARM.com 3869444SAndreas.Sandberg@ARM.com 0x1: decode RS_HI { 3879444SAndreas.Sandberg@ARM.com 0x2: decode RS_LO { 3889444SAndreas.Sandberg@ARM.com 3899444SAndreas.Sandberg@ARM.com //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 3909444SAndreas.Sandberg@ARM.com //(( single-word )) 3919444SAndreas.Sandberg@ARM.com 0x0: decode RS_HI { 3929444SAndreas.Sandberg@ARM.com 0x0: decode RS_LO { 3939444SAndreas.Sandberg@ARM.com format FloatOp { 39411650Srekai.gonzalezalberquilla@arm.com 0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}}); 3959444SAndreas.Sandberg@ARM.com 0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}}); 3969444SAndreas.Sandberg@ARM.com 0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}}); 3979783Sandreas.hansson@arm.com 0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}}); 3989783Sandreas.hansson@arm.com 0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}}); 3999783Sandreas.hansson@arm.com 0x5: abss({{ Fd.sf = abs(Fs.sf);}}); 4009783Sandreas.hansson@arm.com 0x6: movs({{ Fd.sf = Fs.sf;}}); 4019783Sandreas.hansson@arm.com 0x7: negs({{ Fd.sf = -1 * Fs.sf;}}); 4029783Sandreas.hansson@arm.com } 4039783Sandreas.hansson@arm.com } 4049783Sandreas.hansson@arm.com 4059444SAndreas.Sandberg@ARM.com 0x1: decode RS_LO { 4061681SN/A //only legal for 64 bit-FP 4071681SN/A format Float64Op { 4082316SN/A 0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}}); 4091681SN/A 0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}}); 4109444SAndreas.Sandberg@ARM.com 0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}}); 4112843Sktlim@umich.edu 0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}}); 4129444SAndreas.Sandberg@ARM.com } 4132843Sktlim@umich.edu 4149444SAndreas.Sandberg@ARM.com format FloatOp { 4159444SAndreas.Sandberg@ARM.com 0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}}); 4161681SN/A 0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}}); 4171681SN/A 0x6: ceil_w_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}}); 4182307SN/A 0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}}); 4191681SN/A } 4202307SN/A } 4211060SN/A 4222348SN/A 0x2: decode RS_LO { 4232307SN/A 0x1: decode MOVCF { 4242307SN/A format FloatOp { 4252307SN/A 0x0: movfs({{ if ( FPConditionCode(CC) == 0 ) Fd = Fs; }}); 4261060SN/A 0x1: movts({{ if ( FPConditionCode(CC) == 1 ) Fd = Fs;}}); 4272307SN/A } 4282307SN/A } 4299444SAndreas.Sandberg@ARM.com 4301060SN/A format BasicOp { 4319427SAndreas.Sandberg@ARM.com 0x2: movzs({{ if (Rt == 0) Fd = Fs; }}); 4322307SN/A 0x3: movns({{ if (Rt != 0) Fd = Fs; }}); 4331060SN/A } 4346221Snate@binkert.org 4356221Snate@binkert.org format Float64Op { 4366221Snate@binkert.org 0x2: recips({{ Fd = 1 / Fs; }}); 4372307SN/A 0x3: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}}); 4381060SN/A } 4392307SN/A } 4402307SN/A 4412873Sktlim@umich.edu 0x4: decode RS_LO { 4422307SN/A 4431060SN/A format FloatOp { 4441060SN/A 0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr; 4451060SN/A Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE); 4461681SN/A }}); 4471060SN/A 4486221Snate@binkert.org 0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr; 4492107SN/A Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE); 4506221Snate@binkert.org }}); 4512107SN/A } 4522292SN/A 4532292SN/A //only legal for 64 bit 4542107SN/A format Float64Op { 4552292SN/A 0x5: cvt_l_s({{ int rnd_mode = xc->miscRegs.fcsr; 4562326SN/A Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE); 4572292SN/A }}); 4582107SN/A 4592292SN/A 0x6: cvt_ps_s({{ Fd.df = Fs.df<31:0> | Ft.df<31:0>; }}); 4602935Sksewell@umich.edu } 4614632Sgblack@eecs.umich.edu } 4622935Sksewell@umich.edu } 4632292SN/A 46410239Sbinhpham@cs.rutgers.edu //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 46510239Sbinhpham@cs.rutgers.edu 0x1: decode RS_HI { 46610239Sbinhpham@cs.rutgers.edu 0x0: decode RS_LO { 46710239Sbinhpham@cs.rutgers.edu format FloatOp { 46810239Sbinhpham@cs.rutgers.edu 0x0: addd({{ Fd.df = Fs.df + Ft.df;}}); 4692292SN/A 0x1: subd({{ Fd.df = Fs.df - Ft.df;}}); 4702107SN/A 0x2: muld({{ Fd.df = Fs.df * Ft.df;}}); 4712292SN/A 0x3: divd({{ Fd.df = Fs.df / Ft.df;}}); 4722107SN/A 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}}); 4732292SN/A 0x5: absd({{ Fd.df = abs(Fs.df);}}); 4742292SN/A 0x6: movd({{ Fd.df = Fs.df;}}); 4752107SN/A 0x7: negd({{ Fd.df = -1 * Fs.df;}}); 4762702Sktlim@umich.edu } 4772107SN/A } 4782107SN/A 4792107SN/A 0x1: decode RS_LO { 4802107SN/A //only legal for 64 bit 48113429Srekai.gonzalezalberquilla@arm.com format Float64Op { 4822292SN/A 0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 4837720Sgblack@eecs.umich.edu 0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}}); 4847720Sgblack@eecs.umich.edu 0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}}); 4852292SN/A 0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}}); 48610231Ssteve.reinhardt@amd.com } 4877852SMatt.Horsnell@arm.com 4887852SMatt.Horsnell@arm.com format FloatOp { 4897852SMatt.Horsnell@arm.com 0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 4907852SMatt.Horsnell@arm.com 0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }}); 4912935Sksewell@umich.edu 0x6: ceil_w_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }}); 4927852SMatt.Horsnell@arm.com 0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }}); 4937852SMatt.Horsnell@arm.com } 4942292SN/A } 4957852SMatt.Horsnell@arm.com 4967852SMatt.Horsnell@arm.com 0x2: decode RS_LO { 4977852SMatt.Horsnell@arm.com 0x1: decode MOVCF { 4982292SN/A format FloatOp { 4997852SMatt.Horsnell@arm.com 0x0: movfd({{ if (FPConditionCode(CC) == 0) Fd.df = Fs.df; }}); 5007852SMatt.Horsnell@arm.com 0x1: movtd({{ if (FPConditionCode(CC) == 1) Fd.df = Fs.df; }}); 5017852SMatt.Horsnell@arm.com } 5022292SN/A } 5032292SN/A 5042292SN/A format BasicOp { 5052292SN/A 0x2: movz({{ if (Rt == 0) Fd.df = Fs.df; }}); 50613429Srekai.gonzalezalberquilla@arm.com 0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }}); 5072292SN/A } 5088513SGiacomo.Gabrielli@arm.com 5098513SGiacomo.Gabrielli@arm.com format Float64Op { 5108513SGiacomo.Gabrielli@arm.com 0x5: recipd({{ Fd.df = 1 / Fs.df}}); 5118513SGiacomo.Gabrielli@arm.com 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }}); 5128513SGiacomo.Gabrielli@arm.com } 5138513SGiacomo.Gabrielli@arm.com } 5148513SGiacomo.Gabrielli@arm.com 5158513SGiacomo.Gabrielli@arm.com 0x4: decode RS_LO { 51610231Ssteve.reinhardt@amd.com format FloatOp { 5178513SGiacomo.Gabrielli@arm.com 0x0: cvt_s_d({{ 5188513SGiacomo.Gabrielli@arm.com int rnd_mode = xc->miscRegs.fcsr; 5192292SN/A Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE); 5207852SMatt.Horsnell@arm.com }}); 5218513SGiacomo.Gabrielli@arm.com 5228137SAli.Saidi@ARM.com 0x4: cvt_w_d({{ 5232292SN/A int rnd_mode = xc->miscRegs.fcsr; 5248513SGiacomo.Gabrielli@arm.com Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE); 5258513SGiacomo.Gabrielli@arm.com }}); 5262292SN/A } 5277852SMatt.Horsnell@arm.com 5287852SMatt.Horsnell@arm.com //only legal for 64 bit 5292292SN/A format Float64Op { 5302292SN/A 0x5: cvt_l_d({{ 5312292SN/A int rnd_mode = xc->miscRegs.fcsr; 5322292SN/A Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE); 5336221Snate@binkert.org }}); 5342292SN/A } 5352292SN/A } 5362292SN/A } 5372292SN/A 5382292SN/A //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 5392292SN/A 0x4: decode FUNCTION { 5402292SN/A format FloatOp { 5412292SN/A 0x10: cvt_s({{ 5422292SN/A int rnd_mode = xc->miscRegs.fcsr; 5432292SN/A Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD); 5442292SN/A }}); 5452292SN/A 5462292SN/A 0x10: cvt_d({{ 5472292SN/A int rnd_mode = xc->miscRegs.fcsr; 5482292SN/A Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD); 5492292SN/A }}); 5502292SN/A } 5512292SN/A } 5526221Snate@binkert.org 5532292SN/A //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 5542292SN/A //Note: "1. Format type L is legal only if 64-bit floating point operations 5552292SN/A //are enabled." 5562292SN/A 0x5: decode FUNCTION_HI { 5572292SN/A format FloatOp { 5582292SN/A 0x10: cvt_s_l({{ 5592292SN/A int rnd_mode = xc->miscRegs.fcsr; 5602292SN/A Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG); 5612292SN/A }}); 5622292SN/A 5632292SN/A 0x11: cvt_d_l({{ 5642292SN/A int rnd_mode = xc->miscRegs.fcsr; 5652292SN/A Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG); 5662292SN/A }}); 5672292SN/A } 5682292SN/A } 56913429Srekai.gonzalezalberquilla@arm.com 5701060SN/A //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 5711681SN/A //Note: "1. Format type PS is legal only if 64-bit floating point operations 5721060SN/A //are enabled. " 5731060SN/A 0x6: decode RS_HI { 5742292SN/A 0x0: decode RS_LO { 5752292SN/A format Float64Op { 57613429Srekai.gonzalezalberquilla@arm.com 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 5772292SN/A //Lower Halves Independently but we take simulator shortcut 5782292SN/A Fd.df = Fs.df + Ft.df; 5792292SN/A }}); 5801681SN/A 5811681SN/A 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 5821060SN/A //Lower Halves Independently but we take simulator shortcut 58313429Srekai.gonzalezalberquilla@arm.com Fd.df = Fs.df - Ft.df; 5841060SN/A }}); 5852292SN/A 5862292SN/A 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 5871060SN/A //Lower Halves Independently but we take simulator shortcut 5882292SN/A Fd.df = Fs.df * Ft.df; 5892292SN/A }}); 59013429Srekai.gonzalezalberquilla@arm.com 59110333Smitch.hayenga@arm.com 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 59210333Smitch.hayenga@arm.com //Lower Halves Independently but we take simulator shortcut 59310333Smitch.hayenga@arm.com Fd.df = abs(Fs.df); 59410333Smitch.hayenga@arm.com }}); 59510333Smitch.hayenga@arm.com 59610333Smitch.hayenga@arm.com 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 59710333Smitch.hayenga@arm.com //Lower Halves Independently but we take simulator shortcut 59810333Smitch.hayenga@arm.com Fd.df = Fs<31:0> | Ft<31:0>; 59910333Smitch.hayenga@arm.com }}); 60010333Smitch.hayenga@arm.com 60110333Smitch.hayenga@arm.com 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 60210333Smitch.hayenga@arm.com //Lower Halves Independently but we take simulator shortcut 60310333Smitch.hayenga@arm.com Fd.df = -1 * Fs.df; 60413429Srekai.gonzalezalberquilla@arm.com }}); 6052292SN/A } 6063221Sktlim@umich.edu } 6073221Sktlim@umich.edu 6083221Sktlim@umich.edu 0x2: decode RS_LO { 6093221Sktlim@umich.edu 0x1: decode MOVCF { 6103221Sktlim@umich.edu format Float64Op { 6112292SN/A 0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}}); 6122292SN/A 0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}}); 6132292SN/A } 6142292SN/A } 6152326SN/A 6162292SN/A } 6172292SN/A 6182820Sktlim@umich.edu 0x4: decode RS_LO { 6192292SN/A 0x0: Float64Op::cvt_s_pu({{ 6202292SN/A int rnd_mode = xc->miscRegs.fcsr; 6212292SN/A Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI); 6222292SN/A }}); 6232292SN/A } 6242353SN/A 6252353SN/A 0x5: decode RS_LO { 6262292SN/A format Float64Op { 6272292SN/A 0x0: cvt_s_pl({{ 6282292SN/A int rnd_mode = xc->miscRegs.fcsr; 6292292SN/A Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO); 6302292SN/A }}); 6312292SN/A 0x4: pll({{ Fd.df = Fs<31:0> | Ft<31:0>}}); 6322292SN/A 0x5: plu({{ Fd.df = Fs<31:0> | Ft<63:32>}}); 6332292SN/A 0x6: pul({{ Fd.df = Fs<63:32> | Ft<31:0>}}); 6342292SN/A 0x7: puu({{ Fd.df = Fs<63:32 | Ft<63:32>}}); 6352292SN/A } 6362292SN/A } 6372292SN/A } 6382731Sktlim@umich.edu } 6392292SN/A } 6402292SN/A } 6412292SN/A 6422292SN/A //Table A-19 MIPS32 COP2 Encoding of rs Field 6432292SN/A 0x2: decode RS_MSB { 6442292SN/A 0x0: decode RS_HI { 6452292SN/A 0x0: decode RS_LO { 6462292SN/A format WarnUnimpl { 6476221Snate@binkert.org 0x0: mfc2(); 6482292SN/A 0x2: cfc2(); 6492292SN/A 0x3: mfhc2(); 6502292SN/A 0x4: mtc2(); 6512292SN/A 0x6: ctc2(); 6522292SN/A 0x7: mftc2(); 6532292SN/A } 6542292SN/A } 6552292SN/A 6569937SFaissal.Sleiman@arm.com 0x1: decode ND { 6572292SN/A 0x0: decode TF { 6587720Sgblack@eecs.umich.edu format WarnUnimpl { 6592292SN/A 0x0: bc2f(); 6602292SN/A 0x1: bc2t(); 6612292SN/A } 6622292SN/A } 6632292SN/A 6642292SN/A 0x1: decode TF { 6652292SN/A format WarnUnimpl { 6662292SN/A 0x0: bc2fl(); 6672292SN/A 0x1: bc2tl(); 6682292SN/A } 6692292SN/A } 6702292SN/A } 6712292SN/A } 6722292SN/A } 6736221Snate@binkert.org 6746221Snate@binkert.org //Table A-20 MIPS64 COP1X Encoding of Function Field 1 6752292SN/A //Note: "COP1X instructions are legal only if 64-bit floating point 6763867Sbinkertn@umich.edu //operations are enabled." 6776221Snate@binkert.org 0x3: decode FUNCTION_HI { 6783867Sbinkertn@umich.edu 0x0: decode FUNCTION_LO { 6792292SN/A format Memory { 6802292SN/A 0x0: lwxc1({{ EA = Rs + Rt; }},{{ Ft<31:0> = Mem.uf; }}); 6812292SN/A 0x1: ldxc1({{ EA = Rs + Rt; }},{{ Ft<63:0> = Mem.df; }}); 6822292SN/A 0x5: luxc1({{ //Need to make EA<2:0> = 0 6832292SN/A EA = Rs + Rt; 6842292SN/A }}, 6852292SN/A {{ Ft<31:0> = Mem.df; }}); 6862292SN/A } 6872292SN/A } 6882292SN/A 6892292SN/A 0x1: decode FUNCTION_LO { 6906221Snate@binkert.org format Memory { 6916221Snate@binkert.org 0x0: swxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<31:0>; }}); 6922292SN/A 0x1: sdxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<63:0>}}); 6933867Sbinkertn@umich.edu 0x5: suxc1({{ //Need to make EA<2:0> = 0 6946221Snate@binkert.org EA = Rs + Rt; 6953867Sbinkertn@umich.edu }}, 6963867Sbinkertn@umich.edu {{ Mem.df = Ft<63:0>;}}); 6972292SN/A } 6982292SN/A 6992292SN/A 0x7: WarnUnimpl::prefx(); 7002292SN/A } 7011062SN/A 7021062SN/A format FloatOp { 7031681SN/A 0x3: WarnUnimpl::alnv_ps(); 7041062SN/A 7052292SN/A format BasicOp { 7061062SN/A 0x4: decode FUNCTION_LO { 7072292SN/A 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }}); 7081062SN/A 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }}); 7096221Snate@binkert.org 0x6: madd_ps({{ 7106221Snate@binkert.org //Must Check for Exception Here... Supposed to Operate on Upper and 7111062SN/A //Lower Halves Independently but we take simulator shortcut 7123867Sbinkertn@umich.edu Fd.df = (Fs.df * Fs.df) + Fr.df; 7136221Snate@binkert.org }}); 7141062SN/A } 7152292SN/A 7162292SN/A 0x5: decode FUNCTION_LO { 7172292SN/A 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }}); 7182292SN/A 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }}); 7192292SN/A 0x6: msub_ps({{ 7201062SN/A //Must Check for Exception Here... Supposed to Operate on Upper and 7212292SN/A //Lower Halves Independently but we take simulator shortcut 7222292SN/A Fd.df = (Fs.df * Fs.df) - Fr.df; 7232292SN/A }}); 7247897Shestness@cs.utexas.edu } 7252292SN/A 7262292SN/A 0x6: decode FUNCTION_LO { 7272292SN/A 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 7281062SN/A 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); 7292292SN/A 0x6: nmadd_ps({{ 7301062SN/A //Must Check for Exception Here... Supposed to Operate on Upper and 7312292SN/A //Lower Halves Independently but we take simulator shortcut 7322292SN/A Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 7332292SN/A }}); 7342292SN/A } 7352292SN/A 7362292SN/A 0x7: decode FUNCTION_LO { 7371062SN/A 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 7382292SN/A 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }}); 7391062SN/A 0x6: nmsub_ps({{ 7402292SN/A //Must Check for Exception Here... Supposed to Operate on Upper and 7411062SN/A //Lower Halves Independently but we take simulator shortcut 7421062SN/A Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 7431062SN/A }}); 7441681SN/A } 7451062SN/A } 7462292SN/A } 7471062SN/A } 7482292SN/A 7492292SN/A //MIPS obsolete instructions 7502292SN/A format BranchLikely { 7511062SN/A 0x4: beql({{ cond = (Rs.sw == 0); }}); 7522292SN/A 0x5: bnel({{ cond = (Rs.sw != 0); }}); 7532292SN/A 0x6: blezl({{ cond = (Rs.sw <= 0); }}); 7546221Snate@binkert.org 0x7: bgtzl({{ cond = (Rs.sw > 0); }}); 7552292SN/A } 7562292SN/A } 7572292SN/A 75810328Smitch.hayenga@arm.com 0x3: decode OPCODE_LO default FailUnimpl::reserved() { 7592292SN/A 7602292SN/A //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 7612292SN/A 0x4: decode FUNCTION_HI { 7622292SN/A 7632292SN/A 0x0: decode FUNCTION_LO { 7642292SN/A format IntOp { 7652292SN/A 0x0: madd({{ 7662292SN/A INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; 7672292SN/A temp1 = temp1 + (Rs.sw * Rt.sw); 7682292SN/A xc->miscRegs.hi->temp1<63:32>; 7692292SN/A xc->miscRegs.lo->temp1<31:0> 7702292SN/A }}); 7716221Snate@binkert.org 7722292SN/A 0x1: maddu({{ 7732292SN/A INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; 7742292SN/A temp1 = temp1 + (Rs.uw * Rt.uw); 7752292SN/A xc->miscRegs.hi->temp1<63:32>; 7762292SN/A xc->miscRegs.lo->temp1<31:0> 7772292SN/A }}); 7782292SN/A 7792292SN/A 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 7802292SN/A 7812292SN/A 0x4: msub({{ 7822292SN/A INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; 7832292SN/A temp1 = temp1 - (Rs.sw * Rt.sw); 7842292SN/A xc->miscRegs.hi->temp1<63:32>; 7852292SN/A xc->miscRegs.lo->temp1<31:0> 7862292SN/A }}); 7872292SN/A 7882292SN/A 0x5: msubu({{ 7892292SN/A INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; 7902292SN/A temp1 = temp1 - (Rs.uw * Rt.uw); 7912292SN/A xc->miscRegs.hi->temp1<63:32>; 7922292SN/A xc->miscRegs.lo->temp1<31:0> 7932292SN/A }}); 7942292SN/A } 7952702Sktlim@umich.edu } 7962292SN/A 7972292SN/A 0x4: decode FUNCTION_LO { 7982702Sktlim@umich.edu format BasicOp { 7992702Sktlim@umich.edu 0x0: clz({{ 8002292SN/A int cnt = 0; 8012292SN/A int idx = 0; 8022292SN/A while ( Rs.uw<idx>!= 1) { 8032292SN/A cnt++; 8042292SN/A idx--; 8052292SN/A } 8062292SN/A 8072292SN/A Rd.uw = cnt; 8082292SN/A }}); 8092292SN/A 8102292SN/A 0x1: clo({{ 8112292SN/A int cnt = 0; 8122292SN/A int idx = 0; 8132292SN/A while ( Rs.uw<idx>!= 0) { 8142292SN/A cnt++; 8152292SN/A idx--; 8162292SN/A } 8172292SN/A 8182292SN/A Rd.uw = cnt; 8192292SN/A }}); 8202292SN/A } 8212292SN/A } 8222292SN/A 8232292SN/A 0x7: decode FUNCTION_LO { 8242292SN/A 0x7: WarnUnimpl::sdbbp(); 8252292SN/A } 8262292SN/A } 8272292SN/A 8282292SN/A //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture 8292292SN/A 0x7: decode FUNCTION_HI { 8302292SN/A 8312292SN/A 0x0: decode FUNCTION_LO { 8322292SN/A format WarnUnimpl { 8332292SN/A 0x1: ext(); 8342292SN/A 0x4: ins(); 8352292SN/A } 8362292SN/A } 8372292SN/A 8382326SN/A 0x1: decode FUNCTION_LO { 8396221Snate@binkert.org format WarnUnimpl { 8406221Snate@binkert.org 0x0: fork(); 8412326SN/A 0x1: yield(); 8422292SN/A } 8432292SN/A } 8442292SN/A 8452292SN/A 8462292SN/A //Table A-10 MIPS32 BSHFL Encoding of sa Field 8472292SN/A 0x4: decode SA { 8482292SN/A 8496221Snate@binkert.org 0x02: WarnUnimpl::wsbh(); 8502702Sktlim@umich.edu 8514632Sgblack@eecs.umich.edu format BasicOp { 8522935Sksewell@umich.edu 0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}}); 8532702Sktlim@umich.edu 0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}}); 8542935Sksewell@umich.edu } 85510239Sbinhpham@cs.rutgers.edu } 85610239Sbinhpham@cs.rutgers.edu 85710239Sbinhpham@cs.rutgers.edu 0x6: decode FUNCTION_LO { 85810239Sbinhpham@cs.rutgers.edu 0x7: BasicOp::rdhwr({{ Rt = xc->hwRegs[RD];}}); 85910239Sbinhpham@cs.rutgers.edu } 8602702Sktlim@umich.edu } 8612702Sktlim@umich.edu } 8622702Sktlim@umich.edu 8632702Sktlim@umich.edu 0x4: decode OPCODE_LO default FailUnimpl::reserved() { 8642702Sktlim@umich.edu format Memory { 8652702Sktlim@umich.edu 0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }}); 8662702Sktlim@umich.edu 0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }}); 8672702Sktlim@umich.edu 0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }});//, WordAlign); 8682702Sktlim@umich.edu 0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }}); 8692702Sktlim@umich.edu 0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }}); 8702292SN/A 0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }}); 8712292SN/A 0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }});//, WordAlign); 8722292SN/A } 8732292SN/A 8742292SN/A 0x7: FailUnimpl::reserved(); 8752292SN/A } 8762292SN/A 8772292SN/A 0x5: decode OPCODE_LO default FailUnimpl::reserved() { 8782292SN/A format Memory { 8792292SN/A 0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }}); 8802292SN/A 0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }}); 8812292SN/A 0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});//,WordAlign); 8822292SN/A 0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }}); 8832292SN/A 0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});//,WordAlign); 8842292SN/A } 8852292SN/A 8862292SN/A format WarnUnimpl { 8872292SN/A 0x7: cache(); 8882733Sktlim@umich.edu } 8892292SN/A 8902292SN/A } 8912292SN/A 8922292SN/A 0x6: decode OPCODE_LO default FailUnimpl::reserved() { 8932292SN/A 0x0: WarnUnimpl::ll(); 8942292SN/A 8952292SN/A format Memory { 8962733Sktlim@umich.edu 0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }}); 8972292SN/A 0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }}); 8982292SN/A } 8992292SN/A } 9002292SN/A 9016221Snate@binkert.org 0x7: decode OPCODE_LO default FailUnimpl::reserved() { 9022292SN/A 0x0: WarnUnimpl::sc(); 9032292SN/A 9042292SN/A format Memory { 9052292SN/A 0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }}); 9062292SN/A 0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }}); 9072292SN/A } 9082292SN/A 9092292SN/A } 9102292SN/A} 9112292SN/A 9122292SN/A 9132292SN/A