decoder.isa revision 2123
1// -*- mode:c++ -*- 2 3//////////////////////////////////////////////////////////////////// 4// 5// The actual MIPS32 ISA decoder 6// ----------------------------- 7// The following instructions are specified in the MIPS32 ISA 8// Specification. Decoding closely follows the style specified 9// in the MIPS32 ISAthe specification document starting with Table 10// A-2 (document available @ www.mips.com) 11// 12//@todo: Distinguish "unknown/future" use insts from "reserved" 13// ones 14decode OPCODE_HI default Unknown::unknown() { 15 16 // Derived From ... Table A-2 MIPS32 ISA Manual 17 0x0: decode OPCODE_LO { 18 19 0x0: decode FUNCTION_HI { 20 0x0: decode FUNCTION_LO { 21 0x1: decode MOVCI { 22 format BasicOp { 23 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}}); 24 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}}); 25 } 26 } 27 28 format BasicOp { 29 30 //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields 31 //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." 32 33 0x0: sll({{ Rd = Rt.uw << SA; }}); 34 35 0x2: decode SRL { 36 0: srl({{ Rd = Rt.uw >> SA; }}); 37 38 //Hardcoded assuming 32-bit ISA, probably need parameter here 39 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 40 } 41 42 0x3: sra({{ Rd = Rt.sw >> SA; }}); 43 44 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 45 46 0x6: decode SRLV { 47 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 48 49 //Hardcoded assuming 32-bit ISA, probably need parameter here 50 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 51 } 52 53 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }}); 54 } 55 } 56 57 0x1: decode FUNCTION_LO { 58 59 //Table A-3 Note: "Specific encodings of the hint field are used 60 //to distinguish JR from JR.HB and JALR from JALR.HB" 61 format Jump { 62 0x0: decode HINT { 63 0:jr({{ NNPC = Rs; }},IsReturn); 64 65 1:jr_hb({{ NNPC = Rs; clear_exe_inst_hazards(); }},IsReturn); 66 } 67 68 0x1: decode HINT { 69 0: jalr({{ NNPC = Rs; }},IsCall,IsReturn); 70 71 1: jalr_hb({{ NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn); 72 } 73 } 74 75 format BasicOp { 76 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 77 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); 78 } 79 80 format WarnUnimpl { 81 0x4: syscall();//{{ xc->syscall()}},IsNonSpeculative 82 0x5: break(); 83 0x7: sync(); 84 } 85 } 86 87 0x2: decode FUNCTION_LO { 88 format BasicOp { 89 0x0: mfhi({{ Rd = xc->miscRegs.hi; }}); 90 0x1: mthi({{ xc->miscRegs.hi = Rs; }}); 91 0x2: mflo({{ Rd = xc->miscRegs.lo; }}); 92 0x3: mtlo({{ xc->miscRegs.lo = Rs; }}); 93 } 94 } 95 96 0x3: decode FUNCTION_LO { 97 format IntOp { 98 0x0: mult({{ 99 INT64 temp1 = Rs.sw * Rt.sw; 100 xc->miscRegs.hi->temp1<63:32>; 101 xc->miscRegs.lo->temp1<31:0>; 102 }}); 103 104 0x1: multu({{ 105 INT64 temp1 = Rs.uw * Rt.uw; 106 xc->miscRegs.hi->temp1<63:32>; 107 xc->miscRegs.lo->temp1<31:0> 108 Rd.sw = Rs.uw * Rt.uw; 109 }}); 110 111 0x2: div({{ 112 xc->miscRegs.hi = Rs.sw % Rt.sw; 113 xc->miscRegs.lo = Rs.sw / Rt.sw; 114 }}); 115 116 0x3: divu({{ 117 xc->miscRegs.hi = Rs.uw % Rt.uw; 118 xc->miscRegs.lo = Rs.uw / Rt.uw; 119 }}); 120 } 121 } 122 123 0x4: decode FUNCTION_LO { 124 format IntOp { 125 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}}); 126 0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}}); 127 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}}); 128 0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}}); 129 0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}}); 130 0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}}); 131 0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}}); 132 0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}}); 133 } 134 } 135 136 0x5: decode FUNCTION_LO { 137 format IntOp{ 138 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 139 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 140 } 141 } 142 143 0x6: decode FUNCTION_LO { 144 format Trap { 145 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 146 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 147 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 148 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 149 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 150 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 151 } 152 } 153 } 154 155 0x1: decode REGIMM_HI { 156 0x0: decode REGIMM_LO { 157 format Branch { 158 0x0: bltz({{ cond = (Rs.sw < 0); }}); 159 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 160 } 161 162 format BranchLikely { 163 //MIPS obsolete instructions 164 0x2: bltzl({{ cond = (Rs.sw < 0); }}); 165 0x3: bgezl({{ cond = (Rs.sw >= 0); }}); 166 } 167 } 168 169 0x1: decode REGIMM_LO { 170 format Trap { 171 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); 172 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 173 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); 174 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 175 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}}); 176 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}}); 177 } 178 } 179 180 0x2: decode REGIMM_LO { 181 format Branch { 182 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsLink); 183 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsLink); 184 } 185 186 format BranchLikely { 187 //Will be removed in future MIPS releases 188 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsLink); 189 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsLink); 190 } 191 } 192 193 0x3: decode REGIMM_LO { 194 format WarnUnimpl { 195 0x7: synci(); 196 } 197 } 198 } 199 200 format Jump { 201 0x2: j({{ NNPC = (NPC & 0xF0000000) & (0x00000000 & JMPTARG << 2);}}); 202 203 0x3: jal({{ NNPC = (NPC & 0xF0000000) & (0x00000000 & JMPTARG << 2);}},IsCall,IsLink); 204 } 205 206 format Branch { 207 0x4: beq({{ cond = (Rs.sw == 0); }}); 208 0x5: bne({{ cond = (Rs.sw != 0); }}); 209 0x6: blez({{ cond = (Rs.sw <= 0); }}); 210 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 211 } 212 } 213 214 0x1: decode OPCODE_LO { 215 format IntOp { 216 0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }}); 217 0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}}); 218 0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }}); 219 0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }}); 220 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}}); 221 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}}); 222 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}}); 223 0x7: lui({{ Rt = INTIMM << 16}}); 224 } 225 } 226 227 0x2: decode OPCODE_LO { 228 229 //Table A-11 MIPS32 COP0 Encoding of rs Field 230 0x0: decode RS_MSB { 231 0x0: decode RS { 232 format BasicOp { 233 0x0: mfc0({{ 234 //The contents of the coprocessor 0 register specified by the 235 //combination of rd and sel are loaded into general register 236 //rt. Note that not all coprocessor 0 registers support the 237 //sel field. In those instances, the sel field must be zero. 238 239 if (SEL > 0) 240 panic("Can't Handle Cop0 with register select yet\n"); 241 242 uint64_t reg_num = Rd.uw; 243 244 Rt = xc->miscRegs.cop0[reg_num]; 245 }}); 246 247 0x4: mtc0({{ 248 //The contents of the coprocessor 0 register specified by the 249 //combination of rd and sel are loaded into general register 250 //rt. Note that not all coprocessor 0 registers support the 251 //sel field. In those instances, the sel field must be zero. 252 253 if (SEL > 0) 254 panic("Can't Handle Cop0 with register select yet\n"); 255 256 uint64_t reg_num = Rd.uw; 257 258 xc->miscRegs.cop0[reg_num] = Rt; 259 }}); 260 261 0x8: mftr({{ 262 //The contents of the coprocessor 0 register specified by the 263 //combination of rd and sel are loaded into general register 264 //rt. Note that not all coprocessor 0 registers support the 265 //sel field. In those instances, the sel field must be zero. 266 267 //MT Code Needed Here 268 }}); 269 270 0xC: mttr({{ 271 //The contents of the coprocessor 0 register specified by the 272 //combination of rd and sel are loaded into general register 273 //rt. Note that not all coprocessor 0 registers support the 274 //sel field. In those instances, the sel field must be zero. 275 276 //MT Code Needed Here 277 }}); 278 279 280 0xA: rdpgpr({{ 281 //Accessing Previous Shadow Set Register Number 282 uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS]; 283 uint64_t reg_num = Rt.uw; 284 285 Rd = xc->shadowIntRegFile[prev][reg_num]; 286 }}); 287 288 0xB: decode RD { 289 290 0x0: decode SC { 291 0x0: dvpe({{ 292 Rt.sw = xc->miscRegs.cop0.MVPControl; 293 xc->miscRegs.cop0.MVPControl[EVP] = 0; 294 }}); 295 296 0x1: evpe({{ 297 Rt.sw = xc->miscRegs.cop0.MVPControl; 298 xc->miscRegs.cop0.MVPControl[EVP] = 1; 299 }}); 300 } 301 302 0x1: decode SC { 303 0x0: dmt({{ 304 Rt.sw = xc->miscRegs.cop0.VPEControl; 305 xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 0; 306 }}); 307 308 0x1: emt({{ 309 Rt.sw = xc->miscRegs.cop0.VPEControl; 310 xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 1; 311 }}); 312 } 313 314 0xC: decode SC { 315 0x0: di({{ 316 Rt.sw = xc->miscRegs.cop0.Status; 317 xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 0; 318 }}); 319 320 0x1: ei({{ 321 Rt.sw = xc->miscRegs.cop0.Status; 322 xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 1; 323 }}); 324 } 325 } 326 327 0xE: wrpgpr({{ 328 //Accessing Previous Shadow Set Register Number 329 uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS]; 330 uint64_t reg_num = Rd.uw; 331 332 xc->shadowIntRegFile[prev][reg_num] = Rt; 333 }}); 334 } 335 } 336 337 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 338 0x1: decode FUNCTION { 339 format Trap { 340 0x01: tlbr({{ }}); 341 0x02: tlbwi({{ }}); 342 0x06: tlbwr({{ }}); 343 0x08: tlbp({{ }}); 344 } 345 346 format WarnUnimpl { 347 0x18: eret(); 348 0x1F: deret(); 349 0x20: wait(); 350 } 351 } 352 } 353 354 //Table A-13 MIPS32 COP1 Encoding of rs Field 355 0x1: decode RS_MSB { 356 357 0x0: decode RS_HI { 358 0x0: decode RS_LO { 359 format FloatOp { 360 0x0: mfc1({{ Rt = Fs<31:0>; }}); 361 0x2: cfc1({{ Rt = xc->miscRegs.fpcr[Fs];}}); 362 0x3: mfhc1({{ Rt = Fs<63:32>;}}); 363 0x4: mtc1({{ Fs<31:0> = Rt}}); 364 0x6: ctc1({{ xc->miscRegs.fpcr[Fs] = Rt;}}); 365 0x7: mftc1({{ Fs<63:32> = Rt}}); 366 } 367 } 368 369 0x1: decode ND { 370 0x0: decode TF { 371 format Branch { 372 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }}); 373 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }}); 374 } 375 } 376 377 0x1: decode TF { 378 format BranchLikely { 379 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }}); 380 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }}); 381 } 382 } 383 } 384 } 385 386 0x1: decode RS_HI { 387 0x2: decode RS_LO { 388 389 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 390 //(( single-word )) 391 0x0: decode RS_HI { 392 0x0: decode RS_LO { 393 format FloatOp { 394 0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}}); 395 0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}}); 396 0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}}); 397 0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}}); 398 0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}}); 399 0x5: abss({{ Fd.sf = abs(Fs.sf);}}); 400 0x6: movs({{ Fd.sf = Fs.sf;}}); 401 0x7: negs({{ Fd.sf = -1 * Fs.sf;}}); 402 } 403 } 404 405 0x1: decode RS_LO { 406 //only legal for 64 bit-FP 407 format Float64Op { 408 0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}}); 409 0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}}); 410 0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}}); 411 0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}}); 412 } 413 414 format FloatOp { 415 0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}}); 416 0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}}); 417 0x6: ceil_w_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}}); 418 0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}}); 419 } 420 } 421 422 0x2: decode RS_LO { 423 0x1: decode MOVCF { 424 format FloatOp { 425 0x0: movfs({{ if ( FPConditionCode(CC) == 0 ) Fd = Fs; }}); 426 0x1: movts({{ if ( FPConditionCode(CC) == 1 ) Fd = Fs;}}); 427 } 428 } 429 430 format BasicOp { 431 0x2: movzs({{ if (Rt == 0) Fd = Fs; }}); 432 0x3: movns({{ if (Rt != 0) Fd = Fs; }}); 433 } 434 435 format Float64Op { 436 0x2: recips({{ Fd = 1 / Fs; }}); 437 0x3: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}}); 438 } 439 } 440 441 0x4: decode RS_LO { 442 443 format FloatOp { 444 0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr; 445 Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE); 446 }}); 447 448 0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr; 449 Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE); 450 }}); 451 } 452 453 //only legal for 64 bit 454 format Float64Op { 455 0x5: cvt_l_s({{ int rnd_mode = xc->miscRegs.fcsr; 456 Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE); 457 }}); 458 459 0x6: cvt_ps_s({{ Fd.df = Fs.df<31:0> | Ft.df<31:0>; }}); 460 } 461 } 462 } 463 464 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 465 0x1: decode RS_HI { 466 0x0: decode RS_LO { 467 format FloatOp { 468 0x0: addd({{ Fd.df = Fs.df + Ft.df;}}); 469 0x1: subd({{ Fd.df = Fs.df - Ft.df;}}); 470 0x2: muld({{ Fd.df = Fs.df * Ft.df;}}); 471 0x3: divd({{ Fd.df = Fs.df / Ft.df;}}); 472 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}}); 473 0x5: absd({{ Fd.df = abs(Fs.df);}}); 474 0x6: movd({{ Fd.df = Fs.df;}}); 475 0x7: negd({{ Fd.df = -1 * Fs.df;}}); 476 } 477 } 478 479 0x1: decode RS_LO { 480 //only legal for 64 bit 481 format Float64Op { 482 0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 483 0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}}); 484 0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}}); 485 0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}}); 486 } 487 488 format FloatOp { 489 0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 490 0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }}); 491 0x6: ceil_w_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }}); 492 0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }}); 493 } 494 } 495 496 0x2: decode RS_LO { 497 0x1: decode MOVCF { 498 format FloatOp { 499 0x0: movfd({{ if (FPConditionCode(CC) == 0) Fd.df = Fs.df; }}); 500 0x1: movtd({{ if (FPConditionCode(CC) == 1) Fd.df = Fs.df; }}); 501 } 502 } 503 504 format BasicOp { 505 0x2: movz({{ if (Rt == 0) Fd.df = Fs.df; }}); 506 0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }}); 507 } 508 509 format Float64Op { 510 0x5: recipd({{ Fd.df = 1 / Fs.df}}); 511 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }}); 512 } 513 } 514 515 0x4: decode RS_LO { 516 format FloatOp { 517 0x0: cvt_s_d({{ 518 int rnd_mode = xc->miscRegs.fcsr; 519 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE); 520 }}); 521 522 0x4: cvt_w_d({{ 523 int rnd_mode = xc->miscRegs.fcsr; 524 Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE); 525 }}); 526 } 527 528 //only legal for 64 bit 529 format Float64Op { 530 0x5: cvt_l_d({{ 531 int rnd_mode = xc->miscRegs.fcsr; 532 Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE); 533 }}); 534 } 535 } 536 } 537 538 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 539 0x4: decode FUNCTION { 540 format FloatOp { 541 0x10: cvt_s({{ 542 int rnd_mode = xc->miscRegs.fcsr; 543 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD); 544 }}); 545 546 0x10: cvt_d({{ 547 int rnd_mode = xc->miscRegs.fcsr; 548 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD); 549 }}); 550 } 551 } 552 553 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 554 //Note: "1. Format type L is legal only if 64-bit floating point operations 555 //are enabled." 556 0x5: decode FUNCTION_HI { 557 format FloatOp { 558 0x10: cvt_s_l({{ 559 int rnd_mode = xc->miscRegs.fcsr; 560 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG); 561 }}); 562 563 0x11: cvt_d_l({{ 564 int rnd_mode = xc->miscRegs.fcsr; 565 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG); 566 }}); 567 } 568 } 569 570 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 571 //Note: "1. Format type PS is legal only if 64-bit floating point operations 572 //are enabled. " 573 0x6: decode RS_HI { 574 0x0: decode RS_LO { 575 format Float64Op { 576 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 577 //Lower Halves Independently but we take simulator shortcut 578 Fd.df = Fs.df + Ft.df; 579 }}); 580 581 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 582 //Lower Halves Independently but we take simulator shortcut 583 Fd.df = Fs.df - Ft.df; 584 }}); 585 586 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 587 //Lower Halves Independently but we take simulator shortcut 588 Fd.df = Fs.df * Ft.df; 589 }}); 590 591 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 592 //Lower Halves Independently but we take simulator shortcut 593 Fd.df = abs(Fs.df); 594 }}); 595 596 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 597 //Lower Halves Independently but we take simulator shortcut 598 Fd.df = Fs<31:0> | Ft<31:0>; 599 }}); 600 601 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 602 //Lower Halves Independently but we take simulator shortcut 603 Fd.df = -1 * Fs.df; 604 }}); 605 } 606 } 607 608 0x2: decode RS_LO { 609 0x1: decode MOVCF { 610 format Float64Op { 611 0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}}); 612 0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}}); 613 } 614 } 615 616 } 617 618 0x4: decode RS_LO { 619 0x0: Float64Op::cvt_s_pu({{ 620 int rnd_mode = xc->miscRegs.fcsr; 621 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI); 622 }}); 623 } 624 625 0x5: decode RS_LO { 626 format Float64Op { 627 0x0: cvt_s_pl({{ 628 int rnd_mode = xc->miscRegs.fcsr; 629 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO); 630 }}); 631 0x4: pll({{ Fd.df = Fs<31:0> | Ft<31:0>}}); 632 0x5: plu({{ Fd.df = Fs<31:0> | Ft<63:32>}}); 633 0x6: pul({{ Fd.df = Fs<63:32> | Ft<31:0>}}); 634 0x7: puu({{ Fd.df = Fs<63:32 | Ft<63:32>}}); 635 } 636 } 637 } 638 } 639 } 640 } 641 642 //Table A-19 MIPS32 COP2 Encoding of rs Field 643 0x2: decode RS_MSB { 644 0x0: decode RS_HI { 645 0x0: decode RS_LO { 646 format WarnUnimpl { 647 0x0: mfc2(); 648 0x2: cfc2(); 649 0x3: mfhc2(); 650 0x4: mtc2(); 651 0x6: ctc2(); 652 0x7: mftc2(); 653 } 654 } 655 656 0x1: decode ND { 657 0x0: decode TF { 658 format WarnUnimpl { 659 0x0: bc2f(); 660 0x1: bc2t(); 661 } 662 } 663 664 0x1: decode TF { 665 format WarnUnimpl { 666 0x0: bc2fl(); 667 0x1: bc2tl(); 668 } 669 } 670 } 671 } 672 } 673 674 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 675 //Note: "COP1X instructions are legal only if 64-bit floating point 676 //operations are enabled." 677 0x3: decode FUNCTION_HI { 678 0x0: decode FUNCTION_LO { 679 format Memory { 680 0x0: lwxc1({{ EA = Rs + Rt; }},{{ Ft<31:0> = Mem.uf; }}); 681 0x1: ldxc1({{ EA = Rs + Rt; }},{{ Ft<63:0> = Mem.df; }}); 682 0x5: luxc1({{ //Need to make EA<2:0> = 0 683 EA = Rs + Rt; 684 }}, 685 {{ Ft<31:0> = Mem.df; }}); 686 } 687 } 688 689 0x1: decode FUNCTION_LO { 690 format Memory { 691 0x0: swxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<31:0>; }}); 692 0x1: sdxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<63:0>}}); 693 0x5: suxc1({{ //Need to make EA<2:0> = 0 694 EA = Rs + Rt; 695 }}, 696 {{ Mem.df = Ft<63:0>;}}); 697 } 698 699 0x7: WarnUnimpl::prefx(); 700 } 701 702 format FloatOp { 703 0x3: WarnUnimpl::alnv_ps(); 704 705 format BasicOp { 706 0x4: decode FUNCTION_LO { 707 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }}); 708 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }}); 709 0x6: madd_ps({{ 710 //Must Check for Exception Here... Supposed to Operate on Upper and 711 //Lower Halves Independently but we take simulator shortcut 712 Fd.df = (Fs.df * Fs.df) + Fr.df; 713 }}); 714 } 715 716 0x5: decode FUNCTION_LO { 717 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }}); 718 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }}); 719 0x6: msub_ps({{ 720 //Must Check for Exception Here... Supposed to Operate on Upper and 721 //Lower Halves Independently but we take simulator shortcut 722 Fd.df = (Fs.df * Fs.df) - Fr.df; 723 }}); 724 } 725 726 0x6: decode FUNCTION_LO { 727 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 728 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); 729 0x6: nmadd_ps({{ 730 //Must Check for Exception Here... Supposed to Operate on Upper and 731 //Lower Halves Independently but we take simulator shortcut 732 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 733 }}); 734 } 735 736 0x7: decode FUNCTION_LO { 737 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 738 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }}); 739 0x6: nmsub_ps({{ 740 //Must Check for Exception Here... Supposed to Operate on Upper and 741 //Lower Halves Independently but we take simulator shortcut 742 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 743 }}); 744 } 745 } 746 } 747 } 748 749 //MIPS obsolete instructions 750 format BranchLikely { 751 0x4: beql({{ cond = (Rs.sw == 0); }}); 752 0x5: bnel({{ cond = (Rs.sw != 0); }}); 753 0x6: blezl({{ cond = (Rs.sw <= 0); }}); 754 0x7: bgtzl({{ cond = (Rs.sw > 0); }}); 755 } 756 } 757 758 0x3: decode OPCODE_LO default FailUnimpl::reserved() { 759 760 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 761 0x4: decode FUNCTION_HI { 762 763 0x0: decode FUNCTION_LO { 764 format IntOp { 765 0x0: madd({{ 766 INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; 767 temp1 = temp1 + (Rs.sw * Rt.sw); 768 xc->miscRegs.hi->temp1<63:32>; 769 xc->miscRegs.lo->temp1<31:0> 770 }}); 771 772 0x1: maddu({{ 773 INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; 774 temp1 = temp1 + (Rs.uw * Rt.uw); 775 xc->miscRegs.hi->temp1<63:32>; 776 xc->miscRegs.lo->temp1<31:0> 777 }}); 778 779 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 780 781 0x4: msub({{ 782 INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; 783 temp1 = temp1 - (Rs.sw * Rt.sw); 784 xc->miscRegs.hi->temp1<63:32>; 785 xc->miscRegs.lo->temp1<31:0> 786 }}); 787 788 0x5: msubu({{ 789 INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; 790 temp1 = temp1 - (Rs.uw * Rt.uw); 791 xc->miscRegs.hi->temp1<63:32>; 792 xc->miscRegs.lo->temp1<31:0> 793 }}); 794 } 795 } 796 797 0x4: decode FUNCTION_LO { 798 format BasicOp { 799 0x0: clz({{ 800 int cnt = 0; 801 int idx = 0; 802 while ( Rs.uw<idx>!= 1) { 803 cnt++; 804 idx--; 805 } 806 807 Rd.uw = cnt; 808 }}); 809 810 0x1: clo({{ 811 int cnt = 0; 812 int idx = 0; 813 while ( Rs.uw<idx>!= 0) { 814 cnt++; 815 idx--; 816 } 817 818 Rd.uw = cnt; 819 }}); 820 } 821 } 822 823 0x7: decode FUNCTION_LO { 824 0x7: WarnUnimpl::sdbbp(); 825 } 826 } 827 828 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture 829 0x7: decode FUNCTION_HI { 830 831 0x0: decode FUNCTION_LO { 832 format WarnUnimpl { 833 0x1: ext(); 834 0x4: ins(); 835 } 836 } 837 838 0x1: decode FUNCTION_LO { 839 format WarnUnimpl { 840 0x0: fork(); 841 0x1: yield(); 842 } 843 } 844 845 846 //Table A-10 MIPS32 BSHFL Encoding of sa Field 847 0x4: decode SA { 848 849 0x02: WarnUnimpl::wsbh(); 850 851 format BasicOp { 852 0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}}); 853 0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}}); 854 } 855 } 856 857 0x6: decode FUNCTION_LO { 858 0x7: BasicOp::rdhwr({{ Rt = xc->hwRegs[RD];}}); 859 } 860 } 861 } 862 863 0x4: decode OPCODE_LO default FailUnimpl::reserved() { 864 format Memory { 865 0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }}); 866 0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }}); 867 0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }});//, WordAlign); 868 0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }}); 869 0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }}); 870 0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }}); 871 0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }});//, WordAlign); 872 } 873 874 0x7: FailUnimpl::reserved(); 875 } 876 877 0x5: decode OPCODE_LO default FailUnimpl::reserved() { 878 format Memory { 879 0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }}); 880 0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }}); 881 0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});//,WordAlign); 882 0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }}); 883 0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});//,WordAlign); 884 } 885 886 format WarnUnimpl { 887 0x7: cache(); 888 } 889 890 } 891 892 0x6: decode OPCODE_LO default FailUnimpl::reserved() { 893 0x0: WarnUnimpl::ll(); 894 895 format Memory { 896 0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }}); 897 0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }}); 898 } 899 } 900 901 0x7: decode OPCODE_LO default FailUnimpl::reserved() { 902 0x0: WarnUnimpl::sc(); 903 904 format Memory { 905 0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }}); 906 0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }}); 907 } 908 909 } 910} 911 912 913