decoder.isa revision 2084
1//////////////////////////////////////////////////////////////////// 2// 3// The actual MIPS32 ISA decoder 4// ----------------------------- 5// The following instructions are specified in the MIPS32 ISA 6// Specification. Decoding closely follows the style specified 7// in the MIPS32 ISAthe specification document starting with Table 8// A-2 (document available @ www.mips.com) 9// 10//@todo: Distinguish "unknown/future" use insts from "reserved" 11// ones 12decode OPCODE_HI default Unknown::unknown() { 13 14 // Derived From ... Table A-2 MIPS32 ISA Manual 15 0x0: decode OPCODE_LO default FailUnimpl::reserved(){ 16 17 0x0: decode FUNCTION_HI { 18 0x0: decode FUNCTION_LO { 19 0x1: decode MOVCI { 20 format BasicOp { 21 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}}); 22 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}}); 23 } 24 } 25 26 format BasicOp { 27 28 //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields 29 //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." 30 31 0x0: sll({{ Rd = Rt.uw << SA; }}); 32 33 0x2: decode SRL { 34 0: srl({{ Rd = Rt.uw >> SA; }}); 35 36 //Hardcoded assuming 32-bit ISA, probably need parameter here 37 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 38 } 39 40 0x3: sra({{ Rd = Rt.sw >> SA; }}); 41 42 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 43 44 0x6: decode SRLV { 45 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 46 47 //Hardcoded assuming 32-bit ISA, probably need parameter here 48 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 49 } 50 51 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }}); 52 } 53 } 54 55 0x1: decode FUNCTION_LO { 56 57 //Table A-3 Note: "Specific encodings of the hint field are used 58 //to distinguish JR from JR.HB and JALR from JALR.HB" 59 format Jump { 60 0x0: jr(IsReturn); 61 0x1: jalr(IsCall,IsReturn); 62 } 63 64 format BasicOp { 65 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 66 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); 67 } 68 69 70 format WarnUnimpl { 71 0x4: syscall();//{{ xc->syscall()}},IsNonSpeculative 72 0x5: break(); 73 0x7: sync(); 74 } 75 } 76 77 0x2: decode FUNCTION_LO { 78 format BasicOp { 79 0x0: mfhi({{ Rd = xc->miscRegs.hi; }}); 80 0x1: mthi({{ xc->miscRegs.hi = Rs; }}); 81 0x2: mflo({{ Rd = xc->miscRegs.lo; }}); 82 0x3: mtlo({{ xc->miscRegs.lo = Rs; }}); 83 } 84 } 85 86 0x3: decode FUNCTION_LO { 87 format IntOp { 88 0x0: mult({{ 89 INT64 temp1 = Rs.sw * Rt.sw; 90 xc->miscRegs.hi->temp1<63:32>; 91 xc->miscRegs.lo->temp1<31:0>; 92 }}); 93 94 0x1: multu({{ 95 INT64 temp1 = Rs.uw * Rt.uw; 96 xc->miscRegs.hi->temp1<63:32>; 97 xc->miscRegs.lo->temp1<31:0> 98 Rd.sw = Rs.uw * Rt.uw; 99 }}); 100 101 0x2: div({{ 102 xc->miscRegs.hi = Rs.sw % Rt.sw; 103 xc->miscRegs.lo = Rs.sw / Rt.sw; 104 }}); 105 106 0x3: divu({{ 107 xc->miscRegs.hi = Rs.uw % Rt.uw; 108 xc->miscRegs.lo = Rs.uw / Rt.uw; 109 }}); 110 } 111 } 112 113 0x4: decode FUNCTION_LO { 114 format IntOp { 115 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}}); 116 0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}}); 117 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}}); 118 0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}}); 119 0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}}); 120 0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}}); 121 0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}}); 122 0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}}); 123 } 124 } 125 126 0x5: decode FUNCTION_LO { 127 format IntOp{ 128 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 129 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 130 } 131 } 132 133 0x6: decode FUNCTION_LO { 134 format Trap { 135 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 136 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 137 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 138 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 139 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 140 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 141 } 142 } 143 } 144 145 0x1: decode REGIMM_HI { 146 0x0: decode REGIMM_LO { 147 format CondBranch { 148 0x0: bltz({{ cond = (Rs.sw < 0); }}); 149 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 150 151 //MIPS obsolete instructions 152 0x2: bltzl({{ cond = (Rs.sw < 0); }}); 153 0x3: bgezl({{ cond = (Rs.sw >= 0); }}); 154 } 155 } 156 157 0x1: decode REGIMM_LO { 158 format Trap { 159 0x0: tgei({{ cond = (Rs.sw >= INTIMM; }}); 160 0x1: tgeiu({{ cond = (Rs.uw < INTIMM); }}); 161 0x2: tlti({{ cond = (Rs.sw < INTIMM); }}); 162 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 163 0x4: teqi({{ cond = (Rs.sw == INTIMM); }}); 164 0x6: tnei({{ cond = (Rs.sw != INTIMM); }}); 165 } 166 } 167 168 0x2: decode REGIMM_LO { 169 format CondBranch { 170 0x0: bltzal({{ cond = (Rs.sw < 0); }}); 171 0x1: bgezal({{ cond = (Rs.sw >= 0); }}); 172 173 //MIPS obsolete instructions 174 0x2: bltzall({{ cond = (Rs.sw < 0); }}); 175 0x3: bgezall({{ cond = (Rs.sw >= 0); }}); 176 } 177 } 178 179 0x3: decode REGIMM_LO { 180 format WarnUnimpl { 181 0x7: synci(); 182 } 183 } 184 } 185 186 format Jump { 187 0x2: j(); 188 0x3: jal(IsCall); 189 } 190 191 format CondBranch { 192 0x4: beq({{ cond = (Rs.sw == 0); }}); 193 0x5: bne({{ cond = (Rs.sw != 0); }}); 194 0x6: blez({{ cond = (Rs.sw <= 0); }}); 195 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 196 } 197 } 198 199 0x1: decode OPCODE_LO default FailUnimpl::reserved(){ 200 format IntOp { 201 0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }}); 202 0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}}); 203 0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }}); 204 0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }}); 205 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}}); 206 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}}); 207 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}}); 208 0x7: lui({{ Rt = INTIMM << 16}}); 209 } 210 } 211 212 0x2: decode OPCODE_LO default FailUnimpl::reserved(){ 213 214 //Table A-11 MIPS32 COP0 Encoding of rs Field 215 0x0: decode RS_MSB { 216 0x0: decode RS { 217 218 format BasicOp { 219 0x0: mfc0({{ 220 //The contents of the coprocessor 0 register specified by the 221 //combination of rd and sel are loaded into general register 222 //rt. Note that not all coprocessor 0 registers support the 223 //sel field. In those instances, the sel field must be zero. 224 225 if (SEL > 0) 226 panic("Can't Handle Cop0 with register select yet\n"); 227 228 uint64_t reg_num = Rd.uw; 229 230 Rt = xc->miscRegs.cop0[reg_num]; 231 }}); 232 233 0x4: mtc0({{ 234 //The contents of the coprocessor 0 register specified by the 235 //combination of rd and sel are loaded into general register 236 //rt. Note that not all coprocessor 0 registers support the 237 //sel field. In those instances, the sel field must be zero. 238 239 if (SEL > 0) 240 panic("Can't Handle Cop0 with register select yet\n"); 241 242 uint64_t reg_num = Rd.uw; 243 244 xc->miscRegs.cop0[reg_num] = Rt; 245 }}); 246 247 0x8: mftr({{ 248 //The contents of the coprocessor 0 register specified by the 249 //combination of rd and sel are loaded into general register 250 //rt. Note that not all coprocessor 0 registers support the 251 //sel field. In those instances, the sel field must be zero. 252 253 //MT Code Needed Here 254 }}); 255 256 0xC: mttr({{ 257 //The contents of the coprocessor 0 register specified by the 258 //combination of rd and sel are loaded into general register 259 //rt. Note that not all coprocessor 0 registers support the 260 //sel field. In those instances, the sel field must be zero. 261 262 //MT Code Needed Here 263 }}); 264 265 266 0xA: rdpgpr({{ 267 //Accessing Previous Shadow Set Register Number 268 uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS]; 269 uint64_t reg_num = Rt.uw; 270 271 Rd = xc->shadowIntRegFile[prev][reg_num]; 272 }}); 273 } 274 275 0xB: decode RD { 276 277 0x0: decode SC { 278 format BasicOp { 279 0x0: dvpe({{ 280 Rt.sw = xc->miscRegs.cop0.MVPControl; 281 xc->miscRegs.cop0.MVPControl[EVP] = 0; 282 }}); 283 284 0x1: evpe({{ 285 Rt.sw = xc->miscRegs.cop0.MVPControl; 286 xc->miscRegs.cop0.MVPControl[EVP] = 1; 287 }}); 288 } 289 } 290 291 0x1: decode SC { 292 format BasicOp { 293 0x0: dmt({{ 294 Rt.sw = xc->miscRegs.cop0.VPEControl; 295 xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 0; 296 }}); 297 298 0x1: emt({{ 299 Rt.sw = xc->miscRegs.cop0.VPEControl; 300 xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 1; 301 }}); 302 } 303 } 304 305 0xC: decode SC { 306 format BasicOp { 307 0x0: di({{ 308 Rt.sw = xc->miscRegs.cop0.Status; 309 xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 0; 310 }}); 311 312 0x1: ei({{ 313 Rt.sw = xc->miscRegs.cop0.Status; 314 xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 1; 315 }}); 316 } 317 } 318 } 319 320 0xE: BasicOp::wrpgpr({{ 321 //Accessing Previous Shadow Set Register Number 322 uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS]; 323 uint64_t reg_num = Rd.uw; 324 325 xc->shadowIntRegFile[prev][reg_num] = Rt; 326 }}); 327 } 328 329 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 330 0x1: decode FUNCTION { 331 format Trap { 332 0x01: tlbr({{ }}); 333 0x02: tlbwi({{ }}); 334 0x06: tlbwr({{ }}); 335 0x08: tlbp({{ }}); 336 } 337 338 format WarnUnimpl { 339 0x18: eret(); 340 0x1F: deret(); 341 0x20: wait(); 342 } 343 } 344 } 345 346 //Table A-13 MIPS32 COP1 Encoding of rs Field 347 0x1: decode RS_MSB { 348 349 0x0: decode RS_HI { 350 0x0: decode RS_LO { 351 format FloatOp { 352 0x0: mfc1({{ Rt = Fs<31:0>; }}); 353 0x2: cfc1({{ Rt = xc->miscRegs.fpcr[Fs];}}); 354 0x3: mfhc1({{ Rt = Fs<63:32>;}}); 355 0x4: mtc1({{ Fs<31:0> = Rt}}); 356 0x6: ctc1({{ xc->miscRegs.fpcr[Fs] = Rt;}}); 357 0x7: mftc1({{ Fs<63:32> = Rt}}); 358 } 359 } 360 361 0x1: decode ND { 362 0x0: decode TF { 363 format CondBranch { 364 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }}); 365 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }}); 366 } 367 } 368 369 0x1: decode TF { 370 format CondBranch { 371 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }}); 372 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }}); 373 } 374 } 375 } 376 } 377 378 0x1: decode RS_HI { 379 0x2: decode RS_LO { 380 381 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 382 //(( single-word )) 383 0x0: decode RS_HI { 384 0x0: decode RS_LO { 385 format FloatOp { 386 0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}}); 387 0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}}); 388 0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}}); 389 0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}}); 390 0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}}); 391 0x5: abss({{ Fd.sf = abs(Fs.sf);}}); 392 0x6: movs({{ Fd.sf = Fs.sf;}}); 393 0x7: negs({{ Fd.sf = -1 * Fs.sf;}}); 394 } 395 } 396 397 0x1: decode RS_LO { 398 //only legal for 64 bit-FP 399 format Float64Op { 400 0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}}); 401 0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}}); 402 0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}}); 403 0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}}); 404 } 405 406 format FloatOp { 407 0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}}); 408 0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}}); 409 0x6: ceil_w_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}}); 410 0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}}); 411 } 412 } 413 414 0x2: decode RS_LO { 415 0x1: decode MOVCF { 416 format FloatOp { 417 0x0: movfs({{ if ( FPConditionCode(CC) == 0 ) Fd = Fs; }}); 418 0x1: movts({{ if ( FPConditionCode(CC) == 1 ) Fd = Fs;}}); 419 } 420 } 421 422 format BasicOp { 423 0x2: movzs({{ if (Rt == 0) Fd = Fs; }}); 424 0x3: movns({{ if (Rt != 0) Fd = Fs; }}); 425 } 426 427 format Float64Op { 428 0x2: recips({{ Fd = 1 / Fs; }}); 429 0x3: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}}); 430 } 431 } 432 433 0x4: decode RS_LO { 434 435 format FloatOp { 436 0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr; 437 Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE); 438 }}); 439 440 0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr; 441 Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE); 442 }}); 443 } 444 445 //only legal for 64 bit 446 format Float64Op { 447 0x5: cvt_l_s({{ int rnd_mode = xc->miscRegs.fcsr; 448 Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE); 449 }}); 450 451 0x6: cvt_ps_s({{ Fd.df = Fs.df<31:0> | Ft.df<31:0>; }}); 452 } 453 } 454 } 455 456 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 457 0x1: decode RS_HI { 458 0x0: decode RS_LO { 459 format FloatOp { 460 0x0: addd({{ Fd.df = Fs.df + Ft.df;}}); 461 0x1: subd({{ Fd.df = Fs.df - Ft.df;}}); 462 0x2: muld({{ Fd.df = Fs.df * Ft.df;}}); 463 0x3: divd({{ Fd.df = Fs.df / Ft.df;}}); 464 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}}); 465 0x5: absd({{ Fd.df = abs(Fs.df);}}); 466 0x6: movd({{ Fd.df = Fs.df;}}); 467 0x7: negd({{ Fd.df = -1 * Fs.df;}}); 468 } 469 } 470 471 0x1: decode RS_LO { 472 //only legal for 64 bit 473 format Float64Op { 474 0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 475 0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}}); 476 0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}}); 477 0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}}); 478 } 479 480 format FloatOp { 481 0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 482 0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }}); 483 0x6: ceil_w_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }}); 484 0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }}); 485 } 486 } 487 488 0x2: decode RS_LO { 489 0x1: decode MOVCF { 490 format FloatOp { 491 0x0: movfd({{ if (FPConditionCode(CC) == 0) Fd.df = Fs.df; }}); 492 0x1: movtd({{ if (FPConditionCode(CC) == 1) Fd.df = Fs.df; }}); 493 } 494 } 495 496 format BasicOp { 497 0x2: movz({{ if (Rt == 0) Fd.df = Fs.df; }}); 498 0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }}); 499 } 500 501 format Float64Op { 502 0x5: recipd({{ Fd.df = 1 / Fs.df}}); 503 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }}); 504 } 505 } 506 507 0x4: decode RS_LO { 508 format FloatOp { 509 0x0: cvt_s_d({{ 510 int rnd_mode = xc->miscRegs.fcsr; 511 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE); 512 }}); 513 514 0x4: cvt_w_d({{ 515 int rnd_mode = xc->miscRegs.fcsr; 516 Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE); 517 }}); 518 } 519 520 //only legal for 64 bit 521 format Float64Op { 522 0x5: cvt_l_d({{ 523 int rnd_mode = xc->miscRegs.fcsr; 524 Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE); 525 }}); 526 } 527 } 528 } 529 530 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 531 0x4: decode FUNCTION { 532 format FloatOp { 533 0x10: cvt_s({{ 534 int rnd_mode = xc->miscRegs.fcsr; 535 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD); 536 }}); 537 538 0x10: cvt_d({{ 539 int rnd_mode = xc->miscRegs.fcsr; 540 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD); 541 }}); 542 } 543 } 544 545 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 546 //Note: "1. Format type L is legal only if 64-bit floating point operations 547 //are enabled." 548 0x5: decode FUNCTION_HI { 549 format FloatOp { 550 0x10: cvt_s_l({{ 551 int rnd_mode = xc->miscRegs.fcsr; 552 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG); 553 }}); 554 555 0x11: cvt_d_l({{ 556 int rnd_mode = xc->miscRegs.fcsr; 557 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG); 558 }}); 559 } 560 } 561 562 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 563 //Note: "1. Format type PS is legal only if 64-bit floating point operations 564 //are enabled. " 565 0x6: decode RS_HI { 566 0x0: decode RS_LO { 567 format Float64Op { 568 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 569 //Lower Halves Independently but we take simulator shortcut 570 Fd.df = Fs.df + Ft.df; 571 }}); 572 573 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 574 //Lower Halves Independently but we take simulator shortcut 575 Fd.df = Fs.df - Ft.df; 576 }}); 577 578 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 579 //Lower Halves Independently but we take simulator shortcut 580 Fd.df = Fs.df * Ft.df; 581 }}); 582 583 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 584 //Lower Halves Independently but we take simulator shortcut 585 Fd.df = abs(Fs.df); 586 }}); 587 588 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 589 //Lower Halves Independently but we take simulator shortcut 590 Fd.df = Fs<31:0> | Ft<31:0>; 591 }}); 592 593 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 594 //Lower Halves Independently but we take simulator shortcut 595 Fd.df = -1 * Fs.df; 596 }}); 597 } 598 } 599 600 0x2: decode RS_LO { 601 0x1: decode MOVCF { 602 format Float64Op { 603 0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}}); 604 0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}}); 605 } 606 } 607 608 } 609 610 0x4: decode RS_LO { 611 0x0: Float64Op::cvt_s_pu({{ 612 int rnd_mode = xc->miscRegs.fcsr; 613 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI); 614 }}); 615 } 616 617 0x5: decode RS_LO { 618 format Float64Op { 619 0x0: cvt_s_pl({{ 620 int rnd_mode = xc->miscRegs.fcsr; 621 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO); 622 }}); 623 0x4: pll({{ Fd.df = Fs<31:0> | Ft<31:0>}}); 624 0x5: plu({{ Fd.df = Fs<31:0> | Ft<63:32>}}); 625 0x6: pul({{ Fd.df = Fs<63:32> | Ft<31:0>}}); 626 0x7: puu({{ Fd.df = Fs<63:32 | Ft<63:32>}}); 627 } 628 } 629 } 630 } 631 632 //Table A-19 MIPS32 COP2 Encoding of rs Field 633 0x2: decode RS_MSB { 634 0x0: decode RS_HI { 635 0x0: decode RS_LO { 636 format WarnUnimpl { 637 0x0: mfc2(); 638 0x2: cfc2(); 639 0x3: mfhc2(); 640 0x4: mtc2(); 641 0x6: ctc2(); 642 0x7: mftc2(); 643 } 644 } 645 646 0x1: decode ND { 647 0x0: decode TF { 648 format WarnUnimpl { 649 0x0: bc2f(); 650 0x1: bc2t(); 651 } 652 } 653 654 0x1: decode TF { 655 format WarnUnimpl { 656 0x0: bc2fl(); 657 0x1: bc2tl(); 658 } 659 } 660 } 661 } 662 } 663 664 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 665 //Note: "COP1X instructions are legal only if 64-bit floating point 666 //operations are enabled." 667 0x3: decode FUNCTION_HI { 668 0x0: decode FUNCTION_LO { 669 format Memory { 670 0x0: lwxc1({{ EA = Rs + Rt; }},{{ Ft<31:0> = Mem.uf; }}); 671 0x1: ldxc1({{ EA = Rs + Rt; }},{{ Ft<63:0> = Mem.df; }}); 672 0x5: luxc1({{ //Need to make EA<2:0> = 0 673 EA = Rs + Rt; 674 }}, 675 {{ Ft<31:0> = Mem.df; }}); 676 } 677 } 678 679 0x1: decode FUNCTION_LO { 680 format Memory { 681 0x0: swxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<31:0>; }}); 682 0x1: sdxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<63:0>}}); 683 0x5: suxc1({{ //Need to make EA<2:0> = 0 684 EA = Rs + Rt; 685 }}, 686 {{ Mem.df = Ft<63:0>;}}); 687 } 688 689 0x7: WarnUnimpl::prefx(); 690 } 691 692 format FloatOp { 693 0x3: WarnUnimpl::alnv_ps(); 694 695 format BasicOp { 696 0x4: decode FUNCTION_LO { 697 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }}); 698 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }}); 699 0x6: madd_ps({{ 700 //Must Check for Exception Here... Supposed to Operate on Upper and 701 //Lower Halves Independently but we take simulator shortcut 702 Fd.df = (Fs.df * Fs.df) + Fr.df; 703 }}); 704 } 705 706 0x5: decode FUNCTION_LO { 707 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }}); 708 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }}); 709 0x6: msub_ps({{ 710 //Must Check for Exception Here... Supposed to Operate on Upper and 711 //Lower Halves Independently but we take simulator shortcut 712 Fd.df = (Fs.df * Fs.df) - Fr.df; 713 }}); 714 } 715 716 0x6: decode FUNCTION_LO { 717 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 718 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); 719 0x6: nmadd_ps({{ 720 //Must Check for Exception Here... Supposed to Operate on Upper and 721 //Lower Halves Independently but we take simulator shortcut 722 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 723 }}); 724 } 725 726 0x7: decode FUNCTION_LO { 727 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 728 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }}); 729 0x6: nmsub_ps({{ 730 //Must Check for Exception Here... Supposed to Operate on Upper and 731 //Lower Halves Independently but we take simulator shortcut 732 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 733 }}); 734 } 735 } 736 } 737 } 738 739 //MIPS obsolete instructions 740 format CondBranch { 741 0x4: beql({{ cond = (Rs.sw == 0); }}); 742 0x5: bnel({{ cond = (Rs.sw != 0); }}); 743 0x6: blezl({{ cond = (Rs.sw <= 0); }}); 744 0x7: bgtzl({{ cond = (Rs.sw > 0); }}); 745 } 746 } 747 748 0x3: decode OPCODE_LO default FailUnimpl::reserved() { 749 750 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 751 0x4: decode FUNCTION_HI { 752 753 0x0: decode FUNCTION_LO { 754 format IntOp { 755 0x0: madd({{ 756 INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; 757 temp1 = temp1 + (Rs.sw * Rt.sw); 758 xc->miscRegs.hi->temp1<63:32>; 759 xc->miscRegs.lo->temp1<31:0> 760 }}); 761 762 0x1: maddu({{ 763 INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; 764 temp1 = temp1 + (Rs.uw * Rt.uw); 765 xc->miscRegs.hi->temp1<63:32>; 766 xc->miscRegs.lo->temp1<31:0> 767 }}); 768 769 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 770 771 0x4: msub({{ 772 INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; 773 temp1 = temp1 - (Rs.sw * Rt.sw); 774 xc->miscRegs.hi->temp1<63:32>; 775 xc->miscRegs.lo->temp1<31:0> 776 }}); 777 778 0x5: msubu({{ 779 INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; 780 temp1 = temp1 - (Rs.uw * Rt.uw); 781 xc->miscRegs.hi->temp1<63:32>; 782 xc->miscRegs.lo->temp1<31:0> 783 }}); 784 } 785 } 786 787 0x4: decode FUNCTION_LO { 788 format BasicOp { 789 0x0: clz({{ 790 int cnt = 0; 791 int idx = 0; 792 while ( Rs.uw<idx>!= 1) { 793 cnt++; 794 idx--; 795 } 796 797 Rd.uw = cnt; 798 }}); 799 800 0x1: clo({{ 801 int cnt = 0; 802 int idx = 0; 803 while ( Rs.uw<idx>!= 0) { 804 cnt++; 805 idx--; 806 } 807 808 Rd.uw = cnt; 809 }}); 810 } 811 } 812 813 0x7: decode FUNCTION_LO { 814 0x7: WarnUnimpl::sdbbp(); 815 } 816 } 817 818 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture 819 0x7: decode FUNCTION_HI { 820 821 0x0: decode FUNCTION_LO { 822 format WarnUnimpl { 823 0x1: ext(); 824 0x4: ins(); 825 } 826 } 827 828 0x1: decode FUNCTION_LO { 829 format WarnUnimpl { 830 0x0: fork(); 831 0x1: yield(); 832 } 833 } 834 835 836 //Table A-10 MIPS32 BSHFL Encoding of sa Field 837 0x4: decode SA { 838 839 0x02: WarnUnimpl::wsbh(); 840 841 format BasicOp { 842 0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}}); 843 0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}}); 844 } 845 } 846 847 0x6: decode FUNCTION_LO { 848 0x7: BasicOp::rdhwr({{ Rt = xc->hwRegs[RD];}}); 849 } 850 } 851 } 852 853 0x4: decode OPCODE_LO default FailUnimpl::reserved() { 854 format Memory { 855 0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }}); 856 0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }}); 857 0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }});//, WordAlign); 858 0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }}); 859 0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }}); 860 0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }}); 861 0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }});//, WordAlign); 862 } 863 864 0x7: FailUnimpl::reserved(); 865 } 866 867 0x5: decode OPCODE_LO default FailUnimpl::reserved() { 868 format Memory { 869 0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }}); 870 0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }}); 871 0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});//,WordAlign); 872 0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }}); 873 0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});//,WordAlign); 874 } 875 876 format WarnUnimpl { 877 0x7: cache(); 878 } 879 880 } 881 882 0x6: decode OPCODE_LO default FailUnimpl::reserved() { 883 0x0: WarnUnimpl::ll(); 884 885 format Memory { 886 0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }}); 887 0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }}); 888 } 889 } 890 891 0x7: decode OPCODE_LO default FailUnimpl::reserved() { 892 0x0: WarnUnimpl::sc(); 893 894 format Memory { 895 0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }}); 896 0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }}); 897 } 898 899 } 900} 901 902 903