decoder.isa revision 2084
12SN/A//////////////////////////////////////////////////////////////////// 21762SN/A// 32SN/A// The actual MIPS32 ISA decoder 42SN/A// ----------------------------- 52SN/A// The following instructions are specified in the MIPS32 ISA 62SN/A// Specification. Decoding closely follows the style specified 72SN/A// in the MIPS32 ISAthe specification document starting with Table 82SN/A// A-2 (document available @ www.mips.com) 92SN/A// 102SN/A//@todo: Distinguish "unknown/future" use insts from "reserved" 112SN/A// ones 122SN/Adecode OPCODE_HI default Unknown::unknown() { 132SN/A 142SN/A // Derived From ... Table A-2 MIPS32 ISA Manual 152SN/A 0x0: decode OPCODE_LO default FailUnimpl::reserved(){ 162SN/A 172SN/A 0x0: decode FUNCTION_HI { 182SN/A 0x0: decode FUNCTION_LO { 192SN/A 0x1: decode MOVCI { 202SN/A format BasicOp { 212SN/A 0: movf({{ if( xc->miscRegs.fpcr == 0) Rd = Rs}}); 222SN/A 1: movt({{ if( xc->miscRegs.fpcr == 1) Rd = Rs}}); 232SN/A } 242SN/A } 252SN/A 262SN/A format BasicOp { 272665Ssaidi@eecs.umich.edu 282665Ssaidi@eecs.umich.edu //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields 292665Ssaidi@eecs.umich.edu //are used to distinguish among the SLL, NOP, SSNOP and EHB functions." 302SN/A 312SN/A 0x0: sll({{ Rd = Rt.uw << SA; }}); 321112SN/A 331112SN/A 0x2: decode SRL { 342SN/A 0: srl({{ Rd = Rt.uw >> SA; }}); 353386Sgblack@eecs.umich.edu 362SN/A //Hardcoded assuming 32-bit ISA, probably need parameter here 372SN/A 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 382SN/A } 392SN/A 402SN/A 0x3: sra({{ Rd = Rt.sw >> SA; }}); 412SN/A 422SN/A 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 432SN/A 442SN/A 0x6: decode SRLV { 452SN/A 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 462SN/A 474070Ssaidi@eecs.umich.edu //Hardcoded assuming 32-bit ISA, probably need parameter here 482SN/A 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 492SN/A } 502SN/A 512SN/A 0x7: srav({{ Rd = Rt.sw >> Rs<4:0>; }}); 522SN/A } 532SN/A } 542SN/A 552SN/A 0x1: decode FUNCTION_LO { 562SN/A 572SN/A //Table A-3 Note: "Specific encodings of the hint field are used 582SN/A //to distinguish JR from JR.HB and JALR from JALR.HB" 592SN/A format Jump { 602SN/A 0x0: jr(IsReturn); 612SN/A 0x1: jalr(IsCall,IsReturn); 623814Ssaidi@eecs.umich.edu } 633814Ssaidi@eecs.umich.edu 643814Ssaidi@eecs.umich.edu format BasicOp { 653814Ssaidi@eecs.umich.edu 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 663814Ssaidi@eecs.umich.edu 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); 673814Ssaidi@eecs.umich.edu } 683814Ssaidi@eecs.umich.edu 693814Ssaidi@eecs.umich.edu 703814Ssaidi@eecs.umich.edu format WarnUnimpl { 713814Ssaidi@eecs.umich.edu 0x4: syscall();//{{ xc->syscall()}},IsNonSpeculative 723814Ssaidi@eecs.umich.edu 0x5: break(); 734070Ssaidi@eecs.umich.edu 0x7: sync(); 744070Ssaidi@eecs.umich.edu } 754070Ssaidi@eecs.umich.edu } 764070Ssaidi@eecs.umich.edu 774070Ssaidi@eecs.umich.edu 0x2: decode FUNCTION_LO { 784070Ssaidi@eecs.umich.edu format BasicOp { 793814Ssaidi@eecs.umich.edu 0x0: mfhi({{ Rd = xc->miscRegs.hi; }}); 802SN/A 0x1: mthi({{ xc->miscRegs.hi = Rs; }}); 812SN/A 0x2: mflo({{ Rd = xc->miscRegs.lo; }}); 822SN/A 0x3: mtlo({{ xc->miscRegs.lo = Rs; }}); 832SN/A } 842SN/A } 852SN/A 862SN/A 0x3: decode FUNCTION_LO { 872SN/A format IntOp { 882SN/A 0x0: mult({{ 892SN/A INT64 temp1 = Rs.sw * Rt.sw; 902SN/A xc->miscRegs.hi->temp1<63:32>; 913422Sgblack@eecs.umich.edu xc->miscRegs.lo->temp1<31:0>; 923422Sgblack@eecs.umich.edu }}); 933422Sgblack@eecs.umich.edu 943422Sgblack@eecs.umich.edu 0x1: multu({{ 953422Sgblack@eecs.umich.edu INT64 temp1 = Rs.uw * Rt.uw; 963422Sgblack@eecs.umich.edu xc->miscRegs.hi->temp1<63:32>; 973422Sgblack@eecs.umich.edu xc->miscRegs.lo->temp1<31:0> 983422Sgblack@eecs.umich.edu Rd.sw = Rs.uw * Rt.uw; 993422Sgblack@eecs.umich.edu }}); 1003422Sgblack@eecs.umich.edu 1013422Sgblack@eecs.umich.edu 0x2: div({{ 1023422Sgblack@eecs.umich.edu xc->miscRegs.hi = Rs.sw % Rt.sw; 1033422Sgblack@eecs.umich.edu xc->miscRegs.lo = Rs.sw / Rt.sw; 1043422Sgblack@eecs.umich.edu }}); 1053422Sgblack@eecs.umich.edu 1063422Sgblack@eecs.umich.edu 0x3: divu({{ 1073422Sgblack@eecs.umich.edu xc->miscRegs.hi = Rs.uw % Rt.uw; 1083422Sgblack@eecs.umich.edu xc->miscRegs.lo = Rs.uw / Rt.uw; 1093422Sgblack@eecs.umich.edu }}); 1103422Sgblack@eecs.umich.edu } 1113422Sgblack@eecs.umich.edu } 1123422Sgblack@eecs.umich.edu 1133422Sgblack@eecs.umich.edu 0x4: decode FUNCTION_LO { 1143422Sgblack@eecs.umich.edu format IntOp { 1154103Ssaidi@eecs.umich.edu 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;}}); 1164103Ssaidi@eecs.umich.edu 0x1: addu({{ Rd.uw = Rs.uw + Rt.uw;}}); 1174103Ssaidi@eecs.umich.edu 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;}}); 1184103Ssaidi@eecs.umich.edu 0x3: subu({{ Rd.uw = Rs.uw - Rt.uw;}}); 1194103Ssaidi@eecs.umich.edu 0x4: and({{ Rd.sw = Rs.uw & Rt.uw;}}); 1204103Ssaidi@eecs.umich.edu 0x5: or({{ Rd.sw = Rs.uw | Rt.uw;}}); 1214103Ssaidi@eecs.umich.edu 0x6: xor({{ Rd.sw = Rs.uw ^ Rt.uw;}}); 1224103Ssaidi@eecs.umich.edu 0x7: nor({{ Rd.sw = ~(Rs.uw | Rt.uw);}}); 1234103Ssaidi@eecs.umich.edu } 1244244Ssaidi@eecs.umich.edu } 1254244Ssaidi@eecs.umich.edu 1264244Ssaidi@eecs.umich.edu 0x5: decode FUNCTION_LO { 1274244Ssaidi@eecs.umich.edu format IntOp{ 1284244Ssaidi@eecs.umich.edu 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 1294244Ssaidi@eecs.umich.edu 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 1304103Ssaidi@eecs.umich.edu } 1314103Ssaidi@eecs.umich.edu } 1324103Ssaidi@eecs.umich.edu 1334259Sgblack@eecs.umich.edu 0x6: decode FUNCTION_LO { 1344259Sgblack@eecs.umich.edu format Trap { 1354259Sgblack@eecs.umich.edu 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 1364259Sgblack@eecs.umich.edu 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 1374259Sgblack@eecs.umich.edu 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 1384259Sgblack@eecs.umich.edu 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 1394259Sgblack@eecs.umich.edu 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 1404259Sgblack@eecs.umich.edu 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 1414259Sgblack@eecs.umich.edu } 1424259Sgblack@eecs.umich.edu } 1434258Sgblack@eecs.umich.edu } 1444257Sgblack@eecs.umich.edu 1454259Sgblack@eecs.umich.edu 0x1: decode REGIMM_HI { 1464259Sgblack@eecs.umich.edu 0x0: decode REGIMM_LO { 1474259Sgblack@eecs.umich.edu format CondBranch { 1484258Sgblack@eecs.umich.edu 0x0: bltz({{ cond = (Rs.sw < 0); }}); 1494258Sgblack@eecs.umich.edu 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 1504258Sgblack@eecs.umich.edu 1514258Sgblack@eecs.umich.edu //MIPS obsolete instructions 1524258Sgblack@eecs.umich.edu 0x2: bltzl({{ cond = (Rs.sw < 0); }}); 1534103Ssaidi@eecs.umich.edu 0x3: bgezl({{ cond = (Rs.sw >= 0); }}); 1544259Sgblack@eecs.umich.edu } 1554259Sgblack@eecs.umich.edu } 1564259Sgblack@eecs.umich.edu 1574259Sgblack@eecs.umich.edu 0x1: decode REGIMM_LO { 1584258Sgblack@eecs.umich.edu format Trap { 1594258Sgblack@eecs.umich.edu 0x0: tgei({{ cond = (Rs.sw >= INTIMM; }}); 1604258Sgblack@eecs.umich.edu 0x1: tgeiu({{ cond = (Rs.uw < INTIMM); }}); 1614258Sgblack@eecs.umich.edu 0x2: tlti({{ cond = (Rs.sw < INTIMM); }}); 1624258Sgblack@eecs.umich.edu 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 1634258Sgblack@eecs.umich.edu 0x4: teqi({{ cond = (Rs.sw == INTIMM); }}); 1644259Sgblack@eecs.umich.edu 0x6: tnei({{ cond = (Rs.sw != INTIMM); }}); 1654258Sgblack@eecs.umich.edu } 1664258Sgblack@eecs.umich.edu } 1674258Sgblack@eecs.umich.edu 1684258Sgblack@eecs.umich.edu 0x2: decode REGIMM_LO { 1694258Sgblack@eecs.umich.edu format CondBranch { 1704258Sgblack@eecs.umich.edu 0x0: bltzal({{ cond = (Rs.sw < 0); }}); 1714258Sgblack@eecs.umich.edu 0x1: bgezal({{ cond = (Rs.sw >= 0); }}); 1724259Sgblack@eecs.umich.edu 1734259Sgblack@eecs.umich.edu //MIPS obsolete instructions 1744261Sgblack@eecs.umich.edu 0x2: bltzall({{ cond = (Rs.sw < 0); }}); 1754258Sgblack@eecs.umich.edu 0x3: bgezall({{ cond = (Rs.sw >= 0); }}); 1764258Sgblack@eecs.umich.edu } 1774257Sgblack@eecs.umich.edu } 1784261Sgblack@eecs.umich.edu 1794261Sgblack@eecs.umich.edu 0x3: decode REGIMM_LO { 1804261Sgblack@eecs.umich.edu format WarnUnimpl { 1814261Sgblack@eecs.umich.edu 0x7: synci(); 1824258Sgblack@eecs.umich.edu } 1834258Sgblack@eecs.umich.edu } 1844258Sgblack@eecs.umich.edu } 1854258Sgblack@eecs.umich.edu 1864258Sgblack@eecs.umich.edu format Jump { 1874258Sgblack@eecs.umich.edu 0x2: j(); 1884257Sgblack@eecs.umich.edu 0x3: jal(IsCall); 1894259Sgblack@eecs.umich.edu } 1904258Sgblack@eecs.umich.edu 1914258Sgblack@eecs.umich.edu format CondBranch { 1924257Sgblack@eecs.umich.edu 0x4: beq({{ cond = (Rs.sw == 0); }}); 1934261Sgblack@eecs.umich.edu 0x5: bne({{ cond = (Rs.sw != 0); }}); 1944261Sgblack@eecs.umich.edu 0x6: blez({{ cond = (Rs.sw <= 0); }}); 1954261Sgblack@eecs.umich.edu 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 1964258Sgblack@eecs.umich.edu } 1974260Sgblack@eecs.umich.edu } 1984258Sgblack@eecs.umich.edu 1994258Sgblack@eecs.umich.edu 0x1: decode OPCODE_LO default FailUnimpl::reserved(){ 2004258Sgblack@eecs.umich.edu format IntOp { 2014258Sgblack@eecs.umich.edu 0x0: addi({{ Rt.sw = Rs.sw + INTIMM; }}); 2024258Sgblack@eecs.umich.edu 0x1: addiu({{ Rt.uw = Rs.uw + INTIMM;}}); 2034257Sgblack@eecs.umich.edu 0x2: slti({{ Rt.sw = ( Rs.sw < INTIMM ) ? 1 : 0 }}); 2044259Sgblack@eecs.umich.edu 0x3: sltiu({{ Rt.uw = ( Rs.uw < INTIMM ) ? 1 : 0 }}); 2054259Sgblack@eecs.umich.edu 0x4: andi({{ Rt.sw = Rs.sw & INTIMM;}}); 2064258Sgblack@eecs.umich.edu 0x5: ori({{ Rt.sw = Rs.sw | INTIMM;}}); 2074258Sgblack@eecs.umich.edu 0x6: xori({{ Rt.sw = Rs.sw ^ INTIMM;}}); 2084258Sgblack@eecs.umich.edu 0x7: lui({{ Rt = INTIMM << 16}}); 2094258Sgblack@eecs.umich.edu } 2104258Sgblack@eecs.umich.edu } 2114258Sgblack@eecs.umich.edu 2124258Sgblack@eecs.umich.edu 0x2: decode OPCODE_LO default FailUnimpl::reserved(){ 2134258Sgblack@eecs.umich.edu 2144257Sgblack@eecs.umich.edu //Table A-11 MIPS32 COP0 Encoding of rs Field 2154258Sgblack@eecs.umich.edu 0x0: decode RS_MSB { 2164260Sgblack@eecs.umich.edu 0x0: decode RS { 2174258Sgblack@eecs.umich.edu 2184258Sgblack@eecs.umich.edu format BasicOp { 2194258Sgblack@eecs.umich.edu 0x0: mfc0({{ 2204258Sgblack@eecs.umich.edu //The contents of the coprocessor 0 register specified by the 2214258Sgblack@eecs.umich.edu //combination of rd and sel are loaded into general register 2224258Sgblack@eecs.umich.edu //rt. Note that not all coprocessor 0 registers support the 2234259Sgblack@eecs.umich.edu //sel field. In those instances, the sel field must be zero. 2244259Sgblack@eecs.umich.edu 2254259Sgblack@eecs.umich.edu if (SEL > 0) 2264259Sgblack@eecs.umich.edu panic("Can't Handle Cop0 with register select yet\n"); 2274259Sgblack@eecs.umich.edu 2284259Sgblack@eecs.umich.edu uint64_t reg_num = Rd.uw; 2294258Sgblack@eecs.umich.edu 2304258Sgblack@eecs.umich.edu Rt = xc->miscRegs.cop0[reg_num]; 2314257Sgblack@eecs.umich.edu }}); 2324258Sgblack@eecs.umich.edu 2334258Sgblack@eecs.umich.edu 0x4: mtc0({{ 2344258Sgblack@eecs.umich.edu //The contents of the coprocessor 0 register specified by the 2354258Sgblack@eecs.umich.edu //combination of rd and sel are loaded into general register 2364258Sgblack@eecs.umich.edu //rt. Note that not all coprocessor 0 registers support the 2374257Sgblack@eecs.umich.edu //sel field. In those instances, the sel field must be zero. 2384258Sgblack@eecs.umich.edu 2394260Sgblack@eecs.umich.edu if (SEL > 0) 2404258Sgblack@eecs.umich.edu panic("Can't Handle Cop0 with register select yet\n"); 2414258Sgblack@eecs.umich.edu 2424258Sgblack@eecs.umich.edu uint64_t reg_num = Rd.uw; 2434257Sgblack@eecs.umich.edu 2444258Sgblack@eecs.umich.edu xc->miscRegs.cop0[reg_num] = Rt; 2454260Sgblack@eecs.umich.edu }}); 2464258Sgblack@eecs.umich.edu 2474258Sgblack@eecs.umich.edu 0x8: mftr({{ 2484258Sgblack@eecs.umich.edu //The contents of the coprocessor 0 register specified by the 2494257Sgblack@eecs.umich.edu //combination of rd and sel are loaded into general register 2504258Sgblack@eecs.umich.edu //rt. Note that not all coprocessor 0 registers support the 2514260Sgblack@eecs.umich.edu //sel field. In those instances, the sel field must be zero. 2524258Sgblack@eecs.umich.edu 2534258Sgblack@eecs.umich.edu //MT Code Needed Here 2544258Sgblack@eecs.umich.edu }}); 2554258Sgblack@eecs.umich.edu 2564258Sgblack@eecs.umich.edu 0xC: mttr({{ 2574257Sgblack@eecs.umich.edu //The contents of the coprocessor 0 register specified by the 2584259Sgblack@eecs.umich.edu //combination of rd and sel are loaded into general register 2594259Sgblack@eecs.umich.edu //rt. Note that not all coprocessor 0 registers support the 2604259Sgblack@eecs.umich.edu //sel field. In those instances, the sel field must be zero. 2614259Sgblack@eecs.umich.edu 2624259Sgblack@eecs.umich.edu //MT Code Needed Here 2634259Sgblack@eecs.umich.edu }}); 2644259Sgblack@eecs.umich.edu 2654259Sgblack@eecs.umich.edu 2664259Sgblack@eecs.umich.edu 0xA: rdpgpr({{ 2674259Sgblack@eecs.umich.edu //Accessing Previous Shadow Set Register Number 2684259Sgblack@eecs.umich.edu uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS]; 2694259Sgblack@eecs.umich.edu uint64_t reg_num = Rt.uw; 2704259Sgblack@eecs.umich.edu 2714259Sgblack@eecs.umich.edu Rd = xc->shadowIntRegFile[prev][reg_num]; 2724259Sgblack@eecs.umich.edu }}); 2734257Sgblack@eecs.umich.edu } 2744258Sgblack@eecs.umich.edu 2754258Sgblack@eecs.umich.edu 0xB: decode RD { 2764258Sgblack@eecs.umich.edu 2774258Sgblack@eecs.umich.edu 0x0: decode SC { 2784258Sgblack@eecs.umich.edu format BasicOp { 2794257Sgblack@eecs.umich.edu 0x0: dvpe({{ 2804257Sgblack@eecs.umich.edu Rt.sw = xc->miscRegs.cop0.MVPControl; 2814257Sgblack@eecs.umich.edu xc->miscRegs.cop0.MVPControl[EVP] = 0; 2824257Sgblack@eecs.umich.edu }}); 2834257Sgblack@eecs.umich.edu 2844259Sgblack@eecs.umich.edu 0x1: evpe({{ 2854259Sgblack@eecs.umich.edu Rt.sw = xc->miscRegs.cop0.MVPControl; 2864259Sgblack@eecs.umich.edu xc->miscRegs.cop0.MVPControl[EVP] = 1; 2874259Sgblack@eecs.umich.edu }}); 2884257Sgblack@eecs.umich.edu } 2894257Sgblack@eecs.umich.edu } 2904257Sgblack@eecs.umich.edu 2914258Sgblack@eecs.umich.edu 0x1: decode SC { 2924258Sgblack@eecs.umich.edu format BasicOp { 2934258Sgblack@eecs.umich.edu 0x0: dmt({{ 2944257Sgblack@eecs.umich.edu Rt.sw = xc->miscRegs.cop0.VPEControl; 2954259Sgblack@eecs.umich.edu xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 0; 2964259Sgblack@eecs.umich.edu }}); 2974259Sgblack@eecs.umich.edu 2984259Sgblack@eecs.umich.edu 0x1: emt({{ 2994259Sgblack@eecs.umich.edu Rt.sw = xc->miscRegs.cop0.VPEControl; 3004259Sgblack@eecs.umich.edu xc->miscRegs.cop0.VPEControl[THREAD_ENABLE] = 1; 3014259Sgblack@eecs.umich.edu }}); 3024257Sgblack@eecs.umich.edu } 3034257Sgblack@eecs.umich.edu } 3044257Sgblack@eecs.umich.edu 3054257Sgblack@eecs.umich.edu 0xC: decode SC { 3064257Sgblack@eecs.umich.edu format BasicOp { 3074257Sgblack@eecs.umich.edu 0x0: di({{ 3084257Sgblack@eecs.umich.edu Rt.sw = xc->miscRegs.cop0.Status; 3094257Sgblack@eecs.umich.edu xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 0; 3104257Sgblack@eecs.umich.edu }}); 3114259Sgblack@eecs.umich.edu 3124259Sgblack@eecs.umich.edu 0x1: ei({{ 3134257Sgblack@eecs.umich.edu Rt.sw = xc->miscRegs.cop0.Status; 3144257Sgblack@eecs.umich.edu xc->miscRegs.cop0.Status[INTERRUPT_ENABLE] = 1; 3154259Sgblack@eecs.umich.edu }}); 3164259Sgblack@eecs.umich.edu } 3174259Sgblack@eecs.umich.edu } 3184258Sgblack@eecs.umich.edu } 3194257Sgblack@eecs.umich.edu 3204257Sgblack@eecs.umich.edu 0xE: BasicOp::wrpgpr({{ 3214259Sgblack@eecs.umich.edu //Accessing Previous Shadow Set Register Number 3224259Sgblack@eecs.umich.edu uint64_t prev = xc->miscRegs.cop0[SRSCtl][PSS]; 3234259Sgblack@eecs.umich.edu uint64_t reg_num = Rd.uw; 3244259Sgblack@eecs.umich.edu 3254258Sgblack@eecs.umich.edu xc->shadowIntRegFile[prev][reg_num] = Rt; 3264258Sgblack@eecs.umich.edu }}); 3274258Sgblack@eecs.umich.edu } 3284258Sgblack@eecs.umich.edu 3294257Sgblack@eecs.umich.edu //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 3304257Sgblack@eecs.umich.edu 0x1: decode FUNCTION { 3314259Sgblack@eecs.umich.edu format Trap { 3324259Sgblack@eecs.umich.edu 0x01: tlbr({{ }}); 3334258Sgblack@eecs.umich.edu 0x02: tlbwi({{ }}); 3344258Sgblack@eecs.umich.edu 0x06: tlbwr({{ }}); 3354258Sgblack@eecs.umich.edu 0x08: tlbp({{ }}); 3364258Sgblack@eecs.umich.edu } 3374258Sgblack@eecs.umich.edu 3384258Sgblack@eecs.umich.edu format WarnUnimpl { 3394259Sgblack@eecs.umich.edu 0x18: eret(); 3404259Sgblack@eecs.umich.edu 0x1F: deret(); 3414258Sgblack@eecs.umich.edu 0x20: wait(); 3424258Sgblack@eecs.umich.edu } 3434258Sgblack@eecs.umich.edu } 3444258Sgblack@eecs.umich.edu } 3454258Sgblack@eecs.umich.edu 3464258Sgblack@eecs.umich.edu //Table A-13 MIPS32 COP1 Encoding of rs Field 3474258Sgblack@eecs.umich.edu 0x1: decode RS_MSB { 3484258Sgblack@eecs.umich.edu 3494257Sgblack@eecs.umich.edu 0x0: decode RS_HI { 3504258Sgblack@eecs.umich.edu 0x0: decode RS_LO { 3514257Sgblack@eecs.umich.edu format FloatOp { 3524259Sgblack@eecs.umich.edu 0x0: mfc1({{ Rt = Fs<31:0>; }}); 3534257Sgblack@eecs.umich.edu 0x2: cfc1({{ Rt = xc->miscRegs.fpcr[Fs];}}); 3544257Sgblack@eecs.umich.edu 0x3: mfhc1({{ Rt = Fs<63:32>;}}); 3554259Sgblack@eecs.umich.edu 0x4: mtc1({{ Fs<31:0> = Rt}}); 3564257Sgblack@eecs.umich.edu 0x6: ctc1({{ xc->miscRegs.fpcr[Fs] = Rt;}}); 3574257Sgblack@eecs.umich.edu 0x7: mftc1({{ Fs<63:32> = Rt}}); 3584257Sgblack@eecs.umich.edu } 3594257Sgblack@eecs.umich.edu } 3604103Ssaidi@eecs.umich.edu 3611112SN/A 0x1: decode ND { 362 0x0: decode TF { 363 format CondBranch { 364 0x0: bc1f({{ cond = (xc->miscRegs.fpcr == 0); }}); 365 0x1: bc1t({{ cond = (xc->miscRegs.fpcr == 1); }}); 366 } 367 } 368 369 0x1: decode TF { 370 format CondBranch { 371 0x0: bc1fl({{ cond = (xc->miscRegs.fpcr == 0); }}); 372 0x1: bc1tl({{ cond = (xc->miscRegs.fpcr == 1); }}); 373 } 374 } 375 } 376 } 377 378 0x1: decode RS_HI { 379 0x2: decode RS_LO { 380 381 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 382 //(( single-word )) 383 0x0: decode RS_HI { 384 0x0: decode RS_LO { 385 format FloatOp { 386 0x0: adds({{ Fd.sf = Fs.sf + Ft.sf;}}); 387 0x1: subs({{ Fd.sf = Fs.sf - Ft.sf;}}); 388 0x2: muls({{ Fd.sf = Fs.sf * Ft.sf;}}); 389 0x3: divs({{ Fd.sf = Fs.sf / Ft.sf;}}); 390 0x4: sqrts({{ Fd.sf = sqrt(Fs.sf);}}); 391 0x5: abss({{ Fd.sf = abs(Fs.sf);}}); 392 0x6: movs({{ Fd.sf = Fs.sf;}}); 393 0x7: negs({{ Fd.sf = -1 * Fs.sf;}}); 394 } 395 } 396 397 0x1: decode RS_LO { 398 //only legal for 64 bit-FP 399 format Float64Op { 400 0x0: round_l_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_LONG,FP_SINGLE);}}); 401 0x1: trunc_l_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_LONG,FP_SINGLE);}}); 402 0x2: ceil_l_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_LONG,FP_SINGLE);}}); 403 0x3: floor_l_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_LONG,FP_SINGLE);}}); 404 } 405 406 format FloatOp { 407 0x4: round_w_s({{ Fd = convert_and_round(Fs.sf,RND_NEAREST,FP_WORD,FP_SINGLE);}}); 408 0x5: trunc_w_s({{ Fd = convert_and_round(Fs.sf,RND_ZERO,FP_WORD,FP_SINGLE);}}); 409 0x6: ceil_w_s({{ Fd = convert_and_round(Fs.sf,RND_UP,FP_WORD,FP_SINGLE);}}); 410 0x7: floor_w_s({{ Fd = convert_and_round(Fs.sf,RND_DOWN,FP_WORD,FP_SINGLE);}}); 411 } 412 } 413 414 0x2: decode RS_LO { 415 0x1: decode MOVCF { 416 format FloatOp { 417 0x0: movfs({{ if ( FPConditionCode(CC) == 0 ) Fd = Fs; }}); 418 0x1: movts({{ if ( FPConditionCode(CC) == 1 ) Fd = Fs;}}); 419 } 420 } 421 422 format BasicOp { 423 0x2: movzs({{ if (Rt == 0) Fd = Fs; }}); 424 0x3: movns({{ if (Rt != 0) Fd = Fs; }}); 425 } 426 427 format Float64Op { 428 0x2: recips({{ Fd = 1 / Fs; }}); 429 0x3: rsqrts({{ Fd = 1 / sqrt(Fs.ud);}}); 430 } 431 } 432 433 0x4: decode RS_LO { 434 435 format FloatOp { 436 0x1: cvt_d_s({{ int rnd_mode = xc->miscRegs.fcsr; 437 Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE); 438 }}); 439 440 0x4: cvt_w_s({{ int rnd_mode = xc->miscRegs.fcsr; 441 Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE); 442 }}); 443 } 444 445 //only legal for 64 bit 446 format Float64Op { 447 0x5: cvt_l_s({{ int rnd_mode = xc->miscRegs.fcsr; 448 Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE); 449 }}); 450 451 0x6: cvt_ps_s({{ Fd.df = Fs.df<31:0> | Ft.df<31:0>; }}); 452 } 453 } 454 } 455 456 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 457 0x1: decode RS_HI { 458 0x0: decode RS_LO { 459 format FloatOp { 460 0x0: addd({{ Fd.df = Fs.df + Ft.df;}}); 461 0x1: subd({{ Fd.df = Fs.df - Ft.df;}}); 462 0x2: muld({{ Fd.df = Fs.df * Ft.df;}}); 463 0x3: divd({{ Fd.df = Fs.df / Ft.df;}}); 464 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}}); 465 0x5: absd({{ Fd.df = abs(Fs.df);}}); 466 0x6: movd({{ Fd.df = Fs.df;}}); 467 0x7: negd({{ Fd.df = -1 * Fs.df;}}); 468 } 469 } 470 471 0x1: decode RS_LO { 472 //only legal for 64 bit 473 format Float64Op { 474 0x0: round_l_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 475 0x1: trunc_l_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE);}}); 476 0x2: ceil_l_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE);}}); 477 0x3: floor_l_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE);}}); 478 } 479 480 format FloatOp { 481 0x4: round_w_d({{ Fd = convert_and_round(Fs.df,RND_NEAREST,FP_LONG,FP_DOUBLE); }}); 482 0x5: trunc_w_d({{ Fd = convert_and_round(Fs.df,RND_ZERO,FP_LONG,FP_DOUBLE); }}); 483 0x6: ceil_w_d({{ Fd = convert_and_round(Fs.df,RND_UP,FP_LONG,FP_DOUBLE); }}); 484 0x7: floor_w_d({{ Fd = convert_and_round(Fs.df,RND_DOWN,FP_LONG,FP_DOUBLE); }}); 485 } 486 } 487 488 0x2: decode RS_LO { 489 0x1: decode MOVCF { 490 format FloatOp { 491 0x0: movfd({{ if (FPConditionCode(CC) == 0) Fd.df = Fs.df; }}); 492 0x1: movtd({{ if (FPConditionCode(CC) == 1) Fd.df = Fs.df; }}); 493 } 494 } 495 496 format BasicOp { 497 0x2: movz({{ if (Rt == 0) Fd.df = Fs.df; }}); 498 0x3: movn({{ if (Rt != 0) Fd.df = Fs.df; }}); 499 } 500 501 format Float64Op { 502 0x5: recipd({{ Fd.df = 1 / Fs.df}}); 503 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }}); 504 } 505 } 506 507 0x4: decode RS_LO { 508 format FloatOp { 509 0x0: cvt_s_d({{ 510 int rnd_mode = xc->miscRegs.fcsr; 511 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_DOUBLE); 512 }}); 513 514 0x4: cvt_w_d({{ 515 int rnd_mode = xc->miscRegs.fcsr; 516 Fd = convert_and_round(Fs.df,rnd_mode,FP_WORD,FP_DOUBLE); 517 }}); 518 } 519 520 //only legal for 64 bit 521 format Float64Op { 522 0x5: cvt_l_d({{ 523 int rnd_mode = xc->miscRegs.fcsr; 524 Fd = convert_and_round(Fs.df,rnd_mode,FP_LONG,FP_DOUBLE); 525 }}); 526 } 527 } 528 } 529 530 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 531 0x4: decode FUNCTION { 532 format FloatOp { 533 0x10: cvt_s({{ 534 int rnd_mode = xc->miscRegs.fcsr; 535 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_WORD); 536 }}); 537 538 0x10: cvt_d({{ 539 int rnd_mode = xc->miscRegs.fcsr; 540 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_WORD); 541 }}); 542 } 543 } 544 545 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 546 //Note: "1. Format type L is legal only if 64-bit floating point operations 547 //are enabled." 548 0x5: decode FUNCTION_HI { 549 format FloatOp { 550 0x10: cvt_s_l({{ 551 int rnd_mode = xc->miscRegs.fcsr; 552 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_LONG); 553 }}); 554 555 0x11: cvt_d_l({{ 556 int rnd_mode = xc->miscRegs.fcsr; 557 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_LONG); 558 }}); 559 } 560 } 561 562 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 563 //Note: "1. Format type PS is legal only if 64-bit floating point operations 564 //are enabled. " 565 0x6: decode RS_HI { 566 0x0: decode RS_LO { 567 format Float64Op { 568 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 569 //Lower Halves Independently but we take simulator shortcut 570 Fd.df = Fs.df + Ft.df; 571 }}); 572 573 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 574 //Lower Halves Independently but we take simulator shortcut 575 Fd.df = Fs.df - Ft.df; 576 }}); 577 578 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 579 //Lower Halves Independently but we take simulator shortcut 580 Fd.df = Fs.df * Ft.df; 581 }}); 582 583 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 584 //Lower Halves Independently but we take simulator shortcut 585 Fd.df = abs(Fs.df); 586 }}); 587 588 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 589 //Lower Halves Independently but we take simulator shortcut 590 Fd.df = Fs<31:0> | Ft<31:0>; 591 }}); 592 593 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 594 //Lower Halves Independently but we take simulator shortcut 595 Fd.df = -1 * Fs.df; 596 }}); 597 } 598 } 599 600 0x2: decode RS_LO { 601 0x1: decode MOVCF { 602 format Float64Op { 603 0x0: movfps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}}); 604 0x1: movtps({{ if ( FPConditionCode(CC) == 0) Fd = Fs;}}); 605 } 606 } 607 608 } 609 610 0x4: decode RS_LO { 611 0x0: Float64Op::cvt_s_pu({{ 612 int rnd_mode = xc->miscRegs.fcsr; 613 Fd = convert_and_round(Fs.df,rnd_mode,FP_DOUBLE,FP_PS_HI); 614 }}); 615 } 616 617 0x5: decode RS_LO { 618 format Float64Op { 619 0x0: cvt_s_pl({{ 620 int rnd_mode = xc->miscRegs.fcsr; 621 Fd = convert_and_round(Fs.df,rnd_mode,FP_SINGLE,FP_PS_LO); 622 }}); 623 0x4: pll({{ Fd.df = Fs<31:0> | Ft<31:0>}}); 624 0x5: plu({{ Fd.df = Fs<31:0> | Ft<63:32>}}); 625 0x6: pul({{ Fd.df = Fs<63:32> | Ft<31:0>}}); 626 0x7: puu({{ Fd.df = Fs<63:32 | Ft<63:32>}}); 627 } 628 } 629 } 630 } 631 632 //Table A-19 MIPS32 COP2 Encoding of rs Field 633 0x2: decode RS_MSB { 634 0x0: decode RS_HI { 635 0x0: decode RS_LO { 636 format WarnUnimpl { 637 0x0: mfc2(); 638 0x2: cfc2(); 639 0x3: mfhc2(); 640 0x4: mtc2(); 641 0x6: ctc2(); 642 0x7: mftc2(); 643 } 644 } 645 646 0x1: decode ND { 647 0x0: decode TF { 648 format WarnUnimpl { 649 0x0: bc2f(); 650 0x1: bc2t(); 651 } 652 } 653 654 0x1: decode TF { 655 format WarnUnimpl { 656 0x0: bc2fl(); 657 0x1: bc2tl(); 658 } 659 } 660 } 661 } 662 } 663 664 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 665 //Note: "COP1X instructions are legal only if 64-bit floating point 666 //operations are enabled." 667 0x3: decode FUNCTION_HI { 668 0x0: decode FUNCTION_LO { 669 format Memory { 670 0x0: lwxc1({{ EA = Rs + Rt; }},{{ Ft<31:0> = Mem.uf; }}); 671 0x1: ldxc1({{ EA = Rs + Rt; }},{{ Ft<63:0> = Mem.df; }}); 672 0x5: luxc1({{ //Need to make EA<2:0> = 0 673 EA = Rs + Rt; 674 }}, 675 {{ Ft<31:0> = Mem.df; }}); 676 } 677 } 678 679 0x1: decode FUNCTION_LO { 680 format Memory { 681 0x0: swxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<31:0>; }}); 682 0x1: sdxc1({{ EA = Rs + Rt; }},{{ Mem.uf = Ft<63:0>}}); 683 0x5: suxc1({{ //Need to make EA<2:0> = 0 684 EA = Rs + Rt; 685 }}, 686 {{ Mem.df = Ft<63:0>;}}); 687 } 688 689 0x7: WarnUnimpl::prefx(); 690 } 691 692 format FloatOp { 693 0x3: WarnUnimpl::alnv_ps(); 694 695 format BasicOp { 696 0x4: decode FUNCTION_LO { 697 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }}); 698 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }}); 699 0x6: madd_ps({{ 700 //Must Check for Exception Here... Supposed to Operate on Upper and 701 //Lower Halves Independently but we take simulator shortcut 702 Fd.df = (Fs.df * Fs.df) + Fr.df; 703 }}); 704 } 705 706 0x5: decode FUNCTION_LO { 707 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }}); 708 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }}); 709 0x6: msub_ps({{ 710 //Must Check for Exception Here... Supposed to Operate on Upper and 711 //Lower Halves Independently but we take simulator shortcut 712 Fd.df = (Fs.df * Fs.df) - Fr.df; 713 }}); 714 } 715 716 0x6: decode FUNCTION_LO { 717 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 718 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); 719 0x6: nmadd_ps({{ 720 //Must Check for Exception Here... Supposed to Operate on Upper and 721 //Lower Halves Independently but we take simulator shortcut 722 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 723 }}); 724 } 725 726 0x7: decode FUNCTION_LO { 727 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 728 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }}); 729 0x6: nmsub_ps({{ 730 //Must Check for Exception Here... Supposed to Operate on Upper and 731 //Lower Halves Independently but we take simulator shortcut 732 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 733 }}); 734 } 735 } 736 } 737 } 738 739 //MIPS obsolete instructions 740 format CondBranch { 741 0x4: beql({{ cond = (Rs.sw == 0); }}); 742 0x5: bnel({{ cond = (Rs.sw != 0); }}); 743 0x6: blezl({{ cond = (Rs.sw <= 0); }}); 744 0x7: bgtzl({{ cond = (Rs.sw > 0); }}); 745 } 746 } 747 748 0x3: decode OPCODE_LO default FailUnimpl::reserved() { 749 750 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 751 0x4: decode FUNCTION_HI { 752 753 0x0: decode FUNCTION_LO { 754 format IntOp { 755 0x0: madd({{ 756 INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; 757 temp1 = temp1 + (Rs.sw * Rt.sw); 758 xc->miscRegs.hi->temp1<63:32>; 759 xc->miscRegs.lo->temp1<31:0> 760 }}); 761 762 0x1: maddu({{ 763 INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; 764 temp1 = temp1 + (Rs.uw * Rt.uw); 765 xc->miscRegs.hi->temp1<63:32>; 766 xc->miscRegs.lo->temp1<31:0> 767 }}); 768 769 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 770 771 0x4: msub({{ 772 INT64 temp1 = Hi.sw << 32 | Lo.sw >> 32; 773 temp1 = temp1 - (Rs.sw * Rt.sw); 774 xc->miscRegs.hi->temp1<63:32>; 775 xc->miscRegs.lo->temp1<31:0> 776 }}); 777 778 0x5: msubu({{ 779 INT64 temp1 = Hi.uw << 32 | Lo.uw >> 32; 780 temp1 = temp1 - (Rs.uw * Rt.uw); 781 xc->miscRegs.hi->temp1<63:32>; 782 xc->miscRegs.lo->temp1<31:0> 783 }}); 784 } 785 } 786 787 0x4: decode FUNCTION_LO { 788 format BasicOp { 789 0x0: clz({{ 790 int cnt = 0; 791 int idx = 0; 792 while ( Rs.uw<idx>!= 1) { 793 cnt++; 794 idx--; 795 } 796 797 Rd.uw = cnt; 798 }}); 799 800 0x1: clo({{ 801 int cnt = 0; 802 int idx = 0; 803 while ( Rs.uw<idx>!= 0) { 804 cnt++; 805 idx--; 806 } 807 808 Rd.uw = cnt; 809 }}); 810 } 811 } 812 813 0x7: decode FUNCTION_LO { 814 0x7: WarnUnimpl::sdbbp(); 815 } 816 } 817 818 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture 819 0x7: decode FUNCTION_HI { 820 821 0x0: decode FUNCTION_LO { 822 format WarnUnimpl { 823 0x1: ext(); 824 0x4: ins(); 825 } 826 } 827 828 0x1: decode FUNCTION_LO { 829 format WarnUnimpl { 830 0x0: fork(); 831 0x1: yield(); 832 } 833 } 834 835 836 //Table A-10 MIPS32 BSHFL Encoding of sa Field 837 0x4: decode SA { 838 839 0x02: WarnUnimpl::wsbh(); 840 841 format BasicOp { 842 0x10: seb({{ Rd.sw = /* sext32(Rt<7>,24) | */ Rt<7:0>}}); 843 0x18: seh({{ Rd.sw = /* sext32(Rt<15>,16) | */ Rt<15:0>}}); 844 } 845 } 846 847 0x6: decode FUNCTION_LO { 848 0x7: BasicOp::rdhwr({{ Rt = xc->hwRegs[RD];}}); 849 } 850 } 851 } 852 853 0x4: decode OPCODE_LO default FailUnimpl::reserved() { 854 format Memory { 855 0x0: lb({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sb; }}); 856 0x1: lh({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sh; }}); 857 0x2: lwl({{ EA = Rs + disp; }}, {{ Rb.sw = Mem.sw; }});//, WordAlign); 858 0x3: lw({{ EA = Rs + disp; }}, {{ Rb.uq = Mem.sb; }}); 859 0x4: lbu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.ub; }}); 860 0x5: lhu({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uh; }}); 861 0x6: lwr({{ EA = Rs + disp; }}, {{ Rb.uw = Mem.uw; }});//, WordAlign); 862 } 863 864 0x7: FailUnimpl::reserved(); 865 } 866 867 0x5: decode OPCODE_LO default FailUnimpl::reserved() { 868 format Memory { 869 0x0: sb({{ EA = Rs + disp; }}, {{ Mem.ub = Rt<7:0>; }}); 870 0x1: sh({{ EA = Rs + disp; }},{{ Mem.uh = Rt<15:0>; }}); 871 0x2: swl({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});//,WordAlign); 872 0x3: sw({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }}); 873 0x6: swr({{ EA = Rs + disp; }},{{ Mem.ub = Rt<31:0>; }});//,WordAlign); 874 } 875 876 format WarnUnimpl { 877 0x7: cache(); 878 } 879 880 } 881 882 0x6: decode OPCODE_LO default FailUnimpl::reserved() { 883 0x0: WarnUnimpl::ll(); 884 885 format Memory { 886 0x1: lwc1({{ EA = Rs + disp; }},{{ Ft<31:0> = Mem.uf; }}); 887 0x5: ldc1({{ EA = Rs + disp; }},{{ Ft<63:0> = Mem.df; }}); 888 } 889 } 890 891 0x7: decode OPCODE_LO default FailUnimpl::reserved() { 892 0x0: WarnUnimpl::sc(); 893 894 format Memory { 895 0x1: swc1({{ EA = Rs + disp; }},{{ Mem.uf = Ft<31:0>; }}); 896 0x5: sdc1({{ EA = Rs + disp; }},{{ Mem.df = Ft<63:0>; }}); 897 } 898 899 } 900} 901 902 903