faults.cc revision 2665
12131SN/A/* 22131SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32131SN/A * All rights reserved. 42131SN/A * 52131SN/A * Redistribution and use in source and binary forms, with or without 62131SN/A * modification, are permitted provided that the following conditions are 72131SN/A * met: redistributions of source code must retain the above copyright 82131SN/A * notice, this list of conditions and the following disclaimer; 92131SN/A * redistributions in binary form must reproduce the above copyright 102131SN/A * notice, this list of conditions and the following disclaimer in the 112131SN/A * documentation and/or other materials provided with the distribution; 122131SN/A * neither the name of the copyright holders nor the names of its 132131SN/A * contributors may be used to endorse or promote products derived from 142131SN/A * this software without specific prior written permission. 152131SN/A * 162131SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172131SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182131SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192131SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202131SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212131SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222131SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232131SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242131SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252131SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262131SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Korey Sewell 292131SN/A */ 302131SN/A 312239SN/A#include "arch/mips/faults.hh" 322447SN/A#include "cpu/exec_context.hh" 332447SN/A#include "cpu/base.hh" 342447SN/A#include "base/trace.hh" 352131SN/A 362447SN/Anamespace MipsISA 372447SN/A{ 382131SN/A 392479SN/AFaultName MachineCheckFault::_name = "Machine Check"; 402447SN/AFaultVect MachineCheckFault::_vect = 0x0401; 412447SN/AFaultStat MachineCheckFault::_count; 422131SN/A 432479SN/AFaultName AlignmentFault::_name = "Alignment"; 442447SN/AFaultVect AlignmentFault::_vect = 0x0301; 452447SN/AFaultStat AlignmentFault::_count; 462447SN/A 472447SN/AFaultName ResetFault::_name = "reset"; 482447SN/AFaultVect ResetFault::_vect = 0x0001; 492447SN/AFaultStat ResetFault::_count; 502447SN/A 512447SN/AFaultName ArithmeticFault::_name = "arith"; 522447SN/AFaultVect ArithmeticFault::_vect = 0x0501; 532447SN/AFaultStat ArithmeticFault::_count; 542447SN/A 552447SN/AFaultName InterruptFault::_name = "interrupt"; 562447SN/AFaultVect InterruptFault::_vect = 0x0101; 572447SN/AFaultStat InterruptFault::_count; 582447SN/A 592447SN/AFaultName NDtbMissFault::_name = "dtb_miss_single"; 602447SN/AFaultVect NDtbMissFault::_vect = 0x0201; 612447SN/AFaultStat NDtbMissFault::_count; 622447SN/A 632447SN/AFaultName PDtbMissFault::_name = "dtb_miss_double"; 642447SN/AFaultVect PDtbMissFault::_vect = 0x0281; 652447SN/AFaultStat PDtbMissFault::_count; 662447SN/A 672447SN/AFaultName DtbPageFault::_name = "dfault"; 682447SN/AFaultVect DtbPageFault::_vect = 0x0381; 692447SN/AFaultStat DtbPageFault::_count; 702447SN/A 712447SN/AFaultName DtbAcvFault::_name = "dfault"; 722447SN/AFaultVect DtbAcvFault::_vect = 0x0381; 732447SN/AFaultStat DtbAcvFault::_count; 742447SN/A 752447SN/AFaultName ItbMissFault::_name = "itbmiss"; 762447SN/AFaultVect ItbMissFault::_vect = 0x0181; 772447SN/AFaultStat ItbMissFault::_count; 782447SN/A 792447SN/AFaultName ItbPageFault::_name = "itbmiss"; 802447SN/AFaultVect ItbPageFault::_vect = 0x0181; 812447SN/AFaultStat ItbPageFault::_count; 822447SN/A 832447SN/AFaultName ItbAcvFault::_name = "iaccvio"; 842447SN/AFaultVect ItbAcvFault::_vect = 0x0081; 852447SN/AFaultStat ItbAcvFault::_count; 862447SN/A 872447SN/AFaultName UnimplementedOpcodeFault::_name = "opdec"; 882447SN/AFaultVect UnimplementedOpcodeFault::_vect = 0x0481; 892447SN/AFaultStat UnimplementedOpcodeFault::_count; 902447SN/A 912447SN/AFaultName FloatEnableFault::_name = "fen"; 922447SN/AFaultVect FloatEnableFault::_vect = 0x0581; 932447SN/AFaultStat FloatEnableFault::_count; 942447SN/A 952447SN/AFaultName PalFault::_name = "pal"; 962447SN/AFaultVect PalFault::_vect = 0x2001; 972447SN/AFaultStat PalFault::_count; 982447SN/A 992447SN/AFaultName IntegerOverflowFault::_name = "intover"; 1002447SN/AFaultVect IntegerOverflowFault::_vect = 0x0501; 1012447SN/AFaultStat IntegerOverflowFault::_count; 1022447SN/A 1032447SN/A#if FULL_SYSTEM 1042447SN/A 1052447SN/Avoid MipsFault::invoke(ExecContext * xc) 1062447SN/A{ 1072447SN/A FaultBase::invoke(xc); 1082447SN/A countStat()++; 1092447SN/A 1102447SN/A // exception restart address 1112447SN/A if (setRestartAddress() || !xc->inPalMode()) 1122447SN/A xc->setMiscReg(MipsISA::IPR_EXC_ADDR, xc->readPC()); 1132447SN/A 1142447SN/A if (skipFaultingInstruction()) { 1152447SN/A // traps... skip faulting instruction. 1162447SN/A xc->setMiscReg(MipsISA::IPR_EXC_ADDR, 1172447SN/A xc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4); 1182447SN/A } 1192447SN/A 1202447SN/A xc->setPC(xc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect()); 1212447SN/A xc->setNextPC(xc->readPC() + sizeof(MachInst)); 1222447SN/A} 1232447SN/A 1242447SN/Avoid ArithmeticFault::invoke(ExecContext * xc) 1252447SN/A{ 1262447SN/A FaultBase::invoke(xc); 1272447SN/A panic("Arithmetic traps are unimplemented!"); 1282447SN/A} 1292447SN/A 1302447SN/A#endif 1312447SN/A 1322447SN/A} // namespace MipsISA 1332447SN/A 134