faults.cc revision 2665
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Korey Sewell 29 */ 30 31#include "arch/mips/faults.hh" 32#include "cpu/exec_context.hh" 33#include "cpu/base.hh" 34#include "base/trace.hh" 35 36namespace MipsISA 37{ 38 39FaultName MachineCheckFault::_name = "Machine Check"; 40FaultVect MachineCheckFault::_vect = 0x0401; 41FaultStat MachineCheckFault::_count; 42 43FaultName AlignmentFault::_name = "Alignment"; 44FaultVect AlignmentFault::_vect = 0x0301; 45FaultStat AlignmentFault::_count; 46 47FaultName ResetFault::_name = "reset"; 48FaultVect ResetFault::_vect = 0x0001; 49FaultStat ResetFault::_count; 50 51FaultName ArithmeticFault::_name = "arith"; 52FaultVect ArithmeticFault::_vect = 0x0501; 53FaultStat ArithmeticFault::_count; 54 55FaultName InterruptFault::_name = "interrupt"; 56FaultVect InterruptFault::_vect = 0x0101; 57FaultStat InterruptFault::_count; 58 59FaultName NDtbMissFault::_name = "dtb_miss_single"; 60FaultVect NDtbMissFault::_vect = 0x0201; 61FaultStat NDtbMissFault::_count; 62 63FaultName PDtbMissFault::_name = "dtb_miss_double"; 64FaultVect PDtbMissFault::_vect = 0x0281; 65FaultStat PDtbMissFault::_count; 66 67FaultName DtbPageFault::_name = "dfault"; 68FaultVect DtbPageFault::_vect = 0x0381; 69FaultStat DtbPageFault::_count; 70 71FaultName DtbAcvFault::_name = "dfault"; 72FaultVect DtbAcvFault::_vect = 0x0381; 73FaultStat DtbAcvFault::_count; 74 75FaultName ItbMissFault::_name = "itbmiss"; 76FaultVect ItbMissFault::_vect = 0x0181; 77FaultStat ItbMissFault::_count; 78 79FaultName ItbPageFault::_name = "itbmiss"; 80FaultVect ItbPageFault::_vect = 0x0181; 81FaultStat ItbPageFault::_count; 82 83FaultName ItbAcvFault::_name = "iaccvio"; 84FaultVect ItbAcvFault::_vect = 0x0081; 85FaultStat ItbAcvFault::_count; 86 87FaultName UnimplementedOpcodeFault::_name = "opdec"; 88FaultVect UnimplementedOpcodeFault::_vect = 0x0481; 89FaultStat UnimplementedOpcodeFault::_count; 90 91FaultName FloatEnableFault::_name = "fen"; 92FaultVect FloatEnableFault::_vect = 0x0581; 93FaultStat FloatEnableFault::_count; 94 95FaultName PalFault::_name = "pal"; 96FaultVect PalFault::_vect = 0x2001; 97FaultStat PalFault::_count; 98 99FaultName IntegerOverflowFault::_name = "intover"; 100FaultVect IntegerOverflowFault::_vect = 0x0501; 101FaultStat IntegerOverflowFault::_count; 102 103#if FULL_SYSTEM 104 105void MipsFault::invoke(ExecContext * xc) 106{ 107 FaultBase::invoke(xc); 108 countStat()++; 109 110 // exception restart address 111 if (setRestartAddress() || !xc->inPalMode()) 112 xc->setMiscReg(MipsISA::IPR_EXC_ADDR, xc->readPC()); 113 114 if (skipFaultingInstruction()) { 115 // traps... skip faulting instruction. 116 xc->setMiscReg(MipsISA::IPR_EXC_ADDR, 117 xc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4); 118 } 119 120 xc->setPC(xc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect()); 121 xc->setNextPC(xc->readPC() + sizeof(MachInst)); 122} 123 124void ArithmeticFault::invoke(ExecContext * xc) 125{ 126 FaultBase::invoke(xc); 127 panic("Arithmetic traps are unimplemented!"); 128} 129 130#endif 131 132} // namespace MipsISA 133 134