1/*
2 * Copyright (c) 2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * Author: Anthony Gutierrez
34 */
35
36#include "arch/hsail/insts/branch.hh"
37
38#include "gpu-compute/hsail_code.hh"
39
40namespace HsailISA
41{
42    GPUStaticInst*
43    decodeBrn(const Brig::BrigInstBase *ib, const BrigObject *obj)
44    {
45        // Detect direct vs indirect branch by seeing whether we have a
46        // register operand.
47        unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
48        const Brig::BrigOperand *reg = obj->getOperand(op_offs);
49
50        if (reg->kind == Brig::BRIG_KIND_OPERAND_REGISTER) {
51            return new BrnIndirectInst(ib, obj);
52        } else {
53            return new BrnDirectInst(ib, obj);
54        }
55    }
56
57    GPUStaticInst*
58    decodeCbr(const Brig::BrigInstBase *ib, const BrigObject *obj)
59    {
60        // Detect direct vs indirect branch by seeing whether we have a
61        // second register operand (after the condition).
62        unsigned op_offs = obj->getOperandPtr(ib->operands, 1);
63        const Brig::BrigOperand *reg = obj->getOperand(op_offs);
64
65        if (reg->kind == Brig::BRIG_KIND_OPERAND_REGISTER) {
66            return new CbrIndirectInst(ib, obj);
67        } else {
68            return new CbrDirectInst(ib, obj);
69        }
70    }
71
72    GPUStaticInst*
73    decodeBr(const Brig::BrigInstBase *ib, const BrigObject *obj)
74    {
75        // Detect direct vs indirect branch by seeing whether we have a
76        // second register operand (after the condition).
77        unsigned op_offs = obj->getOperandPtr(ib->operands, 1);
78        const Brig::BrigOperand *reg = obj->getOperand(op_offs);
79
80        if (reg->kind == Brig::BRIG_KIND_OPERAND_REGISTER) {
81            return new BrIndirectInst(ib, obj);
82        } else {
83            return new BrDirectInst(ib, obj);
84        }
85    }
86} // namespace HsailISA
87