memhelpers.hh revision 11303:f694764d656d
110802Srene.dejong@arm.com/* 210802Srene.dejong@arm.com * Copyright (c) 2013 ARM Limited 310802Srene.dejong@arm.com * All rights reserved 410802Srene.dejong@arm.com * 510802Srene.dejong@arm.com * The license below extends only to copyright in the software and shall 610802Srene.dejong@arm.com * not be construed as granting a license to any other intellectual 710802Srene.dejong@arm.com * property including but not limited to intellectual property relating 810802Srene.dejong@arm.com * to a hardware implementation of the functionality of the software 910802Srene.dejong@arm.com * licensed hereunder. You may use the software subject to the license 1010802Srene.dejong@arm.com * terms below provided that you ensure that this notice is replicated 1110802Srene.dejong@arm.com * unmodified and in its entirety in all distributions of the software, 1210802Srene.dejong@arm.com * modified or unmodified, in source code or in binary form. 1310802Srene.dejong@arm.com * 1410802Srene.dejong@arm.com * Copyright (c) 2011 Google 1510802Srene.dejong@arm.com * All rights reserved. 1610802Srene.dejong@arm.com * 1710802Srene.dejong@arm.com * Redistribution and use in source and binary forms, with or without 1810802Srene.dejong@arm.com * modification, are permitted provided that the following conditions are 1910802Srene.dejong@arm.com * met: redistributions of source code must retain the above copyright 2010802Srene.dejong@arm.com * notice, this list of conditions and the following disclaimer; 2110802Srene.dejong@arm.com * redistributions in binary form must reproduce the above copyright 2210802Srene.dejong@arm.com * notice, this list of conditions and the following disclaimer in the 2310802Srene.dejong@arm.com * documentation and/or other materials provided with the distribution; 2410802Srene.dejong@arm.com * neither the name of the copyright holders nor the names of its 2510802Srene.dejong@arm.com * contributors may be used to endorse or promote products derived from 2610802Srene.dejong@arm.com * this software without specific prior written permission. 2710802Srene.dejong@arm.com * 2810802Srene.dejong@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2910802Srene.dejong@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3010802Srene.dejong@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3110802Srene.dejong@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3210802Srene.dejong@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3310802Srene.dejong@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3410802Srene.dejong@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3510802Srene.dejong@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3610802Srene.dejong@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3710802Srene.dejong@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3810802Srene.dejong@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3910802Srene.dejong@arm.com * 4010802Srene.dejong@arm.com * Authors: Gabe Black 4110802Srene.dejong@arm.com */ 4210802Srene.dejong@arm.com 4310802Srene.dejong@arm.com#ifndef __ARCH_GENERIC_MEMHELPERS_HH__ 4410802Srene.dejong@arm.com#define __ARCH_GENERIC_MEMHELPERS_HH__ 4510802Srene.dejong@arm.com 4610802Srene.dejong@arm.com#include "base/types.hh" 4710802Srene.dejong@arm.com#include "mem/request.hh" 4810802Srene.dejong@arm.com#include "sim/byteswap.hh" 4910802Srene.dejong@arm.com#include "sim/insttracer.hh" 5010802Srene.dejong@arm.com 5110802Srene.dejong@arm.com/// Initiate a read from memory in timing mode. Note that the 'mem' 5210802Srene.dejong@arm.com/// parameter is unused; only the type of that parameter is used 5310802Srene.dejong@arm.com/// to determine the size of the access. 5410802Srene.dejong@arm.comtemplate <class XC, class MemT> 5510802Srene.dejong@arm.comFault 5610802Srene.dejong@arm.cominitiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr, 5710802Srene.dejong@arm.com MemT &mem, unsigned flags) 5810802Srene.dejong@arm.com{ 5910802Srene.dejong@arm.com return xc->initiateMemRead(addr, sizeof(MemT), flags); 6010802Srene.dejong@arm.com} 6110802Srene.dejong@arm.com 6210802Srene.dejong@arm.com/// Extract the data returned from a timing mode read. 6310802Srene.dejong@arm.comtemplate <class MemT> 6410802Srene.dejong@arm.comvoid 6510802Srene.dejong@arm.comgetMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData) 6610802Srene.dejong@arm.com{ 6710802Srene.dejong@arm.com mem = pkt->get<MemT>(); 6810802Srene.dejong@arm.com if (traceData) 6910802Srene.dejong@arm.com traceData->setData(mem); 7010802Srene.dejong@arm.com} 7110802Srene.dejong@arm.com 7210802Srene.dejong@arm.com/// Read from memory in atomic mode. 7310802Srene.dejong@arm.comtemplate <class XC, class MemT> 7410802Srene.dejong@arm.comFault 7510802Srene.dejong@arm.comreadMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem, 7610802Srene.dejong@arm.com unsigned flags) 7710802Srene.dejong@arm.com{ 7810802Srene.dejong@arm.com memset(&mem, 0, sizeof(mem)); 7910802Srene.dejong@arm.com Fault fault = xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags); 8010802Srene.dejong@arm.com if (fault == NoFault) { 8110802Srene.dejong@arm.com mem = TheISA::gtoh(mem); 8210802Srene.dejong@arm.com if (traceData) 8310802Srene.dejong@arm.com traceData->setData(mem); 8410802Srene.dejong@arm.com } 8510802Srene.dejong@arm.com return fault; 8610802Srene.dejong@arm.com} 8710802Srene.dejong@arm.com 8810802Srene.dejong@arm.com/// Write to memory in timing mode. 8910802Srene.dejong@arm.comtemplate <class XC, class MemT> 9010802Srene.dejong@arm.comFault 9110802Srene.dejong@arm.comwriteMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr, 9210802Srene.dejong@arm.com unsigned flags, uint64_t *res) 9310802Srene.dejong@arm.com{ 9410802Srene.dejong@arm.com if (traceData) { 9510802Srene.dejong@arm.com traceData->setData(mem); 9610802Srene.dejong@arm.com } 9710802Srene.dejong@arm.com mem = TheISA::htog(mem); 9810802Srene.dejong@arm.com return xc->writeMem((uint8_t *)&mem, sizeof(MemT), addr, flags, res); 9910802Srene.dejong@arm.com} 10010802Srene.dejong@arm.com 10110802Srene.dejong@arm.com/// Write to memory in atomic mode. 10210802Srene.dejong@arm.comtemplate <class XC, class MemT> 10310802Srene.dejong@arm.comFault 10410802Srene.dejong@arm.comwriteMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem, 10510802Srene.dejong@arm.com Addr addr, unsigned flags, uint64_t *res) 10610802Srene.dejong@arm.com{ 10710802Srene.dejong@arm.com if (traceData) { 10810802Srene.dejong@arm.com traceData->setData(mem); 10910802Srene.dejong@arm.com } 11010802Srene.dejong@arm.com MemT host_mem = TheISA::htog(mem); 11110802Srene.dejong@arm.com Fault fault = 11210802Srene.dejong@arm.com xc->writeMem((uint8_t *)&host_mem, sizeof(MemT), addr, flags, res); 11310802Srene.dejong@arm.com if (fault == NoFault && res != NULL) { 11410802Srene.dejong@arm.com if (flags & Request::MEM_SWAP || flags & Request::MEM_SWAP_COND) 11510802Srene.dejong@arm.com *res = TheISA::gtoh((MemT)*res); 11610802Srene.dejong@arm.com else 11710802Srene.dejong@arm.com *res = TheISA::gtoh(*res); 11810802Srene.dejong@arm.com } 11910802Srene.dejong@arm.com return fault; 12010802Srene.dejong@arm.com} 12110802Srene.dejong@arm.com 12210802Srene.dejong@arm.com#endif 12310802Srene.dejong@arm.com