utility.hh revision 7692:8173327c9c65 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Korey Sewell
42 *          Stephen Hines
43 */
44
45#ifndef __ARCH_ARM_UTILITY_HH__
46#define __ARCH_ARM_UTILITY_HH__
47
48#include "arch/arm/isa_traits.hh"
49#include "arch/arm/miscregs.hh"
50#include "arch/arm/types.hh"
51#include "base/misc.hh"
52#include "base/trace.hh"
53#include "base/types.hh"
54#include "cpu/thread_context.hh"
55
56namespace ArmISA {
57
58    inline bool
59    testPredicate(CPSR cpsr, ConditionCode code)
60    {
61        switch (code)
62        {
63            case COND_EQ: return  cpsr.z;
64            case COND_NE: return !cpsr.z;
65            case COND_CS: return  cpsr.c;
66            case COND_CC: return !cpsr.c;
67            case COND_MI: return  cpsr.n;
68            case COND_PL: return !cpsr.n;
69            case COND_VS: return  cpsr.v;
70            case COND_VC: return !cpsr.v;
71            case COND_HI: return  (cpsr.c && !cpsr.z);
72            case COND_LS: return !(cpsr.c && !cpsr.z);
73            case COND_GE: return !(cpsr.n ^ cpsr.v);
74            case COND_LT: return  (cpsr.n ^ cpsr.v);
75            case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z);
76            case COND_LE: return  (cpsr.n ^ cpsr.v || cpsr.z);
77            case COND_AL: return true;
78            case COND_UC: return true;
79            default:
80                panic("Unhandled predicate condition: %d\n", code);
81        }
82    }
83
84    /**
85     * Function to insure ISA semantics about 0 registers.
86     * @param tc The thread context.
87     */
88    template <class TC>
89    void zeroRegisters(TC *tc);
90
91    inline void startupCPU(ThreadContext *tc, int cpuId)
92    {
93        tc->activate(0);
94    }
95
96    static inline bool
97    isThumb(Addr pc)
98    {
99        return (pc & PcTBit);
100    }
101
102    static inline void
103    copyRegs(ThreadContext *src, ThreadContext *dest)
104    {
105        panic("Copy Regs Not Implemented Yet\n");
106    }
107
108    static inline void
109    copyMiscRegs(ThreadContext *src, ThreadContext *dest)
110    {
111        panic("Copy Misc. Regs Not Implemented Yet\n");
112    }
113
114    void initCPU(ThreadContext *tc, int cpuId);
115
116    static inline bool
117    inUserMode(CPSR cpsr)
118    {
119        return cpsr.mode == MODE_USER;
120    }
121
122    static inline bool
123    inUserMode(ThreadContext *tc)
124    {
125        return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
126    }
127
128    static inline bool
129    inPrivilegedMode(CPSR cpsr)
130    {
131        return !inUserMode(cpsr);
132    }
133
134    static inline bool
135    inPrivilegedMode(ThreadContext *tc)
136    {
137        return !inUserMode(tc);
138    }
139
140    static inline bool
141    vfpEnabled(CPACR cpacr, CPSR cpsr)
142    {
143        return cpacr.cp10 == 0x3 ||
144            (cpacr.cp10 == 0x1 && inPrivilegedMode(cpsr));
145    }
146
147    static inline bool
148    vfpEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
149    {
150        return fpexc.en && vfpEnabled(cpacr, cpsr);
151    }
152
153    static inline bool
154    neonEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
155    {
156        return !cpacr.asedis && vfpEnabled(cpacr, cpsr, fpexc);
157    }
158
159uint64_t getArgument(ThreadContext *tc, int number, bool fp);
160
161Fault setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
162Fault readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
163
164};
165
166
167#endif
168