utility.hh revision 7680:f4eda002333b 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Korey Sewell
42 *          Stephen Hines
43 */
44
45#ifndef __ARCH_ARM_UTILITY_HH__
46#define __ARCH_ARM_UTILITY_HH__
47
48#include "arch/arm/miscregs.hh"
49#include "arch/arm/types.hh"
50#include "base/misc.hh"
51#include "base/trace.hh"
52#include "base/types.hh"
53#include "cpu/thread_context.hh"
54
55namespace ArmISA {
56
57    inline bool
58    testPredicate(CPSR cpsr, ConditionCode code)
59    {
60        switch (code)
61        {
62            case COND_EQ: return  cpsr.z;
63            case COND_NE: return !cpsr.z;
64            case COND_CS: return  cpsr.c;
65            case COND_CC: return !cpsr.c;
66            case COND_MI: return  cpsr.n;
67            case COND_PL: return !cpsr.n;
68            case COND_VS: return  cpsr.v;
69            case COND_VC: return !cpsr.v;
70            case COND_HI: return  (cpsr.c && !cpsr.z);
71            case COND_LS: return !(cpsr.c && !cpsr.z);
72            case COND_GE: return !(cpsr.n ^ cpsr.v);
73            case COND_LT: return  (cpsr.n ^ cpsr.v);
74            case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z);
75            case COND_LE: return  (cpsr.n ^ cpsr.v || cpsr.z);
76            case COND_AL: return true;
77            case COND_UC: return true;
78            default:
79                panic("Unhandled predicate condition: %d\n", code);
80        }
81    }
82
83    /**
84     * Function to insure ISA semantics about 0 registers.
85     * @param tc The thread context.
86     */
87    template <class TC>
88    void zeroRegisters(TC *tc);
89
90    inline void startupCPU(ThreadContext *tc, int cpuId)
91    {
92        tc->activate(0);
93    }
94
95    static inline void
96    copyRegs(ThreadContext *src, ThreadContext *dest)
97    {
98        panic("Copy Regs Not Implemented Yet\n");
99    }
100
101    static inline void
102    copyMiscRegs(ThreadContext *src, ThreadContext *dest)
103    {
104        panic("Copy Misc. Regs Not Implemented Yet\n");
105    }
106
107    void initCPU(ThreadContext *tc, int cpuId);
108
109    static inline bool
110    inUserMode(CPSR cpsr)
111    {
112        return cpsr.mode == MODE_USER;
113    }
114
115    static inline bool
116    inUserMode(ThreadContext *tc)
117    {
118        return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
119    }
120
121    static inline bool
122    inPrivilegedMode(CPSR cpsr)
123    {
124        return !inUserMode(cpsr);
125    }
126
127    static inline bool
128    inPrivilegedMode(ThreadContext *tc)
129    {
130        return !inUserMode(tc);
131    }
132
133    static inline bool
134    vfpEnabled(CPACR cpacr, CPSR cpsr)
135    {
136        return cpacr.cp10 == 0x3 ||
137            (cpacr.cp10 == 0x1 && inPrivilegedMode(cpsr));
138    }
139
140    static inline bool
141    vfpEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
142    {
143        return fpexc.en && vfpEnabled(cpacr, cpsr);
144    }
145
146    static inline bool
147    neonEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc)
148    {
149        return !cpacr.asedis && vfpEnabled(cpacr, cpsr, fpexc);
150    }
151
152uint64_t getArgument(ThreadContext *tc, int number, bool fp);
153
154Fault setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
155Fault readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
156
157};
158
159
160#endif
161