utility.hh revision 7426:5da64155a605 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Korey Sewell
42 *          Stephen Hines
43 */
44
45#ifndef __ARCH_ARM_UTILITY_HH__
46#define __ARCH_ARM_UTILITY_HH__
47
48#include "arch/arm/miscregs.hh"
49#include "arch/arm/types.hh"
50#include "base/hashmap.hh"
51#include "base/trace.hh"
52#include "base/types.hh"
53#include "cpu/thread_context.hh"
54
55namespace __hash_namespace {
56    template<>
57    struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> {
58        size_t operator()(const ArmISA::ExtMachInst &emi) const {
59            return hash<uint32_t>::operator()((uint32_t)emi);
60        };
61    };
62}
63
64namespace ArmISA {
65
66    inline bool
67    testPredicate(CPSR cpsr, ConditionCode code)
68    {
69        switch (code)
70        {
71            case COND_EQ: return  cpsr.z;
72            case COND_NE: return !cpsr.z;
73            case COND_CS: return  cpsr.c;
74            case COND_CC: return !cpsr.c;
75            case COND_MI: return  cpsr.n;
76            case COND_PL: return !cpsr.n;
77            case COND_VS: return  cpsr.v;
78            case COND_VC: return !cpsr.v;
79            case COND_HI: return  (cpsr.c && !cpsr.z);
80            case COND_LS: return !(cpsr.c && !cpsr.z);
81            case COND_GE: return !(cpsr.n ^ cpsr.v);
82            case COND_LT: return  (cpsr.n ^ cpsr.v);
83            case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z);
84            case COND_LE: return  (cpsr.n ^ cpsr.v || cpsr.z);
85            case COND_AL: return true;
86            case COND_UC: return true;
87            default:
88                panic("Unhandled predicate condition: %d\n", code);
89        }
90    }
91
92    /**
93     * Function to insure ISA semantics about 0 registers.
94     * @param tc The thread context.
95     */
96    template <class TC>
97    void zeroRegisters(TC *tc);
98
99    // Instruction address compression hooks
100    static inline Addr realPCToFetchPC(const Addr &addr) {
101        return addr;
102    }
103
104    static inline Addr fetchPCToRealPC(const Addr &addr) {
105        return addr;
106    }
107
108    // the size of "fetched" instructions
109    static inline size_t fetchInstSize() {
110        return sizeof(MachInst);
111    }
112
113    static inline MachInst makeRegisterCopy(int dest, int src) {
114        panic("makeRegisterCopy not implemented");
115        return 0;
116    }
117
118    inline void startupCPU(ThreadContext *tc, int cpuId)
119    {
120        tc->activate(0);
121    }
122
123    template <class XC>
124    Fault
125    checkFpEnableFault(XC *xc)
126    {
127        return NoFault;
128    }
129
130    static inline void
131    copyRegs(ThreadContext *src, ThreadContext *dest)
132    {
133        panic("Copy Regs Not Implemented Yet\n");
134    }
135
136    static inline void
137    copyMiscRegs(ThreadContext *src, ThreadContext *dest)
138    {
139        panic("Copy Misc. Regs Not Implemented Yet\n");
140    }
141
142    void initCPU(ThreadContext *tc, int cpuId);
143
144    static inline bool
145    inUserMode(ThreadContext *tc)
146    {
147        return (tc->readMiscRegNoEffect(MISCREG_CPSR) & 0x1f) == MODE_USER;
148    }
149
150uint64_t getArgument(ThreadContext *tc, int number, bool fp);
151
152Fault setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
153Fault readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
154
155};
156
157
158#endif
159