utility.hh revision 6242:1cee707c1228 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Korey Sewell
30 *          Stephen Hines
31 */
32
33#ifndef __ARCH_ARM_UTILITY_HH__
34#define __ARCH_ARM_UTILITY_HH__
35
36#include "arch/arm/miscregs.hh"
37#include "arch/arm/types.hh"
38#include "base/misc.hh"
39#include "base/types.hh"
40#include "config/full_system.hh"
41#include "cpu/thread_context.hh"
42
43class ThreadContext;
44
45namespace ArmISA {
46
47    inline bool
48    testPredicate(CPSR cpsr, ConditionCode code)
49    {
50        switch (code)
51        {
52            case COND_EQ: return  cpsr.z;
53            case COND_NE: return !cpsr.z;
54            case COND_CS: return  cpsr.c;
55            case COND_CC: return !cpsr.c;
56            case COND_MI: return  cpsr.n;
57            case COND_PL: return !cpsr.n;
58            case COND_VS: return  cpsr.v;
59            case COND_VC: return !cpsr.v;
60            case COND_HI: return  (cpsr.c && !cpsr.z);
61            case COND_LS: return !(cpsr.c && !cpsr.z);
62            case COND_GE: return !(cpsr.n ^ cpsr.v);
63            case COND_LT: return  (cpsr.n ^ cpsr.v);
64            case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z);
65            case COND_LE: return  (cpsr.n ^ cpsr.v || cpsr.z);
66            case COND_AL: return true;
67            case COND_NV: return false;
68            default:
69                panic("Unhandled predicate condition: %d\n", code);
70        }
71    }
72
73    //Floating Point Utility Functions
74    uint64_t fpConvert(ConvertType cvt_type, double fp_val);
75    double roundFP(double val, int digits);
76    double truncFP(double val);
77
78    bool getCondCode(uint32_t fcsr, int cc);
79    uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val);
80    uint32_t genInvalidVector(uint32_t fcsr);
81
82    bool isNan(void *val_ptr, int size);
83    bool isQnan(void *val_ptr, int size);
84    bool isSnan(void *val_ptr, int size);
85
86    /**
87     * Function to insure ISA semantics about 0 registers.
88     * @param tc The thread context.
89     */
90    template <class TC>
91    void zeroRegisters(TC *tc);
92
93    // Instruction address compression hooks
94    static inline Addr realPCToFetchPC(const Addr &addr) {
95        return addr;
96    }
97
98    static inline Addr fetchPCToRealPC(const Addr &addr) {
99        return addr;
100    }
101
102    // the size of "fetched" instructions
103    static inline size_t fetchInstSize() {
104        return sizeof(MachInst);
105    }
106
107    static inline MachInst makeRegisterCopy(int dest, int src) {
108        panic("makeRegisterCopy not implemented");
109        return 0;
110    }
111
112    inline void startupCPU(ThreadContext *tc, int cpuId)
113    {
114        tc->activate(0);
115    }
116};
117
118
119#endif
120