utility.hh revision 6214:1ec0ec8933ae 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Korey Sewell
30 *          Stephen Hines
31 */
32
33#ifndef __ARCH_ARM_UTILITY_HH__
34#define __ARCH_ARM_UTILITY_HH__
35
36#include "arch/arm/types.hh"
37#include "base/misc.hh"
38#include "config/full_system.hh"
39#include "cpu/thread_context.hh"
40#include "base/types.hh"
41
42class ThreadContext;
43
44namespace ArmISA {
45
46    //Floating Point Utility Functions
47    uint64_t fpConvert(ConvertType cvt_type, double fp_val);
48    double roundFP(double val, int digits);
49    double truncFP(double val);
50
51    bool getCondCode(uint32_t fcsr, int cc);
52    uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val);
53    uint32_t genInvalidVector(uint32_t fcsr);
54
55    bool isNan(void *val_ptr, int size);
56    bool isQnan(void *val_ptr, int size);
57    bool isSnan(void *val_ptr, int size);
58
59    /**
60     * Function to insure ISA semantics about 0 registers.
61     * @param tc The thread context.
62     */
63    template <class TC>
64    void zeroRegisters(TC *tc);
65
66    // Instruction address compression hooks
67    static inline Addr realPCToFetchPC(const Addr &addr) {
68        return addr;
69    }
70
71    static inline Addr fetchPCToRealPC(const Addr &addr) {
72        return addr;
73    }
74
75    // the size of "fetched" instructions
76    static inline size_t fetchInstSize() {
77        return sizeof(MachInst);
78    }
79
80    static inline MachInst makeRegisterCopy(int dest, int src) {
81        panic("makeRegisterCopy not implemented");
82        return 0;
83    }
84
85    inline void startupCPU(ThreadContext *tc, int cpuId)
86    {
87        tc->activate(0);
88    }
89};
90
91
92#endif
93