utility.hh revision 12494
1/*
2 * Copyright (c) 2010, 2012-2013, 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Korey Sewell
42 *          Stephen Hines
43 */
44
45#ifndef __ARCH_ARM_UTILITY_HH__
46#define __ARCH_ARM_UTILITY_HH__
47
48#include "arch/arm/isa_traits.hh"
49#include "arch/arm/miscregs.hh"
50#include "arch/arm/types.hh"
51#include "base/logging.hh"
52#include "base/trace.hh"
53#include "base/types.hh"
54#include "cpu/static_inst.hh"
55#include "cpu/thread_context.hh"
56
57class ArmSystem;
58
59namespace ArmISA {
60
61inline PCState
62buildRetPC(const PCState &curPC, const PCState &callPC)
63{
64    PCState retPC = callPC;
65    retPC.uEnd();
66    return retPC;
67}
68
69inline bool
70testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
71{
72    bool n = (nz & 0x2);
73    bool z = (nz & 0x1);
74
75    switch (code)
76    {
77        case COND_EQ: return  z;
78        case COND_NE: return !z;
79        case COND_CS: return  c;
80        case COND_CC: return !c;
81        case COND_MI: return  n;
82        case COND_PL: return !n;
83        case COND_VS: return  v;
84        case COND_VC: return !v;
85        case COND_HI: return  (c && !z);
86        case COND_LS: return !(c && !z);
87        case COND_GE: return !(n ^ v);
88        case COND_LT: return  (n ^ v);
89        case COND_GT: return !(n ^ v || z);
90        case COND_LE: return  (n ^ v || z);
91        case COND_AL: return true;
92        case COND_UC: return true;
93        default:
94            panic("Unhandled predicate condition: %d\n", code);
95    }
96}
97
98/**
99 * Function to insure ISA semantics about 0 registers.
100 * @param tc The thread context.
101 */
102template <class TC>
103void zeroRegisters(TC *tc);
104
105inline void startupCPU(ThreadContext *tc, int cpuId)
106{
107    tc->activate();
108}
109
110void copyRegs(ThreadContext *src, ThreadContext *dest);
111
112static inline void
113copyMiscRegs(ThreadContext *src, ThreadContext *dest)
114{
115    panic("Copy Misc. Regs Not Implemented Yet\n");
116}
117
118void initCPU(ThreadContext *tc, int cpuId);
119
120static inline bool
121inUserMode(CPSR cpsr)
122{
123    return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T;
124}
125
126static inline bool
127inUserMode(ThreadContext *tc)
128{
129    return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
130}
131
132static inline bool
133inPrivilegedMode(CPSR cpsr)
134{
135    return !inUserMode(cpsr);
136}
137
138static inline bool
139inPrivilegedMode(ThreadContext *tc)
140{
141    return !inUserMode(tc);
142}
143
144bool inAArch64(ThreadContext *tc);
145
146static inline OperatingMode
147currOpMode(ThreadContext *tc)
148{
149    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
150    return (OperatingMode) (uint8_t) cpsr.mode;
151}
152
153static inline ExceptionLevel
154currEL(ThreadContext *tc)
155{
156    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
157    return (ExceptionLevel) (uint8_t) cpsr.el;
158}
159
160bool ELIs32(ThreadContext *tc, ExceptionLevel el);
161
162bool ELIs64(ThreadContext *tc, ExceptionLevel el);
163
164bool isBigEndian64(ThreadContext *tc);
165
166static inline uint8_t
167itState(CPSR psr)
168{
169    ITSTATE it = 0;
170    it.top6 = psr.it2;
171    it.bottom2 = psr.it1;
172
173    return (uint8_t)it;
174}
175
176/**
177 * Removes the tag from tagged addresses if that mode is enabled.
178 * @param addr The address to be purified.
179 * @param tc The thread context.
180 * @param el The controlled exception level.
181 * @return The purified address.
182 */
183Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
184                      TTBCR tcr);
185Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el);
186
187static inline bool
188inSecureState(SCR scr, CPSR cpsr)
189{
190    switch ((OperatingMode) (uint8_t) cpsr.mode) {
191      case MODE_MON:
192      case MODE_EL3T:
193      case MODE_EL3H:
194        return true;
195      case MODE_HYP:
196      case MODE_EL2T:
197      case MODE_EL2H:
198        return false;
199      default:
200        return !scr.ns;
201    }
202}
203
204bool longDescFormatInUse(ThreadContext *tc);
205
206bool inSecureState(ThreadContext *tc);
207
208uint32_t getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
209
210static inline uint32_t
211mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn,
212               uint32_t opc1, uint32_t opc2)
213{
214    return (isRead <<  0) |
215           (crm    <<  1) |
216           (rt     <<  5) |
217           (crn    << 10) |
218           (opc1   << 14) |
219           (opc2   << 17);
220}
221
222static inline void
223mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt,
224                 uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
225{
226    isRead = (iss >>  0) & 0x1;
227    crm    = (iss >>  1) & 0xF;
228    rt     = (IntRegIndex) ((iss >>  5) & 0xF);
229    crn    = (iss >> 10) & 0xF;
230    opc1   = (iss >> 14) & 0x7;
231    opc2   = (iss >> 17) & 0x7;
232}
233
234static inline uint32_t
235mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2,
236                 uint32_t opc1)
237{
238    return (isRead <<  0) |
239           (crm    <<  1) |
240           (rt     <<  5) |
241           (rt2    << 10) |
242           (opc1   << 16);
243}
244
245static inline uint32_t
246msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn,
247                 uint32_t crm, uint32_t op2, IntRegIndex rt)
248{
249    return isRead |
250        (crm << 1) |
251        (rt << 5) |
252        (crn << 10) |
253        (op1 << 14) |
254        (op2 << 17) |
255        (op0 << 20);
256}
257
258bool
259mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
260                  HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
261bool
262mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
263                  HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
264bool
265mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
266                    HCR hcr, uint32_t iss);
267
268bool msrMrs64TrapToSup(const MiscRegIndex miscReg, ExceptionLevel el,
269                       CPACR cpacr);
270bool msrMrs64TrapToHyp(const MiscRegIndex miscReg, ExceptionLevel el,
271                       bool isRead, CPTR cptr, HCR hcr, bool * isVfpNeon);
272bool msrMrs64TrapToMon(const MiscRegIndex miscReg, CPTR cptr,
273                       ExceptionLevel el, bool * isVfpNeon);
274
275bool SPAlignmentCheckEnabled(ThreadContext* tc);
276
277uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
278
279void skipFunction(ThreadContext *tc);
280
281inline void
282advancePC(PCState &pc, const StaticInstPtr &inst)
283{
284    inst->advancePC(pc);
285}
286
287Addr truncPage(Addr addr);
288Addr roundPage(Addr addr);
289
290inline uint64_t
291getExecutingAsid(ThreadContext *tc)
292{
293    return tc->readMiscReg(MISCREG_CONTEXTIDR);
294}
295
296// Decodes the register index to access based on the fields used in a MSR
297// or MRS instruction
298bool
299decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int &regIdx,
300                      CPSR cpsr, SCR scr, NSACR nsacr,
301                      bool checkSecurity = true);
302
303// This wrapper function is used to turn the register index into a source
304// parameter for the instruction. See Operands.isa
305static inline int
306decodeMrsMsrBankedIntRegIndex(uint8_t sysM, bool r)
307{
308    int  regIdx;
309    bool isIntReg;
310    bool validReg;
311
312    validReg = decodeMrsMsrBankedReg(sysM, r, isIntReg, regIdx, 0, 0, 0, false);
313    return (validReg && isIntReg) ? regIdx : INTREG_DUMMY;
314}
315
316/**
317 * Returns the n. of PA bits corresponding to the specified encoding.
318 */
319int decodePhysAddrRange64(uint8_t pa_enc);
320
321/**
322 * Returns the encoding corresponding to the specified n. of PA bits.
323 */
324uint8_t encodePhysAddrRange64(int pa_size);
325
326}
327
328#endif
329