utility.hh revision 7720
12381SN/A/* 213732Snikos.nikoleris@arm.com * Copyright (c) 2010 ARM Limited 38949Sandreas.hansson@arm.com * All rights reserved 48949Sandreas.hansson@arm.com * 58949Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68949Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78949Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88949Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98949Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108949Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118949Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128949Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138949Sandreas.hansson@arm.com * 142592SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 1510975Sdavid.hashe@amd.com * Copyright (c) 2007-2008 The Florida State University 162381SN/A * All rights reserved. 172381SN/A * 182381SN/A * Redistribution and use in source and binary forms, with or without 192381SN/A * modification, are permitted provided that the following conditions are 202381SN/A * met: redistributions of source code must retain the above copyright 212381SN/A * notice, this list of conditions and the following disclaimer; 222381SN/A * redistributions in binary form must reproduce the above copyright 232381SN/A * notice, this list of conditions and the following disclaimer in the 242381SN/A * documentation and/or other materials provided with the distribution; 252381SN/A * neither the name of the copyright holders nor the names of its 262381SN/A * contributors may be used to endorse or promote products derived from 272381SN/A * this software without specific prior written permission. 282381SN/A * 292381SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302381SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312381SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322381SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332381SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342381SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352381SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362381SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372381SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382381SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392381SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Korey Sewell 422665Ssaidi@eecs.umich.edu * Stephen Hines 432665Ssaidi@eecs.umich.edu */ 449031Sandreas.hansson@arm.com 4512349Snikos.nikoleris@arm.com#ifndef __ARCH_ARM_UTILITY_HH__ 462381SN/A#define __ARCH_ARM_UTILITY_HH__ 472381SN/A 482381SN/A#include "arch/arm/isa_traits.hh" 492381SN/A#include "arch/arm/miscregs.hh" 502662Sstever@eecs.umich.edu#include "arch/arm/types.hh" 512381SN/A#include "base/misc.hh" 522381SN/A#include "base/trace.hh" 532381SN/A#include "base/types.hh" 542381SN/A#include "cpu/static_inst.hh" 552381SN/A#include "cpu/thread_context.hh" 568229Snate@binkert.org 573348Sbinkertn@umich.edunamespace ArmISA { 583348Sbinkertn@umich.edu 593348Sbinkertn@umich.edu inline PCState 6013856Sodanrc@yahoo.com.br buildRetPC(const PCState &curPC, const PCState &callPC) 615735Snate@binkert.org { 624024Sbinkertn@umich.edu PCState retPC = callPC; 635735Snate@binkert.org retPC.uEnd(); 6412334Sgabeblack@google.com return retPC; 655314Sstever@gmail.com } 666216Snate@binkert.org 6713347Sgabeblack@google.com inline bool 682392SN/A testPredicate(CPSR cpsr, ConditionCode code) 694167Sbinkertn@umich.edu { 702394SN/A switch (code) 718737Skoansin.tan@gmail.com { 723349Sbinkertn@umich.edu case COND_EQ: return cpsr.z; 732394SN/A case COND_NE: return !cpsr.z; 742812Srdreslin@umich.edu case COND_CS: return cpsr.c; 7512351Snikos.nikoleris@arm.com case COND_CC: return !cpsr.c; 762812Srdreslin@umich.edu case COND_MI: return cpsr.n; 774022Sstever@eecs.umich.edu case COND_PL: return !cpsr.n; 784022Sstever@eecs.umich.edu case COND_VS: return cpsr.v; 795735Snate@binkert.org case COND_VC: return !cpsr.v; 805735Snate@binkert.org case COND_HI: return (cpsr.c && !cpsr.z); 814022Sstever@eecs.umich.edu case COND_LS: return !(cpsr.c && !cpsr.z); 825735Snate@binkert.org case COND_GE: return !(cpsr.n ^ cpsr.v); 835735Snate@binkert.org case COND_LT: return (cpsr.n ^ cpsr.v); 845735Snate@binkert.org case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z); 854022Sstever@eecs.umich.edu case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z); 864022Sstever@eecs.umich.edu case COND_AL: return true; 874022Sstever@eecs.umich.edu case COND_UC: return true; 884022Sstever@eecs.umich.edu default: 894473Sstever@eecs.umich.edu panic("Unhandled predicate condition: %d\n", code); 905319Sstever@gmail.com } 914022Sstever@eecs.umich.edu } 924022Sstever@eecs.umich.edu 9311199Sandreas.hansson@arm.com /** 9411199Sandreas.hansson@arm.com * Function to insure ISA semantics about 0 registers. 9512344Snikos.nikoleris@arm.com * @param tc The thread context. 9610883Sali.jafri@arm.com */ 974022Sstever@eecs.umich.edu template <class TC> 9813367Syuetsu.kodama@riken.jp void zeroRegisters(TC *tc); 994022Sstever@eecs.umich.edu 1004022Sstever@eecs.umich.edu inline void startupCPU(ThreadContext *tc, int cpuId) 1014022Sstever@eecs.umich.edu { 10210886Sandreas.hansson@arm.com tc->activate(0); 1034022Sstever@eecs.umich.edu } 1047465Ssteve.reinhardt@amd.com 1054628Sstever@eecs.umich.edu static inline void 1067465Ssteve.reinhardt@amd.com copyRegs(ThreadContext *src, ThreadContext *dest) 1077465Ssteve.reinhardt@amd.com { 1084022Sstever@eecs.umich.edu panic("Copy Regs Not Implemented Yet\n"); 1094022Sstever@eecs.umich.edu } 11010885Sandreas.hansson@arm.com 11110885Sandreas.hansson@arm.com static inline void 1124626Sstever@eecs.umich.edu copyMiscRegs(ThreadContext *src, ThreadContext *dest) 1134626Sstever@eecs.umich.edu { 1147669Ssteve.reinhardt@amd.com panic("Copy Misc. Regs Not Implemented Yet\n"); 1154626Sstever@eecs.umich.edu } 1164040Ssaidi@eecs.umich.edu 1174040Ssaidi@eecs.umich.edu void initCPU(ThreadContext *tc, int cpuId); 1185650Sgblack@eecs.umich.edu 1195650Sgblack@eecs.umich.edu static inline bool 12011256Santhony.gutierrez@amd.com inUserMode(CPSR cpsr) 12111256Santhony.gutierrez@amd.com { 12212347Snikos.nikoleris@arm.com return cpsr.mode == MODE_USER; 12312347Snikos.nikoleris@arm.com } 12412347Snikos.nikoleris@arm.com 12512347Snikos.nikoleris@arm.com static inline bool 1264870Sstever@eecs.umich.edu inUserMode(ThreadContext *tc) 1274870Sstever@eecs.umich.edu { 1284870Sstever@eecs.umich.edu return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR)); 1294870Sstever@eecs.umich.edu } 1304870Sstever@eecs.umich.edu 1314870Sstever@eecs.umich.edu static inline bool 1328436SBrad.Beckmann@amd.com inPrivilegedMode(CPSR cpsr) 1338436SBrad.Beckmann@amd.com { 1345314Sstever@gmail.com return !inUserMode(cpsr); 1355314Sstever@gmail.com } 1368184Ssomayeh@cs.wisc.edu 13710886Sandreas.hansson@arm.com static inline bool 13810886Sandreas.hansson@arm.com inPrivilegedMode(ThreadContext *tc) 1394022Sstever@eecs.umich.edu { 1404022Sstever@eecs.umich.edu return !inUserMode(tc); 1414022Sstever@eecs.umich.edu } 1424022Sstever@eecs.umich.edu 1435735Snate@binkert.org static inline bool 1445735Snate@binkert.org vfpEnabled(CPACR cpacr, CPSR cpsr) 1455735Snate@binkert.org { 1464022Sstever@eecs.umich.edu return cpacr.cp10 == 0x3 || 1474022Sstever@eecs.umich.edu (cpacr.cp10 == 0x1 && inPrivilegedMode(cpsr)); 1484626Sstever@eecs.umich.edu } 1494626Sstever@eecs.umich.edu 1507465Ssteve.reinhardt@amd.com static inline bool 1514022Sstever@eecs.umich.edu vfpEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc) 15212347Snikos.nikoleris@arm.com { 15311284Sandreas.hansson@arm.com return fpexc.en && vfpEnabled(cpacr, cpsr); 1544626Sstever@eecs.umich.edu } 1554626Sstever@eecs.umich.edu 1564626Sstever@eecs.umich.edu static inline bool 15711199Sandreas.hansson@arm.com neonEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc) 1584022Sstever@eecs.umich.edu { 1594022Sstever@eecs.umich.edu return !cpacr.asedis && vfpEnabled(cpacr, cpsr, fpexc); 1606076Sgblack@eecs.umich.edu } 1614626Sstever@eecs.umich.edu 1624870Sstever@eecs.umich.eduuint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 1635314Sstever@gmail.com 1648184Ssomayeh@cs.wisc.eduFault setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2); 16511600Sandreas.hansson@arm.comFault readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2); 1664022Sstever@eecs.umich.edu 1674022Sstever@eecs.umich.eduvoid skipFunction(ThreadContext *tc); 1684022Sstever@eecs.umich.edu 1695735Snate@binkert.orginline void 1705735Snate@binkert.orgadvancePC(PCState &pc, const StaticInstPtr inst) 1715735Snate@binkert.org{ 1725735Snate@binkert.org inst->advancePC(pc); 1735735Snate@binkert.org} 1745735Snate@binkert.org 1755735Snate@binkert.org}; 1764022Sstever@eecs.umich.edu 1775735Snate@binkert.org 1785735Snate@binkert.org#endif 1794022Sstever@eecs.umich.edu