utility.hh revision 7707
16019Shines@cs.fsu.edu/* 27111Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37111Sgblack@eecs.umich.edu * All rights reserved 47111Sgblack@eecs.umich.edu * 57111Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67111Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77111Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87111Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97111Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107111Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117111Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127111Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137111Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416019Shines@cs.fsu.edu * Authors: Korey Sewell 426019Shines@cs.fsu.edu * Stephen Hines 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu#ifndef __ARCH_ARM_UTILITY_HH__ 466019Shines@cs.fsu.edu#define __ARCH_ARM_UTILITY_HH__ 476019Shines@cs.fsu.edu 487692SAli.Saidi@ARM.com#include "arch/arm/isa_traits.hh" 496242Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 506019Shines@cs.fsu.edu#include "arch/arm/types.hh" 517678Sgblack@eecs.umich.edu#include "base/misc.hh" 527408Sgblack@eecs.umich.edu#include "base/trace.hh" 536216Snate@binkert.org#include "base/types.hh" 546019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 556019Shines@cs.fsu.edu 566019Shines@cs.fsu.edunamespace ArmISA { 576019Shines@cs.fsu.edu 586242Sgblack@eecs.umich.edu inline bool 596242Sgblack@eecs.umich.edu testPredicate(CPSR cpsr, ConditionCode code) 606242Sgblack@eecs.umich.edu { 616242Sgblack@eecs.umich.edu switch (code) 626242Sgblack@eecs.umich.edu { 636242Sgblack@eecs.umich.edu case COND_EQ: return cpsr.z; 646242Sgblack@eecs.umich.edu case COND_NE: return !cpsr.z; 656242Sgblack@eecs.umich.edu case COND_CS: return cpsr.c; 666242Sgblack@eecs.umich.edu case COND_CC: return !cpsr.c; 676242Sgblack@eecs.umich.edu case COND_MI: return cpsr.n; 686242Sgblack@eecs.umich.edu case COND_PL: return !cpsr.n; 696242Sgblack@eecs.umich.edu case COND_VS: return cpsr.v; 706242Sgblack@eecs.umich.edu case COND_VC: return !cpsr.v; 716242Sgblack@eecs.umich.edu case COND_HI: return (cpsr.c && !cpsr.z); 726242Sgblack@eecs.umich.edu case COND_LS: return !(cpsr.c && !cpsr.z); 736242Sgblack@eecs.umich.edu case COND_GE: return !(cpsr.n ^ cpsr.v); 746242Sgblack@eecs.umich.edu case COND_LT: return (cpsr.n ^ cpsr.v); 756242Sgblack@eecs.umich.edu case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z); 766242Sgblack@eecs.umich.edu case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z); 776242Sgblack@eecs.umich.edu case COND_AL: return true; 787111Sgblack@eecs.umich.edu case COND_UC: return true; 796242Sgblack@eecs.umich.edu default: 806242Sgblack@eecs.umich.edu panic("Unhandled predicate condition: %d\n", code); 816242Sgblack@eecs.umich.edu } 826242Sgblack@eecs.umich.edu } 836242Sgblack@eecs.umich.edu 846019Shines@cs.fsu.edu /** 856019Shines@cs.fsu.edu * Function to insure ISA semantics about 0 registers. 866019Shines@cs.fsu.edu * @param tc The thread context. 876019Shines@cs.fsu.edu */ 886019Shines@cs.fsu.edu template <class TC> 896019Shines@cs.fsu.edu void zeroRegisters(TC *tc); 906019Shines@cs.fsu.edu 916019Shines@cs.fsu.edu inline void startupCPU(ThreadContext *tc, int cpuId) 926019Shines@cs.fsu.edu { 936019Shines@cs.fsu.edu tc->activate(0); 946019Shines@cs.fsu.edu } 956246Sgblack@eecs.umich.edu 967692SAli.Saidi@ARM.com static inline bool 977692SAli.Saidi@ARM.com isThumb(Addr pc) 987692SAli.Saidi@ARM.com { 997692SAli.Saidi@ARM.com return (pc & PcTBit); 1007692SAli.Saidi@ARM.com } 1017692SAli.Saidi@ARM.com 1026329Sgblack@eecs.umich.edu static inline void 1036329Sgblack@eecs.umich.edu copyRegs(ThreadContext *src, ThreadContext *dest) 1046329Sgblack@eecs.umich.edu { 1056329Sgblack@eecs.umich.edu panic("Copy Regs Not Implemented Yet\n"); 1066329Sgblack@eecs.umich.edu } 1076329Sgblack@eecs.umich.edu 1086329Sgblack@eecs.umich.edu static inline void 1096329Sgblack@eecs.umich.edu copyMiscRegs(ThreadContext *src, ThreadContext *dest) 1106329Sgblack@eecs.umich.edu { 1116329Sgblack@eecs.umich.edu panic("Copy Misc. Regs Not Implemented Yet\n"); 1126329Sgblack@eecs.umich.edu } 1136757SAli.Saidi@ARM.com 1146757SAli.Saidi@ARM.com void initCPU(ThreadContext *tc, int cpuId); 1156757SAli.Saidi@ARM.com 1166757SAli.Saidi@ARM.com static inline bool 1177638Sgblack@eecs.umich.edu inUserMode(CPSR cpsr) 1187638Sgblack@eecs.umich.edu { 1197638Sgblack@eecs.umich.edu return cpsr.mode == MODE_USER; 1207638Sgblack@eecs.umich.edu } 1217638Sgblack@eecs.umich.edu 1227638Sgblack@eecs.umich.edu static inline bool 1236757SAli.Saidi@ARM.com inUserMode(ThreadContext *tc) 1246757SAli.Saidi@ARM.com { 1257638Sgblack@eecs.umich.edu return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR)); 1267638Sgblack@eecs.umich.edu } 1277638Sgblack@eecs.umich.edu 1287638Sgblack@eecs.umich.edu static inline bool 1297638Sgblack@eecs.umich.edu inPrivilegedMode(CPSR cpsr) 1307638Sgblack@eecs.umich.edu { 1317638Sgblack@eecs.umich.edu return !inUserMode(cpsr); 1327638Sgblack@eecs.umich.edu } 1337638Sgblack@eecs.umich.edu 1347638Sgblack@eecs.umich.edu static inline bool 1357638Sgblack@eecs.umich.edu inPrivilegedMode(ThreadContext *tc) 1367638Sgblack@eecs.umich.edu { 1377638Sgblack@eecs.umich.edu return !inUserMode(tc); 1386757SAli.Saidi@ARM.com } 1396757SAli.Saidi@ARM.com 1407640Sgblack@eecs.umich.edu static inline bool 1417640Sgblack@eecs.umich.edu vfpEnabled(CPACR cpacr, CPSR cpsr) 1427640Sgblack@eecs.umich.edu { 1437640Sgblack@eecs.umich.edu return cpacr.cp10 == 0x3 || 1447644Sali.saidi@arm.com (cpacr.cp10 == 0x1 && inPrivilegedMode(cpsr)); 1457640Sgblack@eecs.umich.edu } 1467640Sgblack@eecs.umich.edu 1477640Sgblack@eecs.umich.edu static inline bool 1487640Sgblack@eecs.umich.edu vfpEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc) 1497640Sgblack@eecs.umich.edu { 1507640Sgblack@eecs.umich.edu return fpexc.en && vfpEnabled(cpacr, cpsr); 1517640Sgblack@eecs.umich.edu } 1527640Sgblack@eecs.umich.edu 1537640Sgblack@eecs.umich.edu static inline bool 1547640Sgblack@eecs.umich.edu neonEnabled(CPACR cpacr, CPSR cpsr, FPEXC fpexc) 1557640Sgblack@eecs.umich.edu { 1567640Sgblack@eecs.umich.edu return !cpacr.asedis && vfpEnabled(cpacr, cpsr, fpexc); 1577640Sgblack@eecs.umich.edu } 1587640Sgblack@eecs.umich.edu 1597707Sgblack@eecs.umich.eduuint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 1606759SAli.Saidi@ARM.com 1616759SAli.Saidi@ARM.comFault setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2); 1626759SAli.Saidi@ARM.comFault readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2); 1636757SAli.Saidi@ARM.com 1647693SAli.Saidi@ARM.comvoid skipFunction(ThreadContext *tc); 1657693SAli.Saidi@ARM.com 1666019Shines@cs.fsu.edu}; 1676019Shines@cs.fsu.edu 1686019Shines@cs.fsu.edu 1696019Shines@cs.fsu.edu#endif 170