utility.hh revision 7638
16019Shines@cs.fsu.edu/* 214169Sgiacomo.travaglini@arm.com * Copyright (c) 2010 ARM Limited 37111Sgblack@eecs.umich.edu * All rights reserved 47111Sgblack@eecs.umich.edu * 57111Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67111Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77111Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87111Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97111Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107111Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117111Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127111Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137111Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416019Shines@cs.fsu.edu * Authors: Korey Sewell 426019Shines@cs.fsu.edu * Stephen Hines 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu#ifndef __ARCH_ARM_UTILITY_HH__ 466019Shines@cs.fsu.edu#define __ARCH_ARM_UTILITY_HH__ 476019Shines@cs.fsu.edu 487692SAli.Saidi@ARM.com#include "arch/arm/miscregs.hh" 496242Sgblack@eecs.umich.edu#include "arch/arm/types.hh" 506019Shines@cs.fsu.edu#include "base/hashmap.hh" 5112334Sgabeblack@google.com#include "base/trace.hh" 527408Sgblack@eecs.umich.edu#include "base/types.hh" 536216Snate@binkert.org#include "cpu/thread_context.hh" 547720Sgblack@eecs.umich.edu 556019Shines@cs.fsu.edunamespace __hash_namespace { 566019Shines@cs.fsu.edu template<> 5710037SARM gem5 Developers struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> { 5810037SARM gem5 Developers size_t operator()(const ArmISA::ExtMachInst &emi) const { 596019Shines@cs.fsu.edu return hash<uint32_t>::operator()((uint32_t)emi); 606019Shines@cs.fsu.edu }; 617751SAli.Saidi@ARM.com }; 627751SAli.Saidi@ARM.com} 637751SAli.Saidi@ARM.com 647751SAli.Saidi@ARM.comnamespace ArmISA { 657751SAli.Saidi@ARM.com 667751SAli.Saidi@ARM.com inline bool 677751SAli.Saidi@ARM.com testPredicate(CPSR cpsr, ConditionCode code) 687751SAli.Saidi@ARM.com { 697751SAli.Saidi@ARM.com switch (code) 708303SAli.Saidi@ARM.com { 717751SAli.Saidi@ARM.com case COND_EQ: return cpsr.z; 728303SAli.Saidi@ARM.com case COND_NE: return !cpsr.z; 738303SAli.Saidi@ARM.com case COND_CS: return cpsr.c; 748303SAli.Saidi@ARM.com case COND_CC: return !cpsr.c; 757751SAli.Saidi@ARM.com case COND_MI: return cpsr.n; 767720Sgblack@eecs.umich.edu case COND_PL: return !cpsr.n; 778303SAli.Saidi@ARM.com case COND_VS: return cpsr.v; 788303SAli.Saidi@ARM.com case COND_VC: return !cpsr.v; 798303SAli.Saidi@ARM.com case COND_HI: return (cpsr.c && !cpsr.z); 808303SAli.Saidi@ARM.com case COND_LS: return !(cpsr.c && !cpsr.z); 818303SAli.Saidi@ARM.com case COND_GE: return !(cpsr.n ^ cpsr.v); 828303SAli.Saidi@ARM.com case COND_LT: return (cpsr.n ^ cpsr.v); 838303SAli.Saidi@ARM.com case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z); 848303SAli.Saidi@ARM.com case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z); 858303SAli.Saidi@ARM.com case COND_AL: return true; 868303SAli.Saidi@ARM.com case COND_UC: return true; 878303SAli.Saidi@ARM.com default: 888303SAli.Saidi@ARM.com panic("Unhandled predicate condition: %d\n", code); 898303SAli.Saidi@ARM.com } 908303SAli.Saidi@ARM.com } 917751SAli.Saidi@ARM.com 927751SAli.Saidi@ARM.com /** 937751SAli.Saidi@ARM.com * Function to insure ISA semantics about 0 registers. 947751SAli.Saidi@ARM.com * @param tc The thread context. 957720Sgblack@eecs.umich.edu */ 967751SAli.Saidi@ARM.com template <class TC> 977720Sgblack@eecs.umich.edu void zeroRegisters(TC *tc); 987751SAli.Saidi@ARM.com 997751SAli.Saidi@ARM.com inline void startupCPU(ThreadContext *tc, int cpuId) 1007751SAli.Saidi@ARM.com { 1017751SAli.Saidi@ARM.com tc->activate(0); 1027751SAli.Saidi@ARM.com } 1037751SAli.Saidi@ARM.com 1046242Sgblack@eecs.umich.edu template <class XC> 1057751SAli.Saidi@ARM.com Fault 1067751SAli.Saidi@ARM.com checkFpEnableFault(XC *xc) 10710407Smitch.hayenga@arm.com { 1087751SAli.Saidi@ARM.com return NoFault; 1096019Shines@cs.fsu.edu } 1107751SAli.Saidi@ARM.com 1116246Sgblack@eecs.umich.edu static inline void 1127751SAli.Saidi@ARM.com copyRegs(ThreadContext *src, ThreadContext *dest) 1137751SAli.Saidi@ARM.com { 1147751SAli.Saidi@ARM.com panic("Copy Regs Not Implemented Yet\n"); 1157751SAli.Saidi@ARM.com } 1167751SAli.Saidi@ARM.com 1176329Sgblack@eecs.umich.edu static inline void 1187751SAli.Saidi@ARM.com copyMiscRegs(ThreadContext *src, ThreadContext *dest) 1196757SAli.Saidi@ARM.com { 1207751SAli.Saidi@ARM.com panic("Copy Misc. Regs Not Implemented Yet\n"); 1217751SAli.Saidi@ARM.com } 1227751SAli.Saidi@ARM.com 12310037SARM gem5 Developers void initCPU(ThreadContext *tc, int cpuId); 1247751SAli.Saidi@ARM.com 1257638Sgblack@eecs.umich.edu static inline bool 1267751SAli.Saidi@ARM.com inUserMode(CPSR cpsr) 1277751SAli.Saidi@ARM.com { 1287751SAli.Saidi@ARM.com return cpsr.mode == MODE_USER; 1297751SAli.Saidi@ARM.com } 1307751SAli.Saidi@ARM.com 1317638Sgblack@eecs.umich.edu static inline bool 1327751SAli.Saidi@ARM.com inUserMode(ThreadContext *tc) 1337751SAli.Saidi@ARM.com { 1347751SAli.Saidi@ARM.com return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR)); 1357751SAli.Saidi@ARM.com } 1367751SAli.Saidi@ARM.com 1377638Sgblack@eecs.umich.edu static inline bool 1387751SAli.Saidi@ARM.com inPrivilegedMode(CPSR cpsr) 1397751SAli.Saidi@ARM.com { 1407751SAli.Saidi@ARM.com return !inUserMode(cpsr); 1417751SAli.Saidi@ARM.com } 1427751SAli.Saidi@ARM.com 1436757SAli.Saidi@ARM.com static inline bool 14410037SARM gem5 Developers inPrivilegedMode(ThreadContext *tc) 14510037SARM gem5 Developers { 14610037SARM gem5 Developers return !inUserMode(tc); 14710037SARM gem5 Developers } 1487751SAli.Saidi@ARM.com 14910037SARM gem5 Developersuint64_t getArgument(ThreadContext *tc, int number, bool fp); 15010037SARM gem5 Developers 1517751SAli.Saidi@ARM.comFault setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2); 1527640Sgblack@eecs.umich.eduFault readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2); 15310037SARM gem5 Developers 15410037SARM gem5 Developers}; 1557751SAli.Saidi@ARM.com 15614169Sgiacomo.travaglini@arm.com 1577751SAli.Saidi@ARM.com#endif 1587640Sgblack@eecs.umich.edu