utility.hh revision 7408
16019Shines@cs.fsu.edu/* 27111Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37111Sgblack@eecs.umich.edu * All rights reserved 47111Sgblack@eecs.umich.edu * 57111Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67111Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77111Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87111Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97111Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107111Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117111Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127111Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137111Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416019Shines@cs.fsu.edu * Authors: Korey Sewell 426019Shines@cs.fsu.edu * Stephen Hines 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu#ifndef __ARCH_ARM_UTILITY_HH__ 466019Shines@cs.fsu.edu#define __ARCH_ARM_UTILITY_HH__ 476019Shines@cs.fsu.edu 486242Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 496019Shines@cs.fsu.edu#include "arch/arm/types.hh" 506251Sgblack@eecs.umich.edu#include "base/hashmap.hh" 517408Sgblack@eecs.umich.edu#include "base/trace.hh" 526216Snate@binkert.org#include "base/types.hh" 536019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 546019Shines@cs.fsu.edu 556251Sgblack@eecs.umich.edunamespace __hash_namespace { 566251Sgblack@eecs.umich.edu template<> 576251Sgblack@eecs.umich.edu struct hash<ArmISA::ExtMachInst> : public hash<uint32_t> { 586251Sgblack@eecs.umich.edu size_t operator()(const ArmISA::ExtMachInst &emi) const { 596251Sgblack@eecs.umich.edu return hash<uint32_t>::operator()((uint32_t)emi); 606251Sgblack@eecs.umich.edu }; 616251Sgblack@eecs.umich.edu }; 626251Sgblack@eecs.umich.edu} 636251Sgblack@eecs.umich.edu 646019Shines@cs.fsu.edunamespace ArmISA { 656019Shines@cs.fsu.edu 666242Sgblack@eecs.umich.edu inline bool 676242Sgblack@eecs.umich.edu testPredicate(CPSR cpsr, ConditionCode code) 686242Sgblack@eecs.umich.edu { 696242Sgblack@eecs.umich.edu switch (code) 706242Sgblack@eecs.umich.edu { 716242Sgblack@eecs.umich.edu case COND_EQ: return cpsr.z; 726242Sgblack@eecs.umich.edu case COND_NE: return !cpsr.z; 736242Sgblack@eecs.umich.edu case COND_CS: return cpsr.c; 746242Sgblack@eecs.umich.edu case COND_CC: return !cpsr.c; 756242Sgblack@eecs.umich.edu case COND_MI: return cpsr.n; 766242Sgblack@eecs.umich.edu case COND_PL: return !cpsr.n; 776242Sgblack@eecs.umich.edu case COND_VS: return cpsr.v; 786242Sgblack@eecs.umich.edu case COND_VC: return !cpsr.v; 796242Sgblack@eecs.umich.edu case COND_HI: return (cpsr.c && !cpsr.z); 806242Sgblack@eecs.umich.edu case COND_LS: return !(cpsr.c && !cpsr.z); 816242Sgblack@eecs.umich.edu case COND_GE: return !(cpsr.n ^ cpsr.v); 826242Sgblack@eecs.umich.edu case COND_LT: return (cpsr.n ^ cpsr.v); 836242Sgblack@eecs.umich.edu case COND_GT: return !(cpsr.n ^ cpsr.v || cpsr.z); 846242Sgblack@eecs.umich.edu case COND_LE: return (cpsr.n ^ cpsr.v || cpsr.z); 856242Sgblack@eecs.umich.edu case COND_AL: return true; 867111Sgblack@eecs.umich.edu case COND_UC: return true; 876242Sgblack@eecs.umich.edu default: 886242Sgblack@eecs.umich.edu panic("Unhandled predicate condition: %d\n", code); 896242Sgblack@eecs.umich.edu } 906242Sgblack@eecs.umich.edu } 916242Sgblack@eecs.umich.edu 926019Shines@cs.fsu.edu /** 936019Shines@cs.fsu.edu * Function to insure ISA semantics about 0 registers. 946019Shines@cs.fsu.edu * @param tc The thread context. 956019Shines@cs.fsu.edu */ 966019Shines@cs.fsu.edu template <class TC> 976019Shines@cs.fsu.edu void zeroRegisters(TC *tc); 986019Shines@cs.fsu.edu 996019Shines@cs.fsu.edu // Instruction address compression hooks 1006019Shines@cs.fsu.edu static inline Addr realPCToFetchPC(const Addr &addr) { 1016019Shines@cs.fsu.edu return addr; 1026019Shines@cs.fsu.edu } 1036019Shines@cs.fsu.edu 1046019Shines@cs.fsu.edu static inline Addr fetchPCToRealPC(const Addr &addr) { 1056019Shines@cs.fsu.edu return addr; 1066019Shines@cs.fsu.edu } 1076019Shines@cs.fsu.edu 1086019Shines@cs.fsu.edu // the size of "fetched" instructions 1096019Shines@cs.fsu.edu static inline size_t fetchInstSize() { 1106019Shines@cs.fsu.edu return sizeof(MachInst); 1116019Shines@cs.fsu.edu } 1126019Shines@cs.fsu.edu 1136019Shines@cs.fsu.edu static inline MachInst makeRegisterCopy(int dest, int src) { 1146019Shines@cs.fsu.edu panic("makeRegisterCopy not implemented"); 1156019Shines@cs.fsu.edu return 0; 1166019Shines@cs.fsu.edu } 1176019Shines@cs.fsu.edu 1186019Shines@cs.fsu.edu inline void startupCPU(ThreadContext *tc, int cpuId) 1196019Shines@cs.fsu.edu { 1206019Shines@cs.fsu.edu tc->activate(0); 1216019Shines@cs.fsu.edu } 1226246Sgblack@eecs.umich.edu 1236246Sgblack@eecs.umich.edu template <class XC> 1246246Sgblack@eecs.umich.edu Fault 1256246Sgblack@eecs.umich.edu checkFpEnableFault(XC *xc) 1266246Sgblack@eecs.umich.edu { 1276246Sgblack@eecs.umich.edu return NoFault; 1286246Sgblack@eecs.umich.edu } 1296329Sgblack@eecs.umich.edu 1306329Sgblack@eecs.umich.edu static inline void 1316329Sgblack@eecs.umich.edu copyRegs(ThreadContext *src, ThreadContext *dest) 1326329Sgblack@eecs.umich.edu { 1336329Sgblack@eecs.umich.edu panic("Copy Regs Not Implemented Yet\n"); 1346329Sgblack@eecs.umich.edu } 1356329Sgblack@eecs.umich.edu 1366329Sgblack@eecs.umich.edu static inline void 1376329Sgblack@eecs.umich.edu copyMiscRegs(ThreadContext *src, ThreadContext *dest) 1386329Sgblack@eecs.umich.edu { 1396329Sgblack@eecs.umich.edu panic("Copy Misc. Regs Not Implemented Yet\n"); 1406329Sgblack@eecs.umich.edu } 1416757SAli.Saidi@ARM.com 1426757SAli.Saidi@ARM.com void initCPU(ThreadContext *tc, int cpuId); 1436757SAli.Saidi@ARM.com 1446757SAli.Saidi@ARM.com static inline bool 1456757SAli.Saidi@ARM.com inUserMode(ThreadContext *tc) 1466757SAli.Saidi@ARM.com { 1476757SAli.Saidi@ARM.com return (tc->readMiscRegNoEffect(MISCREG_CPSR) & 0x1f) == MODE_USER; 1486757SAli.Saidi@ARM.com } 1496757SAli.Saidi@ARM.com 1507189Sgblack@eecs.umich.edu static inline std::string 1517189Sgblack@eecs.umich.edu inst2string(MachInst machInst) 1527189Sgblack@eecs.umich.edu { 1537189Sgblack@eecs.umich.edu std::string str = ""; 1547189Sgblack@eecs.umich.edu uint32_t mask = (1 << 31); 1557189Sgblack@eecs.umich.edu 1567189Sgblack@eecs.umich.edu while (mask) { 1577189Sgblack@eecs.umich.edu str += ((machInst & mask) ? "1" : "0"); 1587189Sgblack@eecs.umich.edu mask = mask >> 1; 1597189Sgblack@eecs.umich.edu } 1607189Sgblack@eecs.umich.edu 1617189Sgblack@eecs.umich.edu return str; 1627189Sgblack@eecs.umich.edu } 1637189Sgblack@eecs.umich.edu 1646757SAli.Saidi@ARM.comuint64_t getArgument(ThreadContext *tc, int number, bool fp); 1656759SAli.Saidi@ARM.com 1666759SAli.Saidi@ARM.comFault setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2); 1676759SAli.Saidi@ARM.comFault readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2); 1686757SAli.Saidi@ARM.com 1696019Shines@cs.fsu.edu}; 1706019Shines@cs.fsu.edu 1716019Shines@cs.fsu.edu 1726019Shines@cs.fsu.edu#endif 173